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gcc: prevent the use of LDRD/STRD on ARMv5TE

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These instructions are for 64-bit load/store. On ARMv5TE, the CPU
requires addresses to be aligned to 64-bit. When misaligned, behavior is
undefined (effectively either loads the same word twice on LDRD, or
corrupts surrounding memory on STRD).

On ARMv6 and newer, unaligned access is safe.

Removing these instructions for ARMv5TE is necessary, because GCC
ignores alignment information in pointers and does unsafe optimizations
that have shown up as bugs in various places.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 39638
This commit is contained in:
Felix Fietkau 2014-02-19 19:20:10 +00:00
parent f433088d50
commit b050f87d13
3 changed files with 33 additions and 0 deletions
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11
toolchain/gcc/patches/4.6-linaro/800-arm_v5te_no_ldrd_strd.patch Normal file
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@ -0,0 +1,11 @@
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -232,7 +232,7 @@ extern void (*arm_lang_output_object_att
#define TARGET_BACKTRACE (leaf_function_p () \
? TARGET_TPCS_LEAF_FRAME \
: TARGET_TPCS_FRAME)
-#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
+#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN)
#define TARGET_AAPCS_BASED \
(arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)

11
toolchain/gcc/patches/4.8-linaro/800-arm_v5te_no_ldrd_strd.patch Normal file
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@ -0,0 +1,11 @@
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -271,7 +271,7 @@ extern void (*arm_lang_output_object_att
/* Thumb-1 only. */
#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
-#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \
+#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \
&& !TARGET_THUMB1)
/* The following two macros concern the ability to execute coprocessor

11
toolchain/gcc/patches/4.8.0/800-arm_v5te_no_ldrd_strd.patch Normal file
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@ -0,0 +1,11 @@
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -271,7 +271,7 @@ extern void (*arm_lang_output_object_att
/* Thumb-1 only. */
#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
-#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \
+#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \
&& !TARGET_THUMB1)
/* The following two macros concern the ability to execute coprocessor