parent
e83d637f65
commit
ac15780234
2 changed files with 11 additions and 7 deletions
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@ -50,10 +50,11 @@ static int __init mem_check_pattern(u8 *addr, unsigned long offs)
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u32 *p1 = (u32 *)addr;
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u32 *p2 = (u32 *)(addr+offs);
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u32 t,u,v;
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/* save original value */
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t = MEM_READL(p1);
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u = MEM_READL(p2);
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u = MEM_READL(p2);
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if (t != u)
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return 0;
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@ -64,10 +65,7 @@ static int __init mem_check_pattern(u8 *addr, unsigned long offs)
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mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1);
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MEM_WRITEL(p1, v);
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/* flush write buffers */
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MPMC_WRITE_REG(CTRL, MPMC_READ_REG(CTRL) | MPMC_CTRL_DWB);
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adm5120_ndelay(1000);
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u = MEM_READL(p2);
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mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u);
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@ -52,8 +52,14 @@
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#define MPMC_REG_SC3 0x0260
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/* Control register bits */
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#define MPMC_CTRL_AM ( 1 << 1 )
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#define MPMC_CTRL_DWB ( 1 << 3 )
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#define MPMC_CTRL_AM ( 1 << 1 ) /* Address Mirror */
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#define MPMC_CTRL_LPM ( 1 << 2 ) /* Low Power Mode */
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#define MPMC_CTRL_DWB ( 1 << 3 ) /* Drain Write Buffers */
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/* Status register bits */
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#define MPMC_STATUS_BUSY ( 1 << 0 ) /* Busy */
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#define MPMC_STATUS_WBS ( 1 << 1 ) /* Write Buffer Status */
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#define MPMC_STATUS_SRA ( 1 << 2 ) /* Self-Refresh Acknowledge*/
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/* Dynamic Control register bits */
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#define MPMC_DC_CE ( 1 << 0 )
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