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ramips: use gic timer as clocksource for mt7621

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* Switches clocksource to gic timer.
* Moves frequency definitions to dtsi since frequency was hardcoded anyway
  Will work on proper frequency detection later.

Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com>

SVN-Revision: 47843
This commit is contained in:
John Crispin 2015-12-11 15:03:39 +00:00
parent a87272ebfb
commit abd11be13c
3 changed files with 101 additions and 0 deletions
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14
target/linux/ramips/dts/mt7621.dtsi
View file

@ -88,6 +88,9 @@
compatible = "ns16550a";
reg = <0xc00 0x100>;
/* FIXME: there should be way to detect this */
clock-frequency = <50000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
@ -102,6 +105,9 @@
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
/* FIXME: there should be way to detect this */
clock-frequency = <50000000>;
resets = <&rstctrl 18>;
reset-names = "spi";
@ -243,6 +249,14 @@
#interrupt-cells = <3>;
mti,reserved-cpu-vectors = <7>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
/* FIXME: there should be way to detect this */
clock-frequency = <880000000>;
};
};
nand@1e003000 {

4
target/linux/ramips/mt7621/config-4.3
View file

@ -17,10 +17,13 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CEVT_R4K=y
# CONFIG_CEVT_SYSTICK_QUIRK is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_MIPS_GIC=y
CONFIG_CLKSRC_OF=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
@ -78,6 +81,7 @@ CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_BPF_JIT=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y

83
target/linux/ramips/patches-4.3/0902-mt7621-use-gic-timer.patch Normal file
View file

@ -0,0 +1,83 @@
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -52,6 +52,8 @@ choice
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_MIPS_CPS
select MIPS_GIC
+ select COMMON_CLK
+ select CLKSRC_MIPS_GIC
select HW_HAS_PCI
endchoice
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -6,14 +6,18 @@
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-obj-y := prom.o of.o reset.o clk.o timer.o
+obj-y := prom.o of.o reset.o
+
+ifndef CONFIG_MIPS_GIC
+ obj-y += clk.o timer.o
+endif
obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
obj-$(CONFIG_IRQ_INTC) += irq.o
-obj-$(CONFIG_MIPS_GIC) += irq-gic.o
+obj-$(CONFIG_MIPS_GIC) += irq-gic.o timer-gic.o
obj-$(CONFIG_SOC_RT288X) += rt288x.o
obj-$(CONFIG_SOC_RT305X) += rt305x.o
--- a/arch/mips/ralink/irq-gic.c
+++ b/arch/mips/ralink/irq-gic.c
@@ -3,13 +3,6 @@
#include <linux/of.h>
#include <linux/irqchip.h>
-#include <linux/irqchip/mips-gic.h>
-
-unsigned int get_c0_compare_int(void)
-{
- return gic_get_c0_compare_int();
-}
-
void __init
arch_init_irq(void)
{
--- /dev/null
+++ b/arch/mips/ralink/timer-gic.c
@@ -0,0 +1,13 @@
+#include <linux/init.h>
+
+#include <linux/of.h>
+#include <linux/clocksource.h>
+
+#include "common.h"
+
+void __init plat_time_init(void)
+{
+ ralink_of_remap();
+
+ clocksource_of_init();
+}
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -152,11 +152,14 @@ void __init ralink_clk_init(void)
}
break;
}
+ /*
+ FIXME: detect frequency automatically
cpu_clk = 880000000;
ralink_clk_add("cpu", cpu_clk);
ralink_clk_add("1e000b00.spi", 50000000);
ralink_clk_add("1e000c00.uartlite", 50000000);
ralink_clk_add("1e000d00.uart", 50000000);
+ */
}
void __init ralink_of_remap(void)