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sunxi: sun6i-a31 changes - push remaining sun6i patches for 3.13 - enable Colombus A31 devboard (compile-tested only)

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Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>

SVN-Revision: 39487
This commit is contained in:
Zoltan Herpai 2014-02-05 21:11:59 +00:00
parent 3f07af337c
commit a7f0eb013a
3 changed files with 79 additions and 0 deletions
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1
target/linux/sunxi/image/Makefile
View file

@ -12,6 +12,7 @@ BOARDS:= \
sun4i-a10-olinuxino-lime \
sun4i-a10-pcduino \
sun5i-a13-olinuxino \
sun6i-a31-colombus \
sun7i-a20-cubieboard2 \
sun7i-a20-cubietruck \
sun7i-a20-olinuxino-micro

36
target/linux/sunxi/patches-3.13/127-dt-sun6i-add-nodes-for-additional-cores.patch Normal file
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@ -0,0 +1,36 @@
From d3861805e84e1b54073e20dc499b9380b38bb7ab Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Sun, 3 Nov 2013 10:30:12 +0100
Subject: [PATCH] ARM: sun6i: dt: Add IP needed to bring up the additional
cores
Add the PRCM and CPU configuration units needed for SMP in the A31 DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 97966b0..5256ad9 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -322,5 +322,15 @@
#interrupt-cells = <3>;
interrupts = <1 9 0xf04>;
};
+
+ cpucfg@01f01c00 {
+ compatible = "allwinner,sun6i-a31-cpuconfig";
+ reg = <0x01f01c00 0x300>;
+ };
+
+ prcm@01f01c00 {
+ compatible = "allwinner,sun6i-a31-prcm";
+ reg = <0x01f01400 0x200>;
+ };
};
};
--
1.8.5.1

42
target/linux/sunxi/patches-3.13/146-4-dt-sun6i-a31-add-hstimer.patch Normal file
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@ -0,0 +1,42 @@
From 28a9c5d93113cab73dd3a4b4a74a983151c08b9d Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Fri, 20 Dec 2013 22:41:09 +0100
Subject: [PATCH] ARM: sun6i: a31: Add support for the High Speed Timers
The Allwinner A31 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.
Now that we have a driver to support it, we can enable them in the
device tree.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ab6ea43..4b97449 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -312,6 +312,17 @@
status = "disabled";
};
+ hstimer@01c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 51 4>,
+ <0 52 4>,
+ <0 53 4>,
+ <0 54 4>;
+ clocks = <&ahb1_gates 19>;
+ resets = <&ahb1_rst 19>;
+ };
+
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
1.8.5.1