ar71xx: add latch handling code for the RB750
SVN-Revision: 20050
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2 changed files with 104 additions and 0 deletions
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@ -9,10 +9,60 @@
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*/
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#include <asm/mach-ar71xx/ar71xx.h>
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#include <asm/mach-ar71xx/mach-rb750.h>
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#include "machtype.h"
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#include "dev-ap91-eth.h"
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int rb750_latch_change(u32 mask_clr, u32 mask_set)
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{
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static DEFINE_SPINLOCK(lock);
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static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE;
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static u32 latch_oe;
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static u32 latch_clr;
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unsigned long flags;
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u32 t;
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int ret = 0;
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spin_lock_irqsave(&lock, flags);
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if ((mask_clr & BIT(31)) != 0 &&
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(latch_set & RB750_LVC573_LE) == 0) {
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goto unlock;
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}
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latch_set = (latch_set | mask_set) & ~mask_clr;
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latch_clr = (latch_clr | mask_clr) & ~mask_set;
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if (latch_oe == 0)
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latch_oe = __raw_readl(ar71xx_gpio_base + GPIO_REG_OE);
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if (likely(latch_set & RB750_LVC573_LE)) {
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void __iomem *base = ar71xx_gpio_base;
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t = __raw_readl(base + GPIO_REG_OE);
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t |= mask_clr | latch_oe | mask_set;
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__raw_writel(t, base + GPIO_REG_OE);
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__raw_writel(latch_clr, base + GPIO_REG_CLEAR);
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__raw_writel(latch_set, base + GPIO_REG_SET);
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} else if (mask_clr & RB750_LVC573_LE) {
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void __iomem *base = ar71xx_gpio_base;
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latch_oe = __raw_readl(base + GPIO_REG_OE);
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__raw_writel(RB750_LVC573_LE, base + GPIO_REG_CLEAR);
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/* flush write */
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__raw_readl(base + GPIO_REG_CLEAR);
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}
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ret = 1;
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unlock:
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spin_unlock_irqrestore(&lock, flags);
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return ret;
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}
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EXPORT_SYMBOL_GPL(rb750_latch_change);
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static void __init rb750_setup(void)
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{
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ap91_eth_init(NULL);
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@ -0,0 +1,54 @@
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/*
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* MikroTik RouterBOARD 750 definitions
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*
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* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _MACH_RB750_H
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#define _MACH_RB750_H
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#include <linux/bitops.h>
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#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */
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#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */
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#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */
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#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */
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#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */
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#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */
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#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */
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#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */
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#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */
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#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */
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#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */
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#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */
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#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */
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#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */
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#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */
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#define RB750_GPIO_BTN_RESET 1
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#define RB750_GPIO_SPI_CS0 2
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#define RB750_GPIO_LED_ACT 12
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#define RB750_GPIO_LED_PORT1 13
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#define RB750_GPIO_LED_PORT2 14
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#define RB750_GPIO_LED_PORT3 15
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#define RB750_GPIO_LED_PORT4 16
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#define RB750_GPIO_LED_PORT5 17
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#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT)
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#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1)
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#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2)
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#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3)
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#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4)
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#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5)
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#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE)
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#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \
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RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT)
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int rb750_latch_change(u32 mask_clr, u32 mask_set);
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#endif /* _MACH_RB750_H */
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