bcm53xx: backport BCM5301X patches for SRAB
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
This commit is contained in:
Rafał Miłecki
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a180f90518
5 changed files with 170 additions and 1 deletions
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@ -1,5 +1,6 @@
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From 5f79985dcfec73d7a09ed99c40c28b64552518fe Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Date: Wed, 27 Apr 2016 08:58:01 +0200
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Date: Wed, 27 Apr 2016 09:05:03 +0200
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Subject: [PATCH] ARM: BCM5301X: Enable SPI-NOR on dual flash devices
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Subject: [PATCH] ARM: BCM5301X: Enable SPI-NOR on dual flash devices
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MIME-Version: 1.0
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Type: text/plain; charset=UTF-8
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@ -13,7 +14,14 @@ However there are also devices with two flash memories:
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On such devices we still need SPI-NOR e.g. to access NVRAM data.
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On such devices we still need SPI-NOR e.g. to access NVRAM data.
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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---
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arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 4 ++++
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arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 4 ++++
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arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 4 ++++
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arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 4 ++++
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arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 4 ++++
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5 files changed, 20 insertions(+)
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--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
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--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
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+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
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+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
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@ -0,0 +1,63 @@
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From 59f0ce1a3ebb9288fc8c1400aa503e923621161e Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <f.fainelli@gmail.com>
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Date: Mon, 23 May 2016 16:38:00 -0700
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Subject: [PATCH 1/3] ARM: dts: Enable SRAB switch and GMACs on 5301x DTS
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Add the Switch Register Access Block which is a special piece of
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hardware allowing us to perform indirect read/writes towards the
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integrated BCM5301X Ethernet switch.
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We also add the 4 Gigabit MAC Device Tree nodes within the brcm,bus-axi
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bus node to get proper binding between the BCMA instantiated core and
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the Device Tree nodes. We will need that to be able to reference
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Ethernet Device Tree nodes in a future patch adding the switch ports
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layout.
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm5301x.dtsi | 27 +++++++++++++++++++++++++++
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1 file changed, 27 insertions(+)
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -239,6 +239,22 @@
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status = "disabled";
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};
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};
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+
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+ gmac0: ethernet@24000 {
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+ reg = <0x24000 0x800>;
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+ };
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+
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+ gmac1: ethernet@25000 {
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+ reg = <0x25000 0x800>;
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+ };
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+
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+ gmac2: ethernet@26000 {
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+ reg = <0x26000 0x800>;
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+ };
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+
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+ gmac3: ethernet@27000 {
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+ reg = <0x27000 0x800>;
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+ };
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};
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lcpll0: lcpll0@1800c100 {
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@@ -260,6 +276,17 @@
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"sata2";
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};
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+ srab: srab@18007000 {
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+ compatible = "brcm,bcm5301x-srab";
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+ reg = <0x18007000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ status = "disabled";
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+
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+ /* ports are defined in board DTS */
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+ };
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+
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nand: nand@18028000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
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reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
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@ -0,0 +1,38 @@
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From 2cd0c0202f138fa95b3fbb027e87b191ad0b1884 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <f.fainelli@gmail.com>
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Date: Tue, 24 May 2016 11:41:58 -0700
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Subject: [PATCH 2/3] ARM: dts: BCM5301X: Add SRAB interrupts
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Add interrupt mapping for the Switch Register Access Block. Only 12
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interrupts are usable at the moment even though up to 32 are dedicated
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to the SRAB.
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm5301x.dtsi | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -153,6 +153,21 @@
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/* ChipCommon */
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<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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+ /* Switch Register Access Block */
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+ <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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+
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/* PCIe Controller 0 */
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<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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@ -0,0 +1,60 @@
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From 2df1808dc0e2b5358e13beb95192b15200017776 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <f.fainelli@gmail.com>
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Date: Wed, 25 May 2016 16:55:35 -0700
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Subject: [PATCH 3/3] ARM: dts: BCM5310x: Enable switch ports on SmartRG
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SR400AC
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Define the port mapping for the SmartRG SR400ACE device.
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 40 +++++++++++++++++++++++++++
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1 file changed, 40 insertions(+)
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--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
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+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
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@@ -126,3 +126,43 @@
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&spi_nor {
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status = "okay";
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};
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+
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+&srab {
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+ status = "okay";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "lan4";
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan3";
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan2";
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "lan1";
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ label = "wan";
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+ };
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+
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+ port@5 {
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+ reg = <5>;
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+ label = "cpu";
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+ ethernet = <&gmac0>;
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+ };
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+ };
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+};
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