KumiSystems/openwrtv4
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

update tg3 driver

Browse source 
SVN-Revision: 33004
This commit is contained in:
Hauke Mehrtens 2012-08-05 20:27:40 +00:00
parent 35661401da
commit a0fb060211
1 changed files with 128 additions and 75 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

201
target/linux/brcm47xx/patches-3.3/700-ssb-gigabit-ethernet-driver.patch
View file

@ -16,35 +16,38 @@
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
@@ -530,7 +532,8 @@ static void _tw32_flush(struct tg3 *tp, @@ -530,7 +532,9 @@ static void _tw32_flush(struct tg3 *tp,
static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
{ {
tp->write32_mbox(tp, off, val); tp->write32_mbox(tp, off, val);
- if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) - if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
+ if (tg3_flag(tp, FLUSH_POSTED_WRITES) || + if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
+ (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))) + (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
+ !tg3_flag(tp, ICH_WORKAROUND)))
tp->read32_mbox(tp, off); tp->read32_mbox(tp, off);
} }
@@ -540,7 +543,7 @@ static void tg3_write32_tx_mbox(struct t @@ -540,7 +544,8 @@ static void tg3_write32_tx_mbox(struct t
writel(val, mbox); writel(val, mbox);
if (tg3_flag(tp, TXD_MBOX_HWBUG)) if (tg3_flag(tp, TXD_MBOX_HWBUG))
writel(val, mbox); writel(val, mbox);
- if (tg3_flag(tp, MBOX_WRITE_REORDER)) - if (tg3_flag(tp, MBOX_WRITE_REORDER))
+ if (tg3_flag(tp, MBOX_WRITE_REORDER) || tg3_flag(tp, FLUSH_POSTED_WRITES)) + if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
+ tg3_flag(tp, FLUSH_POSTED_WRITES))
readl(mbox); readl(mbox);
} }
@@ -948,7 +951,7 @@ static void tg3_switch_clocks(struct tg3 @@ -948,7 +953,8 @@ static void tg3_switch_clocks(struct tg3
#define PHY_BUSY_LOOPS 5000 #define PHY_BUSY_LOOPS 5000
-static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
+static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val) +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
+ u32 *val)
{ {
u32 frame_val; u32 frame_val;
unsigned int loops; unsigned int loops;
@@ -962,7 +965,7 @@ static int tg3_readphy(struct tg3 *tp, i @@ -962,7 +968,7 @@ static int tg3_readphy(struct tg3 *tp, i
*val = 0x0; *val = 0x0;
@ -53,7 +56,7 @@
MI_COM_PHY_ADDR_MASK); MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
MI_COM_REG_ADDR_MASK); MI_COM_REG_ADDR_MASK);
@@ -997,7 +1000,12 @@ static int tg3_readphy(struct tg3 *tp, i @@ -997,7 +1003,13 @@ static int tg3_readphy(struct tg3 *tp, i
return ret; return ret;
} }
@ -63,11 +66,12 @@
+ return __tg3_readphy(tp, tp->phy_addr, reg, val); + return __tg3_readphy(tp, tp->phy_addr, reg, val);
+} +}
+ +
+static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val) +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
+ u32 val)
{ {
u32 frame_val; u32 frame_val;
unsigned int loops; unsigned int loops;
@@ -1013,7 +1021,7 @@ static int tg3_writephy(struct tg3 *tp, @@ -1013,7 +1025,7 @@ static int tg3_writephy(struct tg3 *tp,
udelay(80); udelay(80);
} }
@ -76,7 +80,7 @@
MI_COM_PHY_ADDR_MASK); MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
MI_COM_REG_ADDR_MASK); MI_COM_REG_ADDR_MASK);
@@ -1046,6 +1054,11 @@ static int tg3_writephy(struct tg3 *tp, @@ -1046,6 +1058,11 @@ static int tg3_writephy(struct tg3 *tp,
return ret; return ret;
} }
@ -88,7 +92,7 @@
static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
{ {
int err; int err;
@@ -1608,6 +1621,11 @@ static int tg3_poll_fw(struct tg3 *tp) @@ -1608,6 +1625,11 @@ static int tg3_poll_fw(struct tg3 *tp)
int i; int i;
u32 val; u32 val;
@ -100,7 +104,19 @@
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
/* Wait up to 20ms for init done. */ /* Wait up to 20ms for init done. */
for (i = 0; i < 200; i++) { for (i = 0; i < 200; i++) {
@@ -3029,9 +3047,12 @@ static int tg3_halt_cpu(struct tg3 *tp, @@ -3015,6 +3037,11 @@ static int tg3_halt_cpu(struct tg3 *tp,
tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
udelay(10);
} else {
+ /* There is only an Rx CPU for the 5750 derivative in the
+ * BCM4785. */
+ if (tg3_flag(tp, IS_SSB_CORE))
+ return 0;
+
for (i = 0; i < 10000; i++) {
tw32(offset + CPU_STATE, 0xffffffff);
tw32(offset + CPU_MODE, CPU_MODE_HALT);
@@ -3029,9 +3056,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
return -ENODEV; return -ENODEV;
} }
@ -116,7 +132,7 @@
return 0; return 0;
} }
@@ -3094,6 +3115,11 @@ static int tg3_load_5701_a0_firmware_fix @@ -3094,6 +3124,11 @@ static int tg3_load_5701_a0_firmware_fix
const __be32 *fw_data; const __be32 *fw_data;
int err, i; int err, i;
@ -128,7 +144,7 @@
fw_data = (void *)tp->fw->data; fw_data = (void *)tp->fw->data;
/* Firmware blob starts with version numbers, followed by /* Firmware blob starts with version numbers, followed by
@@ -3150,6 +3176,11 @@ static int tg3_load_tso_firmware(struct @@ -3150,6 +3185,11 @@ static int tg3_load_tso_firmware(struct
unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
int err, i; int err, i;
@ -140,21 +156,19 @@
if (tg3_flag(tp, HW_TSO_1) || if (tg3_flag(tp, HW_TSO_1) ||
tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_2) ||
tg3_flag(tp, HW_TSO_3)) tg3_flag(tp, HW_TSO_3))
@@ -3496,8 +3527,11 @@ static int tg3_power_down_prepare(struct @@ -3496,8 +3536,9 @@ static int tg3_power_down_prepare(struct
tg3_frob_aux_power(tp, true); tg3_frob_aux_power(tp, true);
/* Workaround for unstable PLL clock */ /* Workaround for unstable PLL clock */
- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || - if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { - (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
+ if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 && + if ((!tg3_flag(tp, IS_SSB_CORE)) &&
+ (tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_3 &&
+ /* !!! FIXME !!! */
+ ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || + ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) { + (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
u32 val = tr32(0x7d00); u32 val = tr32(0x7d00);
val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
@@ -4011,6 +4045,14 @@ relink: @@ -4011,6 +4052,14 @@ relink:
if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
tg3_phy_copper_begin(tp); tg3_phy_copper_begin(tp);
@ -169,14 +183,41 @@
tg3_readphy(tp, MII_BMSR, &bmsr); tg3_readphy(tp, MII_BMSR, &bmsr);
if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
@@ -7833,6 +7875,14 @@ static int tg3_chip_reset(struct tg3 *tp @@ -4029,6 +4078,26 @@ relink:
else
tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
+ /* In order for the 5750 core in BCM4785 chip to work properly
+ * in RGMII mode, the Led Control Register must be set up.
+ */
+ if (tg3_flag(tp, RGMII_MODE)) {
+ u32 led_ctrl = tr32(MAC_LED_CTRL);
+ led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
+
+ if (tp->link_config.active_speed == SPEED_10)
+ led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
+ else if (tp->link_config.active_speed == SPEED_100)
+ led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
+ LED_CTRL_100MBPS_ON);
+ else if (tp->link_config.active_speed == SPEED_1000)
+ led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
+ LED_CTRL_1000MBPS_ON);
+
+ tw32(MAC_LED_CTRL, led_ctrl);
+ udelay(40);
+ }
+
tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
if (tp->link_config.active_duplex == DUPLEX_HALF)
tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
@@ -7833,6 +7902,14 @@ static int tg3_chip_reset(struct tg3 *tp
tw32(0x5000, 0x400); tw32(0x5000, 0x400);
} }
+ if (tg3_flag(tp, IS_SSB_CORE)) { + if (tg3_flag(tp, IS_SSB_CORE)) {
+ /* BCM4785: In order to avoid repercussions from using potentially + /* BCM4785: In order to avoid repercussions from using
+ * defective internal ROM, stop the Rx RISC CPU, which is not + * potentially defective internal ROM, stop the Rx RISC CPU,
+ * required. */ + * which is not required. */
+ tg3_stop_fw(tp); + tg3_stop_fw(tp);
+ tg3_halt_cpu(tp, RX_CPU_BASE); + tg3_halt_cpu(tp, RX_CPU_BASE);
+ } + }
@ -184,7 +225,7 @@
tw32(GRC_MODE, tp->grc_mode); tw32(GRC_MODE, tp->grc_mode);
if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
@@ -9247,6 +9297,11 @@ static void tg3_timer(unsigned long __op @@ -9247,6 +9324,11 @@ static void tg3_timer(unsigned long __op
tg3_flag(tp, 57765_CLASS)) tg3_flag(tp, 57765_CLASS))
tg3_chk_missed_msi(tp); tg3_chk_missed_msi(tp);
@ -196,7 +237,7 @@
if (!tg3_flag(tp, TAGGED_STATUS)) { if (!tg3_flag(tp, TAGGED_STATUS)) {
/* All of this garbage is because when using non-tagged /* All of this garbage is because when using non-tagged
* IRQ status the mailbox/status_block protocol the chip * IRQ status the mailbox/status_block protocol the chip
@@ -10959,6 +11014,11 @@ static int tg3_test_nvram(struct tg3 *tp @@ -10959,6 +11041,11 @@ static int tg3_test_nvram(struct tg3 *tp
if (tg3_flag(tp, NO_NVRAM)) if (tg3_flag(tp, NO_NVRAM))
return 0; return 0;
@ -208,7 +249,7 @@
if (tg3_nvram_read(tp, 0, &magic) != 0) if (tg3_nvram_read(tp, 0, &magic) != 0)
return -EIO; return -EIO;
@@ -11916,11 +11976,11 @@ static int tg3_ioctl(struct net_device * @@ -11916,11 +12003,12 @@ static int tg3_ioctl(struct net_device *
if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
break; /* We have no PHY */ break; /* We have no PHY */
@ -218,11 +259,12 @@
spin_lock_bh(&tp->lock); spin_lock_bh(&tp->lock);
- err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); - err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
+ err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval); + err = __tg3_readphy(tp, data->phy_id & 0x1f,
+ data->reg_num & 0x1f, &mii_regval);
spin_unlock_bh(&tp->lock); spin_unlock_bh(&tp->lock);
data->val_out = mii_regval; data->val_out = mii_regval;
@@ -11932,11 +11992,11 @@ static int tg3_ioctl(struct net_device * @@ -11932,11 +12020,12 @@ static int tg3_ioctl(struct net_device *
if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
break; /* We have no PHY */ break; /* We have no PHY */
@ -232,11 +274,12 @@
spin_lock_bh(&tp->lock); spin_lock_bh(&tp->lock);
- err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); - err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
+ err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); + err = __tg3_writephy(tp, data->phy_id & 0x1f,
+ data->reg_num & 0x1f, data->val_in);
spin_unlock_bh(&tp->lock); spin_unlock_bh(&tp->lock);
return err; return err;
@@ -12670,6 +12730,13 @@ static void __devinit tg3_get_5720_nvram @@ -12670,6 +12759,13 @@ static void __devinit tg3_get_5720_nvram
/* Chips other than 5700/5701 use the NVRAM for fetching info. */ /* Chips other than 5700/5701 use the NVRAM for fetching info. */
static void __devinit tg3_nvram_init(struct tg3 *tp) static void __devinit tg3_nvram_init(struct tg3 *tp)
{ {
@ -250,7 +293,7 @@
tw32_f(GRC_EEPROM_ADDR, tw32_f(GRC_EEPROM_ADDR,
(EEPROM_ADDR_FSM_RESET | (EEPROM_ADDR_FSM_RESET |
(EEPROM_DEFAULT_CLOCK_PERIOD << (EEPROM_DEFAULT_CLOCK_PERIOD <<
@@ -12936,6 +13003,9 @@ static int tg3_nvram_write_block(struct @@ -12936,6 +13032,9 @@ static int tg3_nvram_write_block(struct
{ {
int ret; int ret;
@ -260,7 +303,29 @@
if (tg3_flag(tp, EEPROM_WRITE_PROT)) { if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
~GRC_LCLCTRL_GPIO_OUTPUT1); ~GRC_LCLCTRL_GPIO_OUTPUT1);
@@ -14382,6 +14452,11 @@ static int __devinit tg3_get_invariants( @@ -13394,10 +13493,19 @@ static int __devinit tg3_phy_probe(struc
* subsys device table.
*/
p = tg3_lookup_by_subsys(tp);
- if (!p)
+ if (p) {
+ tp->phy_id = p->phy_id;
+ } else if (!tg3_flag(tp, IS_SSB_CORE)) {
+ /* For now we saw the IDs 0xbc050cd0,
+ * 0xbc050f80 and 0xbc050c30 on devices
+ * connected to an BCM4785 and there are
+ * probably more. Just assume that the phy is
+ * supported when it is connected to a SSB core
+ * for now.
+ */
return -ENODEV;
+ }
- tp->phy_id = p->phy_id;
if (!tp->phy_id ||
tp->phy_id == TG3_PHY_ID_BCM8002)
tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
@@ -14382,6 +14490,11 @@ static int __devinit tg3_get_invariants(
} }
} }
@ -272,7 +337,7 @@
/* Get eeprom hw config before calling tg3_set_power_state(). /* Get eeprom hw config before calling tg3_set_power_state().
* In particular, the TG3_FLAG_IS_NIC flag must be * In particular, the TG3_FLAG_IS_NIC flag must be
* determined before calling tg3_set_power_state() so that * determined before calling tg3_set_power_state() so that
@@ -14798,6 +14873,10 @@ static int __devinit tg3_get_device_addr @@ -14798,6 +14911,10 @@ static int __devinit tg3_get_device_addr
} }
if (!is_valid_ether_addr(&dev->dev_addr[0])) { if (!is_valid_ether_addr(&dev->dev_addr[0])) {
@ -283,16 +348,17 @@
#ifdef CONFIG_SPARC #ifdef CONFIG_SPARC
if (!tg3_get_default_macaddr_sparc(tp)) if (!tg3_get_default_macaddr_sparc(tp))
return 0; return 0;
@@ -15296,6 +15375,8 @@ static char * __devinit tg3_phy_string(s @@ -15082,7 +15199,8 @@ static int __devinit tg3_test_dma(struct
case TG3_PHY_ID_BCM5704: return "5704"; if (tg3_flag(tp, 40BIT_DMA_BUG) &&
case TG3_PHY_ID_BCM5705: return "5705"; GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
case TG3_PHY_ID_BCM5750: return "5750"; tp->dma_rwctrl |= 0x8000;
+ case TG3_PHY_ID_BCM5750_2: return "5750-2"; - else if (ccval == 0x6 || ccval == 0x7)
+ case TG3_PHY_ID_BCM5750_3: return "5750-3"; + else if ((ccval == 0x6 || ccval == 0x7) ||
case TG3_PHY_ID_BCM5752: return "5752"; + tg3_flag(tp, ONE_DMA_AT_ONCE))
case TG3_PHY_ID_BCM5714: return "5714"; tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
case TG3_PHY_ID_BCM5780: return "5780";
@@ -15506,6 +15587,13 @@ static int __devinit tg3_init_one(struct if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
@@ -15506,6 +15624,17 @@ static int __devinit tg3_init_one(struct
tp->msg_enable = tg3_debug; tp->msg_enable = tg3_debug;
else else
tp->msg_enable = TG3_DEF_MSG_ENABLE; tp->msg_enable = TG3_DEF_MSG_ENABLE;
@ -300,43 +366,40 @@
+ tg3_flag_set(tp, IS_SSB_CORE); + tg3_flag_set(tp, IS_SSB_CORE);
+ if (ssb_gige_must_flush_posted_writes(pdev)) + if (ssb_gige_must_flush_posted_writes(pdev))
+ tg3_flag_set(tp, FLUSH_POSTED_WRITES); + tg3_flag_set(tp, FLUSH_POSTED_WRITES);
+ if (ssb_gige_one_dma_at_once(pdev))
+ tg3_flag_set(tp, ONE_DMA_AT_ONCE);
+ if (ssb_gige_have_roboswitch(pdev)) + if (ssb_gige_have_roboswitch(pdev))
+ tg3_flag_set(tp, ROBOSWITCH); + tg3_flag_set(tp, ROBOSWITCH);
+ if (ssb_gige_is_rgmii(pdev))
+ tg3_flag_set(tp, RGMII_MODE);
+ } + }
/* The word/byte swap controls here control register access byte /* The word/byte swap controls here control register access byte
* swapping. DMA data byte swapping is controlled in the GRC_MODE * swapping. DMA data byte swapping is controlled in the GRC_MODE
--- a/drivers/net/ethernet/broadcom/tg3.h --- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -2940,6 +2940,9 @@ enum TG3_FLAGS { @@ -2940,6 +2940,11 @@ enum TG3_FLAGS {
TG3_FLAG_57765_PLUS, TG3_FLAG_57765_PLUS,
TG3_FLAG_57765_CLASS, TG3_FLAG_57765_CLASS,
TG3_FLAG_5717_PLUS, TG3_FLAG_5717_PLUS,
+ TG3_FLAG_IS_SSB_CORE, + TG3_FLAG_IS_SSB_CORE,
+ TG3_FLAG_FLUSH_POSTED_WRITES, + TG3_FLAG_FLUSH_POSTED_WRITES,
+ TG3_FLAG_ROBOSWITCH, + TG3_FLAG_ROBOSWITCH,
+ TG3_FLAG_ONE_DMA_AT_ONCE,
+ TG3_FLAG_RGMII_MODE,
/* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */ /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */ TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
@@ -3089,6 +3092,8 @@ struct tg3 { --- a/include/linux/pci_ids.h
#define TG3_PHY_ID_BCM5704 0x60008190 +++ b/include/linux/pci_ids.h
#define TG3_PHY_ID_BCM5705 0x600081a0 @@ -2120,6 +2120,7 @@
#define TG3_PHY_ID_BCM5750 0x60008180 #define PCI_DEVICE_ID_TIGON3_5754M 0x1672
+#define TG3_PHY_ID_BCM5750_2 0xbc050cd0 #define PCI_DEVICE_ID_TIGON3_5755M 0x1673
+#define TG3_PHY_ID_BCM5750_3 0xbc050f80 #define PCI_DEVICE_ID_TIGON3_5756 0x1674
#define TG3_PHY_ID_BCM5752 0x60008100 +#define PCI_DEVICE_ID_TIGON3_5750 0x1676
#define TG3_PHY_ID_BCM5714 0x60008340 #define PCI_DEVICE_ID_TIGON3_5751 0x1677
#define TG3_PHY_ID_BCM5780 0x60008350 #define PCI_DEVICE_ID_TIGON3_5715 0x1678
@@ -3126,7 +3131,8 @@ struct tg3 { #define PCI_DEVICE_ID_TIGON3_5715S 0x1679
(X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
(X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
(X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
- (X) == TG3_PHY_ID_BCM8002)
+ (X) == TG3_PHY_ID_BCM8002 || (X) == TG3_PHY_ID_BCM5750_2 || \
+ (X) == TG3_PHY_ID_BCM5750_3)
u32 phy_flags;
#define TG3_PHYFLG_IS_LOW_POWER 0x00000001
--- a/include/linux/ssb/ssb_driver_gige.h --- a/include/linux/ssb/ssb_driver_gige.h
+++ b/include/linux/ssb/ssb_driver_gige.h +++ b/include/linux/ssb/ssb_driver_gige.h
@@ -97,21 +97,12 @@ static inline bool ssb_gige_must_flush_p @@ -97,21 +97,12 @@ static inline bool ssb_gige_must_flush_p
@ -374,13 +437,3 @@
#endif /* CONFIG_SSB_DRIVER_GIGE */ #endif /* CONFIG_SSB_DRIVER_GIGE */
#endif /* LINUX_SSB_DRIVER_GIGE_H_ */ #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2120,6 +2120,7 @@
#define PCI_DEVICE_ID_TIGON3_5754M 0x1672
#define PCI_DEVICE_ID_TIGON3_5755M 0x1673
#define PCI_DEVICE_ID_TIGON3_5756 0x1674
+#define PCI_DEVICE_ID_TIGON3_5750 0x1676
#define PCI_DEVICE_ID_TIGON3_5751 0x1677
#define PCI_DEVICE_ID_TIGON3_5715 0x1678
#define PCI_DEVICE_ID_TIGON3_5715S 0x1679