imx6: kernel: add GW16082 miniPCI Expansion Mezzanine support
The GW16082 miniPCI Expansion Mezzanine has the INTA/B/C/D IRQ's reversed from the PCI standard. This will soon be resolved in the bootloader via devicetree, but in the meantime this will work around the issue. Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 42146
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commit e84634dc6c7f3f6af9b8ef1fb36f0d85c476ab95
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Author: Tim Harvey <tharvey@gateworks.com>
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Date: Thu Feb 27 01:02:23 2014 -0800
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PCI: designware: add ability for custom swizzle
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Add the ability for a platform driver to provide a platform-specific
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swizzle function.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -481,6 +481,9 @@ int __init dw_pcie_host_init(struct pcie
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if (pp->ops->host_init)
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pp->ops->host_init(pp);
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+ if (pp->swizzle)
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+ dw_pci.swizzle = pp->swizzle;
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+
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dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
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/* program correct class for RC */
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--- a/drivers/pci/host/pcie-designware.h
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+++ b/drivers/pci/host/pcie-designware.h
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@@ -53,6 +53,7 @@ struct pcie_port {
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struct irq_domain *irq_domain;
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unsigned long msi_data;
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DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
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+ u8 (*swizzle)(struct pci_dev *, u8 *);
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};
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struct pcie_host_ops {
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@ -0,0 +1,81 @@
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commit 2c0d0491438433a1f327f2e754c7b6b55fec51c4
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Author: Tim Harvey <tharvey@gateworks.com>
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Date: Thu Feb 27 00:59:53 2014 -0800
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PCI: imx6: ventana: fixup for IRQ mismapping
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The TI XIO2001 PCIe-to-PCI bridge used on several Ventana expansion boards
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has its slot-to-bridge IRQ mapping reversed from the PCI specification:
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INTA->INTD
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INTB->INTC
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INTC->INTB
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INTD->INTA
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Implement a custom swizzle function that does a fixup on the interrupt for
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devices on a TI XIO2001 bridge.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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--- a/drivers/pci/host/pci-imx6.c
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+++ b/drivers/pci/host/pci-imx6.c
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@@ -540,6 +540,39 @@ static int imx6_add_pcie_port(struct pci
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return 0;
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}
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+/* TI XIO2001 PCIe-to-PCI bridge on GW16082 exp card has IRQs reversed */
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+u8 ventana_swizzle(struct pci_dev *dev, u8 *pin)
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+{
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+ u8 i = 0;
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+ struct pci_dev *pdev = dev;
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+
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+ /* count number of TI XIO2001 bridges on bus */
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+ while (!pci_is_root_bus(pdev->bus)) {
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+ if (pdev->bus && pdev->bus->self &&
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+ (pdev->bus->self->vendor == PCI_VENDOR_ID_TI) &&
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+ (pdev->bus->self->device == PCI_DEVICE_ID_TI_XIO2001)) {
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+ i++;
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+ }
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+ pdev = pdev->bus->self;
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+ }
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+ while (!pci_is_root_bus(dev->bus)) {
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+ /* if we are directly downstream from 1st TI XIO2001 bridge */
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+ if (dev->bus && dev->bus->self &&
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+ (dev->bus->self->vendor == PCI_VENDOR_ID_TI) &&
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+ (dev->bus->self->device == PCI_DEVICE_ID_TI_XIO2001)) {
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+ if (--i == 0) {
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+ /* swap IRQs and swizzle backwards */
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+ *pin = (15 - PCI_SLOT(dev->devfn)) + 1;
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+ dev = dev->bus->self;
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+ continue;
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+ }
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+ }
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+ *pin = pci_swizzle_interrupt_pin(dev, *pin);
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+ dev = dev->bus->self;
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+ }
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+ return PCI_SLOT(dev->devfn);
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+}
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+
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static int __init imx6_pcie_probe(struct platform_device *pdev)
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{
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struct imx6_pcie *imx6_pcie;
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@@ -648,6 +681,9 @@ static int __init imx6_pcie_probe(struct
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return PTR_ERR(imx6_pcie->iomuxc_gpr);
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}
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+ if (of_machine_is_compatible("gw,ventana"))
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+ pp->swizzle = ventana_swizzle;
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+
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ret = imx6_add_pcie_port(pp, pdev);
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if (ret < 0)
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return ret;
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--- a/include/linux/pci_ids.h
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+++ b/include/linux/pci_ids.h
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@@ -822,6 +822,7 @@
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#define PCI_DEVICE_ID_TI_XX12 0x8039
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#define PCI_DEVICE_ID_TI_XX12_FM 0x803b
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#define PCI_DEVICE_ID_TI_XIO2000A 0x8231
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+#define PCI_DEVICE_ID_TI_XIO2001 0x8240
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#define PCI_DEVICE_ID_TI_1130 0xac12
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#define PCI_DEVICE_ID_TI_1031 0xac13
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#define PCI_DEVICE_ID_TI_1131 0xac15
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