bcm53xx: add upstream patch fixing SPI controller driver
That patch fixes handling SPI messages with two writing transfers. It's important when using e.g. by m25p80 driver which uses one transfer for opcode and another one for data. Thanks to that fix we can now drop m25p80 workaround patch. It means one less hack and also a better flash writing performance as there is no more data buf copying. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
This commit is contained in:
Rafał Miłecki
parent
d40a358136
commit
9c312ef628
4 changed files with 214 additions and 127 deletions
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@ -0,0 +1,107 @@
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Fri, 29 Dec 2017 14:44:09 +0100
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Subject: [PATCH] spi: bcm53xx: simplify reading SPI data
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit makes transfer function use spi_transfer_is_last to
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determine if currently processed transfer is the last one. Thanks to
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that we finally set hardware registers properly and it makes controller
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behave the way it's expected to.
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This allows simplifying read function which can now simply start reading
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from the slot 0 instead of the last saved offset. It has been
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successfully tested using spi_write_then_read.
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Moreover this change fixes handling messages with two writing transfers.
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It's important for SPI flash devices as their drivers commonly use one
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transfer for a command and another one for data.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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drivers/spi/spi-bcm53xx.c | 26 ++++++++++----------------
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1 file changed, 10 insertions(+), 16 deletions(-)
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--- a/drivers/spi/spi-bcm53xx.c
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+++ b/drivers/spi/spi-bcm53xx.c
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@@ -27,8 +27,6 @@ struct bcm53xxspi {
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struct bcma_device *core;
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struct spi_master *master;
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void __iomem *mmio_base;
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-
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- size_t read_offset;
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bool bspi; /* Boot SPI mode with memory mapping */
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};
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@@ -172,8 +170,6 @@ static void bcm53xxspi_buf_write(struct
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if (!cont)
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bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
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-
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- b53spi->read_offset = len;
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}
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static void bcm53xxspi_buf_read(struct bcm53xxspi *b53spi, u8 *r_buf,
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@@ -182,10 +178,10 @@ static void bcm53xxspi_buf_read(struct b
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u32 tmp;
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int i;
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- for (i = 0; i < b53spi->read_offset + len; i++) {
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+ for (i = 0; i < len; i++) {
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tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
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B53SPI_CDRAM_PCS_DSCK;
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- if (!cont && i == b53spi->read_offset + len - 1)
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+ if (!cont && i == len - 1)
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tmp &= ~B53SPI_CDRAM_CONT;
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tmp &= ~0x1;
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/* Command Register File */
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@@ -194,8 +190,7 @@ static void bcm53xxspi_buf_read(struct b
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/* Set queue pointers */
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bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
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- bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP,
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- b53spi->read_offset + len - 1);
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1);
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if (cont)
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bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
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@@ -214,13 +209,11 @@ static void bcm53xxspi_buf_read(struct b
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bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
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for (i = 0; i < len; ++i) {
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- int offset = b53spi->read_offset + i;
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+ u16 reg = B53SPI_MSPI_RXRAM + 4 * (1 + i * 2);
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/* Data stored in the transmit register file LSB */
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- r_buf[i] = (u8)bcm53xxspi_read(b53spi, B53SPI_MSPI_RXRAM + 4 * (1 + offset * 2));
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+ r_buf[i] = (u8)bcm53xxspi_read(b53spi, reg);
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}
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-
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- b53spi->read_offset = 0;
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}
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static int bcm53xxspi_transfer_one(struct spi_master *master,
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@@ -238,7 +231,8 @@ static int bcm53xxspi_transfer_one(struc
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left = t->len;
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while (left) {
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size_t to_write = min_t(size_t, 16, left);
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- bool cont = left - to_write > 0;
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+ bool cont = !spi_transfer_is_last(master, t) ||
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+ left - to_write > 0;
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bcm53xxspi_buf_write(b53spi, buf, to_write, cont);
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left -= to_write;
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@@ -250,9 +244,9 @@ static int bcm53xxspi_transfer_one(struc
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buf = (u8 *)t->rx_buf;
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left = t->len;
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while (left) {
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- size_t to_read = min_t(size_t, 16 - b53spi->read_offset,
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- left);
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- bool cont = left - to_read > 0;
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+ size_t to_read = min_t(size_t, 16, left);
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+ bool cont = !spi_transfer_is_last(master, t) ||
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+ left - to_read > 0;
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bcm53xxspi_buf_read(b53spi, buf, to_read, cont);
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left -= to_read;
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@ -1,59 +0,0 @@
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Subject: [PATCH] mtd: m25p80: use single SPI message for writing data
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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On all 3 tested Northstar devices with following flash memories:
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mx25l6405d (8192 Kbytes)
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mx25l12805d (16384 Kbytes)
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mx25l25635e (32768 Kbytes)
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I noticed writing to be broken. Not a single bit was changed leaving all
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bytes set to 0xff.
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This is most likely some problem related to the SPI controller or its
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driver. Using a single SPI message seems to workaround this. Of course
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it's not perfect solution as copying whole data into a new buffer makes
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writing slower.
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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---
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--- a/drivers/mtd/devices/m25p80.c
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+++ b/drivers/mtd/devices/m25p80.c
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@@ -78,6 +78,7 @@ static void m25p80_write(struct spi_nor
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{
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struct m25p *flash = nor->priv;
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struct spi_device *spi = flash->spi;
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+ u8 *command = kzalloc(MAX_CMD_SIZE + len, GFP_KERNEL);
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struct spi_transfer t[2] = {};
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struct spi_message m;
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int cmd_sz = m25p_cmdsz(nor);
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@@ -87,20 +88,19 @@ static void m25p80_write(struct spi_nor
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if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
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cmd_sz = 1;
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- flash->command[0] = nor->program_opcode;
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- m25p_addr2cmd(nor, to, flash->command);
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+ command[0] = nor->program_opcode;
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+ m25p_addr2cmd(nor, to, command);
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+ memcpy(&command[cmd_sz], buf, len);
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- t[0].tx_buf = flash->command;
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- t[0].len = cmd_sz;
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+ t[0].tx_buf = command;
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+ t[0].len = cmd_sz + len;
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spi_message_add_tail(&t[0], &m);
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- t[1].tx_buf = buf;
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- t[1].len = len;
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- spi_message_add_tail(&t[1], &m);
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-
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spi_sync(spi, &m);
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*retlen += m.actual_length - cmd_sz;
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+
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+ kfree(command);
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}
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static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
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@ -0,0 +1,107 @@
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Fri, 29 Dec 2017 14:44:09 +0100
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Subject: [PATCH] spi: bcm53xx: simplify reading SPI data
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit makes transfer function use spi_transfer_is_last to
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determine if currently processed transfer is the last one. Thanks to
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that we finally set hardware registers properly and it makes controller
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behave the way it's expected to.
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This allows simplifying read function which can now simply start reading
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from the slot 0 instead of the last saved offset. It has been
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successfully tested using spi_write_then_read.
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Moreover this change fixes handling messages with two writing transfers.
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It's important for SPI flash devices as their drivers commonly use one
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transfer for a command and another one for data.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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drivers/spi/spi-bcm53xx.c | 26 ++++++++++----------------
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1 file changed, 10 insertions(+), 16 deletions(-)
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--- a/drivers/spi/spi-bcm53xx.c
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+++ b/drivers/spi/spi-bcm53xx.c
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@@ -27,8 +27,6 @@ struct bcm53xxspi {
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struct bcma_device *core;
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struct spi_master *master;
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void __iomem *mmio_base;
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-
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- size_t read_offset;
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bool bspi; /* Boot SPI mode with memory mapping */
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};
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@@ -172,8 +170,6 @@ static void bcm53xxspi_buf_write(struct
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if (!cont)
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bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
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-
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- b53spi->read_offset = len;
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}
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static void bcm53xxspi_buf_read(struct bcm53xxspi *b53spi, u8 *r_buf,
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@@ -182,10 +178,10 @@ static void bcm53xxspi_buf_read(struct b
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u32 tmp;
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int i;
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- for (i = 0; i < b53spi->read_offset + len; i++) {
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+ for (i = 0; i < len; i++) {
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tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
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B53SPI_CDRAM_PCS_DSCK;
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- if (!cont && i == b53spi->read_offset + len - 1)
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+ if (!cont && i == len - 1)
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tmp &= ~B53SPI_CDRAM_CONT;
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tmp &= ~0x1;
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/* Command Register File */
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@@ -194,8 +190,7 @@ static void bcm53xxspi_buf_read(struct b
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/* Set queue pointers */
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bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
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- bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP,
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- b53spi->read_offset + len - 1);
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+ bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1);
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if (cont)
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bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
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@@ -214,13 +209,11 @@ static void bcm53xxspi_buf_read(struct b
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bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
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for (i = 0; i < len; ++i) {
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- int offset = b53spi->read_offset + i;
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+ u16 reg = B53SPI_MSPI_RXRAM + 4 * (1 + i * 2);
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/* Data stored in the transmit register file LSB */
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- r_buf[i] = (u8)bcm53xxspi_read(b53spi, B53SPI_MSPI_RXRAM + 4 * (1 + offset * 2));
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+ r_buf[i] = (u8)bcm53xxspi_read(b53spi, reg);
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}
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-
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- b53spi->read_offset = 0;
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}
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static int bcm53xxspi_transfer_one(struct spi_master *master,
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@@ -238,7 +231,8 @@ static int bcm53xxspi_transfer_one(struc
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left = t->len;
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while (left) {
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size_t to_write = min_t(size_t, 16, left);
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- bool cont = left - to_write > 0;
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+ bool cont = !spi_transfer_is_last(master, t) ||
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+ left - to_write > 0;
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bcm53xxspi_buf_write(b53spi, buf, to_write, cont);
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left -= to_write;
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@@ -250,9 +244,9 @@ static int bcm53xxspi_transfer_one(struc
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buf = (u8 *)t->rx_buf;
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left = t->len;
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while (left) {
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- size_t to_read = min_t(size_t, 16 - b53spi->read_offset,
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- left);
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- bool cont = left - to_read > 0;
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+ size_t to_read = min_t(size_t, 16, left);
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+ bool cont = !spi_transfer_is_last(master, t) ||
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+ left - to_read > 0;
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bcm53xxspi_buf_read(b53spi, buf, to_read, cont);
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left -= to_read;
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@ -1,68 +0,0 @@
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Subject: [PATCH] mtd: m25p80: use single SPI message for writing data
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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||||
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On all 3 tested Northstar devices with following flash memories:
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mx25l6405d (8192 Kbytes)
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mx25l12805d (16384 Kbytes)
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mx25l25635e (32768 Kbytes)
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I noticed writing to be broken. Not a single bit was changed leaving all
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bytes set to 0xff.
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This is most likely some problem related to the SPI controller or its
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driver. Using a single SPI message seems to workaround this. Of course
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it's not perfect solution as copying whole data into a new buffer makes
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writing slower.
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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---
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--- a/drivers/mtd/devices/m25p80.c
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+++ b/drivers/mtd/devices/m25p80.c
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@@ -78,6 +78,7 @@ static ssize_t m25p80_write(struct spi_n
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{
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struct m25p *flash = nor->priv;
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struct spi_device *spi = flash->spi;
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+ u8 *command = kzalloc(MAX_CMD_SIZE + len, GFP_KERNEL);
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struct spi_transfer t[2] = {};
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struct spi_message m;
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int cmd_sz = m25p_cmdsz(nor);
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@@ -88,24 +89,26 @@ static ssize_t m25p80_write(struct spi_n
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if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
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cmd_sz = 1;
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- flash->command[0] = nor->program_opcode;
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- m25p_addr2cmd(nor, to, flash->command);
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+ command[0] = nor->program_opcode;
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+ m25p_addr2cmd(nor, to, command);
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+ memcpy(&command[cmd_sz], buf, len);
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- t[0].tx_buf = flash->command;
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- t[0].len = cmd_sz;
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+ t[0].tx_buf = command;
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+ t[0].len = cmd_sz + len;
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spi_message_add_tail(&t[0], &m);
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- t[1].tx_buf = buf;
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- t[1].len = len;
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- spi_message_add_tail(&t[1], &m);
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-
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ret = spi_sync(spi, &m);
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- if (ret)
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+ if (ret) {
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+ kfree(command);
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return ret;
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+ }
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ret = m.actual_length - cmd_sz;
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- if (ret < 0)
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+ if (ret < 0) {
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+ kfree(command);
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return -EIO;
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+ }
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+ kfree(command);
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return ret;
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}
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