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uboot-lantiq: vrx200 - add support for dual nor flash

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Based on a submission to the uboot-lantiq repo by Eddi De Pieri.

Devices like the xrx200 Arcadyan VGV7519 are using two NOR flash chips.

Signed-off-by: Mathias Kresin <dev@kresin.me>
This commit is contained in:
Mathias Kresin 2016-05-26 23:08:25 +02:00 committed by John Crispin
parent a9f7586ad2
commit 8df4eb0b9b
2 changed files with 30 additions and 12 deletions
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40
package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch
View file

@ -2381,7 +2381,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+}
--- /dev/null
+++ b/arch/mips/cpu/mips32/vrx200/ebu.c
@@ -0,0 +1,111 @@
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
@ -2424,7 +2424,13 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+#define ebu_region0_enable 0
+#endif
+
+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
+#if ((CONFIG_SYS_MAX_FLASH_BANKS == 2) && defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) )
+#define ebu_region0_addrsel_mask 3
+#else
+#define ebu_region0_addrsel_mask 1
+#endif
+
+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) || ((CONFIG_SYS_MAX_FLASH_BANKS == 2) && defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) )
+#define ebu_region1_enable 1
+#else
+#define ebu_region1_enable 0
@ -2460,7 +2466,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+ * bank 0.
+ */
+ ltq_writel(&ltq_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE |
+ EBU_ADDRSEL_MASK(1) | EBU_ADDRSEL_REGEN);
+ EBU_ADDRSEL_MASK(ebu_region0_addrsel_mask) | EBU_ADDRSEL_REGEN);
+
+ ltq_writel(&ltq_ebu_regs->con_0, EBU_CON_AGEN_DEMUX |
+ EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |
@ -2474,17 +2480,26 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+ if (ebu_region1_enable) {
+ /*
+ * Map EBU region 1 to range 0x14000000-0x13ffffff and enable
+ * region control. This supports NAND flash in bank 1.
+ * region control. This supports NAND flash in bank 1. (and NOR flash in bank 2)
+ */
+ ltq_writel(&ltq_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE |
+ EBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN);
+
+ ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
+ EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |
+ EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
+ EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |
+ EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |
+ EBU_CON_CMULT_4);
+ if (ebu_region0_addrsel_mask == 1)
+ ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
+ EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |
+ EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
+ EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |
+ EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |
+ EBU_CON_CMULT_4);
+
+ if (ebu_region0_addrsel_mask == 3)
+ ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
+ EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |
+ EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
+ EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |
+ EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |
+ EBU_CON_CMULT_16);
+ } else
+ ltq_clrbits(&ltq_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN);
+}
@ -3450,7 +3465,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+#endif /* __DANUBE_SOC_H__ */
--- /dev/null
+++ b/arch/mips/include/asm/arch-vrx200/config.h
@@ -0,0 +1,184 @@
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2010 Lantiq Deutschland GmbH
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
@ -3538,9 +3553,12 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+
+/* FLASH driver */
+#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
+#ifndef CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#endif
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_FLASH_BASE 0xB0000000
+#define CONFIG_SYS_FLASH2_BASE 0xB4000000
+#define CONFIG_FLASH_16BIT
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER

2
package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch
View file

@ -19,7 +19,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
endif
--- a/arch/mips/include/asm/arch-vrx200/config.h
+++ b/arch/mips/include/asm/arch-vrx200/config.h
@@ -164,7 +164,7 @@
@@ -167,7 +167,7 @@
#define CONFIG_SYS_TEXT_BASE 0xB0000000
#endif