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add GPIO configuration feature

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SVN-Revision: 17512
This commit is contained in:
Gabor Juhos 2009-09-04 15:08:26 +00:00
parent 8691bbb699
commit 8d8a4e7274
11 changed files with 197 additions and 4 deletions
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1
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/common.h
View file

@ -17,6 +17,7 @@ void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
u32 ramips_intc_get_status(void);
void __init ramips_soc_setup(void);
void __init ramips_gpio_init(void);
void __init ramips_early_serial_setup(int line, unsigned base, unsigned freq,
unsigned irq);

4
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x.h
View file

@ -1,7 +1,7 @@
/*
* Ralink RT288x SoC specific definitions
*
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Ralink's 2.6.21 BSP
@ -68,4 +68,6 @@ static inline u32 rt288x_memc_rr(unsigned reg)
return __raw_readl(rt288x_memc_base + reg);
}
void rt288x_gpio_init(u32 mode) __init;
#endif /* _RT228X_H_ */

10
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
View file

@ -46,6 +46,7 @@
#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
@ -75,6 +76,15 @@
#define RT2880_RESET_FE BIT(18)
#define RT2880_RESET_PCM BIT(19)
#define RT2880_GPIO_MODE_I2C BIT(0)
#define RT2880_GPIO_MODE_UART0 BIT(1)
#define RT2880_GPIO_MODE_SPI BIT(2)
#define RT2880_GPIO_MODE_UART1 BIT(3)
#define RT2880_GPIO_MODE_JTAG BIT(4)
#define RT2880_GPIO_MODE_MDIO BIT(5)
#define RT2880_GPIO_MODE_SDRAM BIT(6)
#define RT2880_GPIO_MODE_PCI BIT(7)
#define RT2880_INTC_INT_TIMER0 BIT(0)
#define RT2880_INTC_INT_TIMER1 BIT(1)
#define RT2880_INTC_INT_UART0 BIT(2)

55
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h
View file

@ -73,4 +73,59 @@ static inline u32 rt305x_memc_rr(unsigned reg)
return __raw_readl(rt305x_memc_base + reg);
}
#define RT305X_GPIO_I2C_SD 1
#define RT305X_GPIO_I2C_SCLK 2
#define RT305X_GPIO_SPI_EN 3
#define RT305X_GPIO_SPI_CLK 4
#define RT305X_GPIO_SPI_DOUT 5
#define RT305X_GPIO_SPI_DIN 6
/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
#define RT305X_GPIO_7 7
#define RT305X_GPIO_8 8
#define RT305X_GPIO_9 9
#define RT305X_GPIO_10 10
#define RT305X_GPIO_11 11
#define RT305X_GPIO_12 12
#define RT305X_GPIO_13 13
#define RT305X_GPIO_14 14
#define RT305X_GPIO_UART1_TXD 15
#define RT305X_GPIO_UART1_RXD 16
#define RT305X_GPIO_JTAG_TDO 17
#define RT305X_GPIO_JTAG_TDI 18
#define RT305X_GPIO_JTAG_TMS 19
#define RT305X_GPIO_JTAG_TCLK 20
#define RT305X_GPIO_JTAG_TRST_N 21
#define RT305X_GPIO_MDIO_MDC 22
#define RT305X_GPIO_MDIO_MDIO 23
#define RT305X_GPIO_SDRAM_MD16 24
#define RT305X_GPIO_SDRAM_MD17 25
#define RT305X_GPIO_SDRAM_MD18 26
#define RT305X_GPIO_SDRAM_MD19 27
#define RT305X_GPIO_SDRAM_MD20 28
#define RT305X_GPIO_SDRAM_MD21 29
#define RT305X_GPIO_SDRAM_MD22 30
#define RT305X_GPIO_SDRAM_MD23 31
#define RT305X_GPIO_SDRAM_MD24 32
#define RT305X_GPIO_SDRAM_MD25 33
#define RT305X_GPIO_SDRAM_MD26 34
#define RT305X_GPIO_SDRAM_MD27 35
#define RT305X_GPIO_SDRAM_MD28 36
#define RT305X_GPIO_SDRAM_MD29 37
#define RT305X_GPIO_SDRAM_MD30 38
#define RT305X_GPIO_SDRAM_MD31 39
#define RT305X_GPIO_GE0_TXD0 40
#define RT305X_GPIO_GE0_TXD1 41
#define RT305X_GPIO_GE0_TXD2 42
#define RT305X_GPIO_GE0_TXD3 43
#define RT305X_GPIO_GE0_TXEN 44
#define RT305X_GPIO_GE0_TXCLK 45
#define RT305X_GPIO_GE0_RXD0 46
#define RT305X_GPIO_GE0_RXD1 47
#define RT305X_GPIO_GE0_RXD2 48
#define RT305X_GPIO_GE0_RXD3 49
#define RT305X_GPIO_GE0_RXDV 50
#define RT305X_GPIO_GE0_RXCLK 51
void rt305x_gpio_init(u32 mode) __init;
#endif /* _RT305X_H_ */

20
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
View file

@ -49,6 +49,7 @@
#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
@ -61,6 +62,25 @@
#define SYSTEM_CONFIG_CPUCLK_320 0x0
#define SYSTEM_CONFIG_CPUCLK_384 0x1
#define RT305X_GPIO_MODE_I2C BIT(0)
#define RT305X_GPIO_MODE_SPI BIT(1)
#define RT305X_GPIO_MODE_UART0_SHIFT 2
#define RT305X_GPIO_MODE_UART0_MASK 0x7
#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
#define RT305X_GPIO_MODE_UARTF 0x0
#define RT305X_GPIO_MODE_PCM_UARTF 0x1
#define RT305X_GPIO_MODE_PCM_I2S 0x2
#define RT305X_GPIO_MODE_I2S_UARTF 0x3
#define RT305X_GPIO_MODE_PCM_GPIO 0x4
#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
#define RT305X_GPIO_MODE_GPIO_I2S 0x6
#define RT305X_GPIO_MODE_GPIO 0x7
#define RT305X_GPIO_MODE_UART1 BIT(5)
#define RT305X_GPIO_MODE_JTAG BIT(6)
#define RT305X_GPIO_MODE_MDIO BIT(7)
#define RT305X_GPIO_MODE_SDRAM BIT(8)
#define RT305X_GPIO_MODE_RGMII BIT(9)
#define RT305X_RESET_SYSTEM BIT(0)
#define RT305X_RESET_TIMER BIT(8)
#define RT305X_RESET_INTC BIT(9)

2
target/linux/ramips/files/arch/mips/ralink/common/gpio.c
View file

@ -220,5 +220,3 @@ __init int ramips_gpio_init(void)
return 0;
}
arch_initcall(ramips_gpio_init);

6
target/linux/ramips/files/arch/mips/ralink/rt288x/mach-rt-n15.c
View file

@ -18,10 +18,14 @@
#include <asm/mips_machine.h>
#include <asm/mach-ralink/machine.h>
#include <asm/mach-ralink/dev_gpio_leds.h>
#include <asm/mach-ralink/rt288x.h>
#include <asm/mach-ralink/rt288x_regs.h>
#include "devices.h"
#define RT_N15_GPIO_LED_POWER 11
#define RT_N15_GPIO_BUTTON_WPS 0
#define RT_N15_GPIO_BUTTON_RESET 12
#ifdef CONFIG_MTD_PARTITIONS
static struct mtd_partition rt_n15_partitions[] = {
@ -73,6 +77,8 @@ static struct gpio_led rt_n15_leds_gpio[] __initdata = {
static void __init rt_n15_init(void)
{
rt288x_gpio_init(RT2880_GPIO_MODE_UART0);
rt288x_register_flash(0, &rt_n15_flash_data);
ramips_register_gpio_leds(-1, ARRAY_SIZE(rt_n15_leds_gpio),

35
target/linux/ramips/files/arch/mips/ralink/rt288x/rt288x.c
View file

@ -1,7 +1,7 @@
/*
* Ralink RT288x SoC specific setup
*
* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Ralink's 2.6.21 BSP
@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <asm/mach-ralink/common.h>
#include <asm/mach-ralink/rt288x.h>
@ -73,3 +74,35 @@ void __init rt288x_detect_sys_freq(void)
rt288x_sys_freq = rt288x_cpu_freq / 2;
}
static void rt288x_gpio_reserve(int first, int last)
{
for (; first <= last; first++)
gpio_request(first, "reserved");
}
void __init rt288x_gpio_init(u32 mode)
{
rt288x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
ramips_gpio_init();
if ((mode & RT2880_GPIO_MODE_I2C) == 0)
rt288x_gpio_reserve(1, 2);
if ((mode & RT2880_GPIO_MODE_SPI) == 0)
rt288x_gpio_reserve(3, 6);
if ((mode & RT2880_GPIO_MODE_UART0) == 0)
rt288x_gpio_reserve(7, 14);
if ((mode & RT2880_GPIO_MODE_JTAG) == 0)
rt288x_gpio_reserve(17, 21);
if ((mode & RT2880_GPIO_MODE_MDIO) == 0)
rt288x_gpio_reserve(22, 23);
if ((mode & RT2880_GPIO_MODE_SDRAM) == 0)
rt288x_gpio_reserve(24, 39);
if ((mode & RT2880_GPIO_MODE_PCI) == 0)
rt288x_gpio_reserve(40, 71);
}

6
target/linux/ramips/files/arch/mips/ralink/rt305x/mach-v22rw-2x2.c
View file

@ -18,9 +18,13 @@
#include <asm/mips_machine.h>
#include <asm/mach-ralink/machine.h>
#include <asm/mach-ralink/dev_gpio_leds.h>
#include <asm/mach-ralink/rt305x.h>
#include <asm/mach-ralink/rt305x_regs.h>
#include "devices.h"
#define V22RW_2X2_GPIO_BUTTON_WPS 0
#define V22RW_2X2_GPIO_BUTTON_SWRST 10
#define V22RW_2X2_GPIO_LED_SECURITY 13
#define V22RW_2X2_GPIO_LED_WPS 14
@ -78,6 +82,8 @@ static struct gpio_led v22rw_2x2_leds_gpio[] __initdata = {
static void __init v22rw_2x2_init(void)
{
rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
rt305x_register_flash(0, &v22rw_2x2_flash_data);
ramips_register_gpio_leds(-1, ARRAY_SIZE(v22rw_2x2_leds_gpio),

4
target/linux/ramips/files/arch/mips/ralink/rt305x/mach-whr-g300n.c
View file

@ -18,6 +18,8 @@
#include <asm/mips_machine.h>
#include <asm/mach-ralink/machine.h>
#include <asm/mach-ralink/dev_gpio_leds.h>
#include <asm/mach-ralink/rt305x.h>
#include <asm/mach-ralink/rt305x_regs.h>
#include "devices.h"
@ -87,6 +89,8 @@ static struct gpio_led whr_g300n_leds_gpio[] __initdata = {
static void __init whr_g300n_init(void)
{
rt305x_gpio_init(RT305X_GPIO_MODE_GPIO << RT305X_GPIO_MODE_UART0_SHIFT);
rt305x_register_flash(0, &whr_g300n_flash_data);
ramips_register_gpio_leds(-1, ARRAY_SIZE(whr_g300n_leds_gpio),

58
target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c
View file

@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <asm/mach-ralink/common.h>
#include <asm/mach-ralink/rt305x.h>
@ -66,3 +67,60 @@ void __init rt305x_detect_sys_freq(void)
rt305x_sys_freq = rt305x_cpu_freq / 3;
}
static void rt305x_gpio_reserve(int first, int last)
{
for (; first <= last; first++)
gpio_request(first, "reserved");
}
void __init rt305x_gpio_init(u32 mode)
{
u32 t;
rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
ramips_gpio_init();
if ((mode & RT305X_GPIO_MODE_I2C) == 0)
rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);
if ((mode & RT305X_GPIO_MODE_SPI) == 0)
rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK);
t = mode >> RT305X_GPIO_MODE_UART0_SHIFT;
t &= RT305X_GPIO_MODE_UART0_MASK;
switch (t) {
case RT305X_GPIO_MODE_UARTF:
case RT305X_GPIO_MODE_PCM_UARTF:
case RT305X_GPIO_MODE_PCM_I2S:
case RT305X_GPIO_MODE_I2S_UARTF:
rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14);
break;
case RT305X_GPIO_MODE_PCM_GPIO:
rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14);
break;
case RT305X_GPIO_MODE_GPIO_UARTF:
case RT305X_GPIO_MODE_GPIO_I2S:
rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10);
break;
}
if ((mode & RT305X_GPIO_MODE_UART1) == 0)
rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD,
RT305X_GPIO_UART1_RXD);
if ((mode & RT305X_GPIO_MODE_JTAG) == 0)
rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI);
if ((mode & RT305X_GPIO_MODE_MDIO) == 0)
rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC,
RT305X_GPIO_MDIO_MDIO);
if ((mode & RT305X_GPIO_MODE_SDRAM) == 0)
rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16,
RT305X_GPIO_SDRAM_MD31);
if ((mode & RT305X_GPIO_MODE_RGMII) == 0)
rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0,
RT305X_GPIO_GE0_RXCLK);
}