mcs814x: remove PCI code
None of the boards we support are using it nor have it wired out of the SoC, just remove it. Signed-off-by: Florian Fainelli <florian@openwrt.org> SVN-Revision: 36061
This commit is contained in:
Florian Fainelli
parent
a9ef927cce
commit
8bc84bac31
6 changed files with 1 additions and 484 deletions
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@ -60,7 +60,6 @@ CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_GPIO=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_MCS814X=y
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CONFIG_GPIO_SYSFS=y
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@ -118,7 +117,6 @@ CONFIG_MCS814X_PHY=y
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# CONFIG_MCS814X_WATCHDOG is not set
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CONFIG_MDIO_BOARDINFO=y
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# CONFIG_MFD_T7L66XB is not set
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CONFIG_MIGHT_HAVE_PCI=y
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# CONFIG_MTD_COMPLEX_MAPPINGS is not set
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# CONFIG_MTD_IMPA7 is not set
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CONFIG_MTD_JEDECPROBE=y
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@ -79,27 +79,6 @@
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interrupts = <19 27>; // done, error
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};
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pci@400b0000 {
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compatible = "moschip,mcs8140-pci", "moschip,mcs814x-pci";
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reg = <0x400b0000 0x44 // PCI master
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0x400d8000 0xe4>; // EEPROM emulator
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interrupts = <25>; // abort interrupt
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0 0x80000000 0x80000000 0 0x04000000 // IO
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0x42000000 0 0x90000000 0x90000000 0 0x20000000 // non-prefetch
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0x02000000 0 0xb0000000 0xb0000000 0 0x10000000>; // prefecth
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#interrupt-cells = <1>;
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interrupt-map-mask = <>;
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interrupt-map = <0 0 0 1 &intc 22 0
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0 0 0 2 &intc 23 0
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0 0 0 3 &intc 24 0
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0 0 0 4 &intc 26 0>;
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};
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gpio: gpio@400d0000 {
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compatible = "moschip,mcs814x-gpio";
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reg = <0x400d0000 0x670>;
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@ -3,4 +3,3 @@ obj-y += common.o
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obj-y += irq.o
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obj-y += timer.o
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obj-y += board-mcs8140-dt.o
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obj-$(CONFIG_PCI) += pci.o
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@ -14,9 +14,4 @@
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#define NR_IRQS 32
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#define IRQ_PCI_INTA 22
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#define IRQ_PCI_INTB 23
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#define IRQ_PCI_INTC 24
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#define IRQ_PCI_INTD 26
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#endif
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@ -1,453 +0,0 @@
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/*
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* Moschip MCS8140 PCI support
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*
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* Copyright (C) 2003 Moschip Semiconductors Ltd.
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* Copyright (C) 2003 Artec Design Ltd.
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* Copyright (C) 2012 Florian Fainelli <florian@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/mach/pci.h>
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#include <asm/mach/map.h>
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#include <mach/mcs814x.h>
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#include <mach/irqs.h>
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#define MCS8140_PCI_CONFIG_SIZE SZ_64M
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#define MCS8140_PCI_IOMISC_SIZE SZ_64M
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#define MCS8140_PCI_HOST_BASE 0x80000000
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#define MCS8140_PCI_IOMISC_BASE 0x00000000
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#define MCS8140_PCI_PRE_BASE 0x10000000
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#define MCS8140_PCI_NONPRE_BASE 0x30000000
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#define MCS8140_PCI_CFG_BASE (MCS8140_PCI_HOST_BASE + 0x04000000)
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#define MCS8140_PCI_IO_BASE (MCS8140_PCI_HOST_BASE)
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#define MCS8140_PCI_IO_VIRT_BASE (MCS814X_IO_BASE - MCS8140_PCI_CONFIG_SIZE - \
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MCS8140_PCI_IOMISC_SIZE)
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#define MCS8140_PCI_CFG_VIRT_BASE (MCS814X_IO_BASE - MCS8140_PCI_CONFIG_SIZE)
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#define PCI_FATAL_ERROR 1
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#define EXTERNAL_ABORT_NON_LINE_FETCH 8
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#define EPRM_DONE 0x80
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#define EPRM_SDRAM_FUNC0 0xAC
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#define PCI_INTD 4
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#define MCS8140_PCI_DEVICE_ID 0xA0009710
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#define MCS8140_PCI_CLASS_ID 0x02000011 /* Host-Class id :0x0600 */
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#define PCI_IF_CONFIG 0x200
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static void __iomem *mcs8140_pci_master_base;
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static void __iomem *mcs8140_eeprom_emu_base;
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static unsigned long __pci_addr(struct pci_bus *bus,
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unsigned int devfn, int offset)
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{
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unsigned int busnr = bus->number;
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unsigned int slot;
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/* we only support bus 0 */
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if (busnr != 0)
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return 0;
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/*
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* Trap out illegal values
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*/
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BUG_ON(devfn > 255 || busnr > 255 || devfn > 255);
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/* Scan 3 slots */
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slot = PCI_SLOT(devfn);
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switch (slot) {
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case 1:
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case 2:
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case 3:
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if (PCI_FUNC(devfn) >= 4)
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return 0;
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return MCS8140_PCI_CFG_VIRT_BASE | (PCI_SLOT(devfn) << 11) |
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(PCI_FUNC(devfn) << 8) | offset;
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default:
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pr_warn("Ignoring: PCI Slot is %x\n", PCI_SLOT(devfn));
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return 0;
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}
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}
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static int mcs8140_pci_host_status(void)
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{
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u32 host_status;
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host_status = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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if (host_status & PCI_FATAL_ERROR) {
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writel_relaxed(host_status & 0xfffffff0,
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mcs8140_pci_master_base + PCI_IF_CONFIG);
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/* flush write */
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host_status =
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readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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return 1;
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}
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return 0;
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}
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static int mcs8140_pci_read_config(struct pci_bus *bus,
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unsigned int devfn, int where,
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int size, u32 *val)
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{
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unsigned long v = 0xFFFFFFFF;
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unsigned long addr = __pci_addr(bus, devfn, where);
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if (addr != 0) {
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switch (size) {
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case 1:
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v = readb_relaxed(addr);
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break;
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case 2:
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addr &= ~1;
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v = readw_relaxed(addr);
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break;
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default:
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addr &= ~3;
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v = readl_relaxed(addr);
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break;
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}
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} else
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v = 0xffffffff;
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if (mcs8140_pci_host_status())
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v = 0xffffffff;
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*val = v;
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return PCIBIOS_SUCCESSFUL;
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}
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static void mcs8140_eeprom_emu_init(void)
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{
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writel_relaxed(0x0000000F, mcs8140_eeprom_emu_base + EPRM_SDRAM_FUNC0);
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writel_relaxed(0x08000000, MCS8140_PCI_CFG_VIRT_BASE + 0x10);
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/* Set the DONE bit of the EEPROM emulator */
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writel_relaxed(0x01, mcs8140_eeprom_emu_base + EPRM_DONE);
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}
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static int mcs8140_pci_write_config(struct pci_bus *bus,
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unsigned int devfn, int where,
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int size, u32 val)
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{
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unsigned long addr = __pci_addr(bus, devfn, where);
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if (addr != 0) {
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switch (size) {
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case 1:
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writeb_relaxed((u8)val, addr);
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break;
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case 2:
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writew_relaxed((u16)val, addr);
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break;
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case 4:
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writel_relaxed(val, addr);
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pci_mcs8140_ops = {
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.read = mcs8140_pci_read_config,
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.write = mcs8140_pci_write_config,
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};
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static struct resource io_mem = {
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.name = "PCI I/O space",
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.start = MCS8140_PCI_HOST_BASE + MCS8140_PCI_IOMISC_BASE,
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.end = MCS8140_PCI_HOST_BASE + MCS8140_PCI_IOMISC_BASE + SZ_64M,
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.flags = IORESOURCE_IO,
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};
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static struct resource pre_mem = {
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.name = "PCI prefetchable",
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.start = MCS8140_PCI_HOST_BASE + MCS8140_PCI_PRE_BASE,
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.end = MCS8140_PCI_HOST_BASE + MCS8140_PCI_PRE_BASE + SZ_512M,
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.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
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};
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static struct resource non_mem = {
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.name = "PCI non-prefetchable",
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.start = MCS8140_PCI_HOST_BASE + MCS8140_PCI_NONPRE_BASE,
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.end = MCS8140_PCI_HOST_BASE + MCS8140_PCI_NONPRE_BASE + SZ_256M,
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.flags = IORESOURCE_MEM,
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};
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int __init pci_mcs8140_setup_resources(struct pci_sys_data *sys)
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{
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int ret = 0;
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ret = request_resource(&iomem_resource, &io_mem);
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if (ret) {
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pr_err("PCI: unable to allocate I/O "
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"memory region (%d)\n", ret);
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goto out;
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}
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ret = request_resource(&iomem_resource, &non_mem);
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if (ret) {
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pr_err("PCI: unable to allocate non-prefetchable "
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"memory region (%d)\n", ret);
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goto release_io_mem;
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}
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ret = request_resource(&iomem_resource, &pre_mem);
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if (ret) {
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pr_err("PCI: unable to allocate prefetchable "
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"memory region (%d)\n", ret);
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goto release_non_mem;
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}
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mcs8140_eeprom_emu_init();
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pci_add_resource(&sys->resources, &io_mem);
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pci_add_resource(&sys->resources, &non_mem);
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pci_add_resource(&sys->resources, &pre_mem);
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return ret;
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release_non_mem:
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release_resource(&non_mem);
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release_io_mem:
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release_resource(&io_mem);
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out:
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return ret;
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}
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struct pci_bus *pci_mcs8140_scan_bus(int nr, struct pci_sys_data *sys)
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{
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return pci_scan_bus(sys->busnr, &pci_mcs8140_ops, sys);
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}
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int __init pci_mcs8140_setup(int nr, struct pci_sys_data *sys)
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{
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int ret = 0;
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u32 val;
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if (nr > 0)
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return 0;
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sys->mem_offset = MCS8140_PCI_IO_VIRT_BASE - MCS8140_PCI_IO_BASE;
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sys->io_offset = 0;
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ret = pci_mcs8140_setup_resources(sys);
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if (ret < 0) {
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pr_err("unable to setup mcs8140 resources\n");
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goto out;
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}
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val = readl_relaxed(MCS8140_PCI_CFG_VIRT_BASE);
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if (val != MCS8140_PCI_DEVICE_ID) {
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pr_err("cannot find MCS8140 PCI Core: %08x\n", val);
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ret = -EIO;
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goto out;
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}
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pr_info("MCS8140 PCI core found\n");
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val = readl_relaxed(MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND);
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/* Added to support wireless cards */
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writel_relaxed(0, MCS8140_PCI_CFG_VIRT_BASE + 0x40);
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writel_relaxed(val | 0x147, MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND);
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val = readl_relaxed(MCS8140_PCI_CFG_VIRT_BASE + PCI_COMMAND);
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ret = 1;
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out:
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return ret;
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}
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static int __init mcs8140_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int line = IRQ_PCI_INTA;
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if (pin != 0) {
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/* IRQ_PCIA - 22 */
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if (pin == PCI_INTD)
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line = IRQ_PCI_INTA + pin; /* IRQ_PCIA - 22 */
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else
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line = IRQ_PCI_INTA + pin - 1; /* IRQ_PCIA - 22 */
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}
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pr_info("PCI: Map interrupt slot 0x%02x pin 0x%02x line 0x%02x\n",
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slot, pin, line);
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return line;
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}
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static irqreturn_t mcs8140_pci_abort_interrupt(int irq, void *dummy)
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{
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u32 word;
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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if (!(word & (1 << 24)))
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return IRQ_NONE;
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writel_relaxed(word & 0xfffffff0,
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mcs8140_pci_master_base + PCI_IF_CONFIG);
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/* flush write */
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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return IRQ_HANDLED;
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}
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static int mcs8140_pci_abort_irq_init(int irq)
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{
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u32 word;
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/* Enable Interrupt in PCI Master Core */
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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word |= (1 << 24);
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writel_relaxed(word, mcs8140_pci_master_base + PCI_IF_CONFIG);
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/* flush write */
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word = readl_relaxed(mcs8140_pci_master_base + PCI_IF_CONFIG);
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return request_irq(irq, mcs8140_pci_abort_interrupt, 0,
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"PCI abort", NULL);
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}
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static int mcs8140_pci_host_abort(unsigned long addr,
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unsigned int fsr, struct pt_regs *regs)
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{
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pr_warn("PCI Data abort: address = 0x%08lx fsr = 0x%03x"
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"PC = 0x%08lx LR = 0x%08lx\n",
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addr, fsr, regs->ARM_pc, regs->ARM_lr);
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/*
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* If it was an imprecise abort, then we need to correct the
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* return address to be _after_ the instruction.
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*/
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if (fsr & (1 << 10) || mcs8140_pci_host_status())
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regs->ARM_pc += 4;
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return 0;
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}
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static void mcs8140_data_abort_init(void)
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{
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hook_fault_code(EXTERNAL_ABORT_NON_LINE_FETCH,
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mcs8140_pci_host_abort, SIGBUS,
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0, "external abort on non-line fetch");
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}
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static struct hw_pci mcs8140_pci __initdata = {
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.map_irq = mcs8140_map_irq,
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.nr_controllers = 1,
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.setup = pci_mcs8140_setup,
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.scan = pci_mcs8140_scan_bus,
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};
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static struct map_desc mcs8140_pci_io_desc[] __initdata = {
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{
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.virtual = MCS8140_PCI_CFG_VIRT_BASE,
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.pfn = __phys_to_pfn(MCS8140_PCI_CFG_BASE),
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.length = MCS8140_PCI_CONFIG_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = MCS8140_PCI_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(MCS8140_PCI_IO_BASE),
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.length = MCS8140_PCI_IOMISC_SIZE,
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.type = MT_DEVICE
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},
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};
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static int __devinit mcs8140_pci_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int ret, irq;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "failed to get mem resource 0\n");
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return -ENODEV;
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}
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mcs8140_pci_master_base = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!mcs8140_pci_master_base) {
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dev_err(&pdev->dev, "failed to remap PCI master regs\n");
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return -ENODEV;
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}
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|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "failed to get mem resource 1\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
mcs8140_eeprom_emu_base = devm_ioremap(&pdev->dev, res->start,
|
||||
resource_size(res));
|
||||
if (!mcs8140_eeprom_emu_base) {
|
||||
dev_err(&pdev->dev, "failed to remap EEPROM regs\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "failed to get pci abort irq\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Setup static mappins for PCI CFG space */
|
||||
iotable_init(mcs8140_pci_io_desc, ARRAY_SIZE(mcs8140_pci_io_desc));
|
||||
|
||||
pcibios_min_io = MCS8140_PCI_HOST_BASE;
|
||||
pcibios_min_mem = MCS8140_PCI_HOST_BASE + MCS8140_PCI_PRE_BASE;
|
||||
|
||||
mcs8140_data_abort_init();
|
||||
ret = mcs8140_pci_abort_irq_init(irq);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to setup abort irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pci_common_init(&mcs8140_pci);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id mcs8140_of_ids[] __devinitdata = {
|
||||
{ .compatible = "moschip,mcs8140-pci" },
|
||||
{ .compatible = "moschip,mcs814x-pci" },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct platform_driver mcs8140_pci_driver = {
|
||||
.driver = {
|
||||
.name = "mcs8140-pci",
|
||||
.of_match_table = mcs8140_of_ids,
|
||||
},
|
||||
.probe = mcs8140_pci_probe,
|
||||
};
|
||||
|
||||
static int __init mcs8140_pci_init(void)
|
||||
{
|
||||
return platform_driver_register(&mcs8140_pci_driver);
|
||||
}
|
||||
subsys_initcall(mcs8140_pci_init);
|
||||
|
||||
|
|
@ -1,12 +1,11 @@
|
|||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -869,6 +869,22 @@ config ARCH_EXYNOS
|
||||
@@ -869,6 +869,21 @@ config ARCH_EXYNOS
|
||||
help
|
||||
Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
|
||||
|
||||
+config ARCH_MCS814X
|
||||
+ bool "Moschip MCS814x"
|
||||
+ select MIGHT_HAVE_PCI
|
||||
+ select FIQ
|
||||
+ select GENERIC_IRQ_CHIP
|
||||
+ select GENERIC_GPIO
|
||||
|
|
|
|||
Loading…
Reference in a new issue