uboot-lantiq: Add support for Arcadyan ARV8539PW22 (Speedport W 504V)
uboot-lantiq: Add support for Arcadyan ARV8539PW22 (Speedport W 504V) Signed-off-by: Jannis Pinter <jannis@pinterjann.is> SVN-Revision: 46225
This commit is contained in:
John Crispin
parent
b9963bbe80
commit
8a843b7b77
2 changed files with 260 additions and 0 deletions
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@ -150,6 +150,25 @@ define uboot/arv752dpw22_brn
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DEPS:=@TARGET_lantiq_xway_ARV752DPW22
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DEPS:=@TARGET_lantiq_xway_ARV752DPW22
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endef
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endef
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define uboot/arv8539pw22_ram
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TITLE:=U-Boot for Speedport W 504V Typ A (RAM)
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SOC:=danube
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DDR_SETTINGS:=board/arcadyan/arv8539pw22/ddr_settings.h
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DEPS:=@TARGET_lantiq_xway_ARV8539PW22
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endef
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define uboot/arv8539pw22_nor
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TITLE:=U-Boot for Speedport W 504V Typ A (NOR)
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SOC:=danube
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DEPS:=@TARGET_lantiq_xway_ARV8539PW22
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endef
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define uboot/arv8539pw22_brn
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TITLE:=U-Boot for Speedport W 504V Typ A (BRN)
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SOC:=danube
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DEPS:=@TARGET_lantiq_xway_ARV8539PW22
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endef
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define uboot/gigasx76x_ram
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define uboot/gigasx76x_ram
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TITLE:=U-Boot for Siemens Gigaset sx76x (RAM)
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TITLE:=U-Boot for Siemens Gigaset sx76x (RAM)
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SOC:=danube
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SOC:=danube
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@ -283,6 +302,7 @@ UBOOTS:= \
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arv7518pw_ram arv7518pw_nor arv7518pw_brn \
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arv7518pw_ram arv7518pw_nor arv7518pw_brn \
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arv752dpw_ram arv752dpw_nor arv752dpw_brn \
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arv752dpw_ram arv752dpw_nor arv752dpw_brn \
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arv752dpw22_ram arv752dpw22_nor arv752dpw22_brn \
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arv752dpw22_ram arv752dpw22_nor arv752dpw22_brn \
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arv8539pw22_brn arv8539pw22_nor arv8539pw22_ram \
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gigasx76x_ram gigasx76x_nor \
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gigasx76x_ram gigasx76x_nor \
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acmp252_ram acmp252_nor \
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acmp252_ram acmp252_nor \
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easy50712_ram easy50712_nor easy50712_norspl \
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easy50712_ram easy50712_nor easy50712_norspl \
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@ -0,0 +1,240 @@
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--- /dev/null
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+++ b/board/arcadyan/arv8539pw22/Makefile
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@@ -0,0 +1,28 @@
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+#
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+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
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+#
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+
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+include $(TOPDIR)/config.mk
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+
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+LIB = $(obj)lib$(BOARD).o
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+
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+COBJS = $(BOARD).o
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+
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+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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+OBJS := $(addprefix $(obj),$(COBJS))
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+SOBJS := $(addprefix $(obj),$(SOBJS))
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+
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+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
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+
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+#########################################################################
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+
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+# defines $(obj).depend target
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+include $(SRCTREE)/rules.mk
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+
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+sinclude $(obj).depend
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+
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+#########################################################################
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+
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--- /dev/null
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+++ b/board/arcadyan/arv8539pw22/arv8539pw22.c
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@@ -0,0 +1,53 @@
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+/*
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+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
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+ * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <common.h>
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+#include <switch.h>
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+#include <asm/gpio.h>
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+#include <asm/lantiq/eth.h>
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+#include <asm/lantiq/reset.h>
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+#include <asm/lantiq/chipid.h>
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+
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+int board_early_init_f(void)
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+{
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+ return 0;
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+}
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+
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+int checkboard(void)
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+{
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+ puts("Board: " CONFIG_BOARD_NAME "\n");
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+ ltq_chip_print_info();
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+
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+ return 0;
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+}
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+
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+static const struct ltq_eth_port_config eth_port_config[] = {
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+ /* MAC0: Atheros ar8216 switch */
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+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII },
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+};
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+
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+static const struct ltq_eth_board_config eth_board_config = {
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+ .ports = eth_port_config,
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+ .num_ports = ARRAY_SIZE(eth_port_config),
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+};
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+
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+int board_eth_init(bd_t *bis)
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+{
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+ return ltq_eth_initialize(ð_board_config);
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+}
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+
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+static struct switch_device ar8216_dev = {
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+ .name = "ar8216",
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+ .cpu_port = 0,
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+ .port_mask = 0xF,
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+};
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+
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+int board_switch_init(void)
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+{
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+ return switch_device_register(&ar8216_dev);
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+}
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+
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--- /dev/null
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+++ b/board/arcadyan/arv8539pw22/config.mk
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@@ -0,0 +1,8 @@
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+#
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+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
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+#
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+
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+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
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+
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--- /dev/null
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+++ b/board/arcadyan/arv8539pw22/ddr_settings.h
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@@ -0,0 +1,55 @@
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+/*
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+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
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+ *
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+ * This file has been generated with lantiq_ram_extract_magic.awk script.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#define MC_DC00_VALUE 0x1B1B
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+#define MC_DC01_VALUE 0x0
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+#define MC_DC02_VALUE 0x0
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+#define MC_DC03_VALUE 0x0
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+#define MC_DC04_VALUE 0x0
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+#define MC_DC05_VALUE 0x200
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+#define MC_DC06_VALUE 0x605
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+#define MC_DC07_VALUE 0x303
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+#define MC_DC08_VALUE 0x102
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+#define MC_DC09_VALUE 0x70A
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+#define MC_DC10_VALUE 0x203
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+#define MC_DC11_VALUE 0xC02
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+#define MC_DC12_VALUE 0x1C8
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+#define MC_DC13_VALUE 0x1
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+#define MC_DC14_VALUE 0x0
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+#define MC_DC15_VALUE 0x134
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+#define MC_DC16_VALUE 0xC800
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+#define MC_DC17_VALUE 0xD
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+#define MC_DC18_VALUE 0x301
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+#define MC_DC19_VALUE 0x200
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+#define MC_DC20_VALUE 0xA03
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+#define MC_DC21_VALUE 0x1400
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+#define MC_DC22_VALUE 0x1414
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+#define MC_DC23_VALUE 0x0
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+#define MC_DC24_VALUE 0x5B
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+#define MC_DC25_VALUE 0x0
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+#define MC_DC26_VALUE 0x0
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+#define MC_DC27_VALUE 0x0
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+#define MC_DC28_VALUE 0x510
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+#define MC_DC29_VALUE 0x4E20
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+#define MC_DC30_VALUE 0x8235
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+#define MC_DC31_VALUE 0x0
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+#define MC_DC32_VALUE 0x0
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+#define MC_DC33_VALUE 0x0
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+#define MC_DC34_VALUE 0x0
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+#define MC_DC35_VALUE 0x0
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+#define MC_DC36_VALUE 0x0
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+#define MC_DC37_VALUE 0x0
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+#define MC_DC38_VALUE 0x0
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+#define MC_DC39_VALUE 0x0
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+#define MC_DC40_VALUE 0x0
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+#define MC_DC41_VALUE 0x0
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+#define MC_DC42_VALUE 0x0
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+#define MC_DC43_VALUE 0x0
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+#define MC_DC44_VALUE 0x0
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+#define MC_DC45_VALUE 0x500
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+#define MC_DC46_VALUE 0x0
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--- a/boards.cfg
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+++ b/boards.cfg
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@@ -553,6 +553,9 @@ Active mips mips32 danube arcadyan arv752dpw
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Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_brn arv752dpw22:SYS_BOOT_BRN -
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Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_nor arv752dpw22:SYS_BOOT_NOR -
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Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_ram arv752dpw22:SYS_BOOT_RAM -
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+Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_brn arv8539pw22:SYS_BOOT_BRN -
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+Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_nor arv8539pw22:SYS_BOOT_NOR -
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+Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_ram arv8539pw22:SYS_BOOT_RAM -
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Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com>
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Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com>
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Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
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--- /dev/null
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+++ b/include/configs/arv8539pw22.h
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@@ -0,0 +1,68 @@
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+/*
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+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#ifndef __CONFIG_H
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+#define __CONFIG_H
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+
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+#define CONFIG_MACH_TYPE "ARV8539PW22"
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+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
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+#define CONFIG_BOARD_NAME "Speedport W 504V Typ A"
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+
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+/* Configure SoC */
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+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
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+
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+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
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+
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+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
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+
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+/* Switch devices */
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+#define CONFIG_SWITCH_MULTI
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+#define CONFIG_SWITCH_AR8216
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+
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+/* Environment */
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+#if defined(CONFIG_SYS_BOOT_NOR)
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+#define CONFIG_ENV_IS_IN_FLASH
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+#define CONFIG_ENV_OVERWRITE
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+#define CONFIG_ENV_OFFSET (192 * 1024)
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+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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+#else
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+#define CONFIG_ENV_IS_NOWHERE
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+#endif
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+
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+#define CONFIG_ENV_SIZE (8 * 1024)
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+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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+
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+/* Burnboot loadable image */
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+#if defined(CONFIG_SYS_BOOT_BRN)
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+#define CONFIG_SYS_TEXT_BASE 0x80002000
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+#define CONFIG_SKIP_LOWLEVEL_INIT
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+#define CONFIG_SYS_DISABLE_CACHE
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+#define CONFIG_ENV_OVERWRITE 1
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+#endif
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+
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+
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+/* Console */
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+#define CONFIG_LTQ_ADVANCED_CONSOLE
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+#define CONFIG_BAUDRATE 115200
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+#define CONFIG_CONSOLE_ASC 1
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+#define CONFIG_CONSOLE_DEV "ttyS1"
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+
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+/* Pull in default board configs for Lantiq XWAY Danube */
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+#include <asm/lantiq/config.h>
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+#include <asm/arch/config.h>
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+
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+/* Pull in default OpenWrt configs for Lantiq SoC */
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+#include "openwrt-lantiq-common.h"
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+
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+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
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+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
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+
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+#define CONFIG_EXTRA_ENV_SETTINGS \
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+ CONFIG_ENV_LANTIQ_DEFAULTS \
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+ CONFIG_ENV_UPDATE_UBOOT_NOR \
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+ "kernel_addr=0xB0040000\0"
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+
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+#endif /* __CONFIG_H */
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