use the new upstream l2cache and wdt code, smaller changes, refresh patches

SVN-Revision: 27558

target/linux/cns3xxx/patches-3.0/002-cns3xxx_wdt.patch

@@ -0,0 +1,69 @@
+1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog
+   since the CNS3xxx SOCs have ARM11 MPcore CPU.
+2. Enable mpcore_watchdog option as module to default configuration at
+   arch/arm/configs/cns3420vb_defconfig.
+
+Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com>
+
+---
+arch/arm/Kconfig                     |    1 +
+ arch/arm/configs/cns3420vb_defconfig |    2 ++
+ arch/arm/mach-cns3xxx/cns3420vb.c    |   22 ++++++++++++++++++++++
+ 3 files changed, 25 insertions(+), 0 deletions(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -327,6 +327,7 @@ config ARCH_CNS3XXX
+ 	select ARM_GIC
+ 	select MIGHT_HAVE_PCI
+ 	select PCI_DOMAINS if PCI
++	select HAVE_ARM_TWD
+ 	help
+ 	  Support for Cavium Networks CNS3XXX platform.
+ 
+--- a/arch/arm/configs/cns3420vb_defconfig
++++ b/arch/arm/configs/cns3420vb_defconfig
+@@ -53,6 +53,8 @@ CONFIG_LEGACY_PTY_COUNT=16
+ # CONFIG_HW_RANDOM is not set
+ # CONFIG_HWMON is not set
+ # CONFIG_VGA_CONSOLE is not set
++CONFIG_WATCHDOG=y
++CONFIG_MPCORE_WATCHDOG=m
+ # CONFIG_HID_SUPPORT is not set
+ # CONFIG_USB_SUPPORT is not set
+ CONFIG_MMC=y
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -159,10 +159,32 @@ static struct platform_device cns3xxx_us
+ 	},
+ };
+ 
++/* Watchdog */
++static struct resource cns3xxx_watchdog_resources[] = {
++	[0] = {
++		.start = CNS3XXX_TC11MP_TWD_BASE,
++		.end   = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1,
++		.flags = IORESOURCE_MEM,
++	},
++	[1] = {
++		.start = IRQ_LOCALWDOG,
++		.end   = IRQ_LOCALWDOG,
++		.flags = IORESOURCE_IRQ,
++	}
++};
++
++static struct platform_device cns3xxx_watchdog_device = {
++	.name		= "mpcore_wdt",
++	.id		= -1,
++	.num_resources	= ARRAY_SIZE(cns3xxx_watchdog_resources),
++	.resource	= cns3xxx_watchdog_resources,
++};
++
+ /*
+  * Initialization
+  */
+ static struct platform_device *cns3420_pdevs[] __initdata = {
++	&cns3xxx_watchdog_device,
+ 	&cns3420_nor_pdev,
+ 	&cns3xxx_usb_ehci_device,
+ 	&cns3xxx_usb_ohci_device,

target/linux/cns3xxx/patches-3.0/003-cns3xxx_l2cache.patch

@@ -0,0 +1,108 @@
+CNS3xxx SOCs have L310-compatible cache controller, so let's use it.
+
+With this patch benchmarking with 'gzip' shows that performance is
+doubled, and I'm still able to boot full-fledged userland over NFS
+(using PCIe NIC), so the support should be pretty robust.
+
+Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
+---
+
+ arch/arm/mach-cns3xxx/cns3420vb.c |    2 +
+ arch/arm/mach-cns3xxx/core.c      |   43 +++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-cns3xxx/core.h      |    6 +++++
+ arch/arm/mm/Kconfig               |    2 +-
+ 4 files changed, 52 insertions(+), 1 deletions(-)
+
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -192,6 +192,8 @@ static struct platform_device *cns3420_p
+ 
+ static void __init cns3420_init(void)
+ {
++	cns3xxx_l2x0_init();
++
+ 	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
+ 
+ 	cns3xxx_ahci_init();
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -16,6 +16,7 @@
+ #include <asm/mach/time.h>
+ #include <asm/mach/irq.h>
+ #include <asm/hardware/gic.h>
++#include <asm/hardware/cache-l2x0.h>
+ #include <mach/cns3xxx.h>
+ #include "core.h"
+ 
+@@ -244,3 +245,45 @@ static void __init cns3xxx_timer_init(vo
+ struct sys_timer cns3xxx_timer = {
+ 	.init = cns3xxx_timer_init,
+ };
++
++#ifdef CONFIG_CACHE_L2X0
++
++void __init cns3xxx_l2x0_init(void)
++{
++	void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
++	u32 val;
++
++	if (WARN_ON(!base))
++		return;
++
++	/*
++	 * Tag RAM Control register
++	 *
++	 * bit[10:8]	- 1 cycle of write accesses latency
++	 * bit[6:4]	- 1 cycle of read accesses latency
++	 * bit[3:0]	- 1 cycle of setup latency
++	 *
++	 * 1 cycle of latency for setup, read and write accesses
++	 */
++	val = readl(base + L2X0_TAG_LATENCY_CTRL);
++	val &= 0xfffff888;
++	writel(val, base + L2X0_TAG_LATENCY_CTRL);
++
++	/*
++	 * Data RAM Control register
++	 *
++	 * bit[10:8]	- 1 cycles of write accesses latency
++	 * bit[6:4]	- 1 cycles of read accesses latency
++	 * bit[3:0]	- 1 cycle of setup latency
++	 *
++	 * 1 cycle of latency for setup, read and write accesses
++	 */
++	val = readl(base + L2X0_DATA_LATENCY_CTRL);
++	val &= 0xfffff888;
++	writel(val, base + L2X0_DATA_LATENCY_CTRL);
++
++	/* 32 KiB, 8-way, parity disable */
++	l2x0_init(base, 0x00540000, 0xfe000fff);
++}
++
++#endif /* CONFIG_CACHE_L2X0 */
+--- a/arch/arm/mach-cns3xxx/core.h
++++ b/arch/arm/mach-cns3xxx/core.h
+@@ -13,6 +13,12 @@
+ 
+ extern struct sys_timer cns3xxx_timer;
+ 
++#ifdef CONFIG_CACHE_L2X0
++void __init cns3xxx_l2x0_init(void);
++#else
++static inline void cns3xxx_l2x0_init(void) {}
++#endif /* CONFIG_CACHE_L2X0 */
++
+ void __init cns3xxx_map_io(void);
+ void __init cns3xxx_init_irq(void);
+ void cns3xxx_power_off(void);
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -821,7 +821,7 @@ config CACHE_L2X0
+ 	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
+ 		   REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
+ 		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
+-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
++		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_CNS3XXX
+ 	default y
+ 	select OUTER_CACHE
+ 	select OUTER_CACHE_SYNC

target/linux/cns3xxx/patches-3.0/049-cns3xxx_smp_support.patch

@@ -185,6 +185,16 @@
 +	 */
 +	return cpu == 0 ? -EPERM : 0;
 +}
+--- a/arch/arm/mach-cns3xxx/Kconfig
++++ b/arch/arm/mach-cns3xxx/Kconfig
+@@ -3,6 +3,7 @@ menu "CNS3XXX platform type"
+ 
+ config MACH_CNS3420VB
+ 	bool "Support for CNS3420 Validation Board"
++	select HAVE_ARM_SCU if SMP
+ 	select MIGHT_HAVE_PCI
+ 	help
+ 	  Include support for the Cavium Networks CNS3420 MPCore Platform
 --- /dev/null
 +++ b/arch/arm/mach-cns3xxx/localtimer.c
 @@ -0,0 +1,26 @@
@@ -394,7 +404,7 @@
 +}
 --- a/arch/arm/Kconfig
 +++ b/arch/arm/Kconfig
-@@ -1312,7 +1312,7 @@ config SMP
+@@ -1313,7 +1313,7 @@ config SMP
  	depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
  		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
  		 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \

target/linux/cns3xxx/patches-3.0/053-cns3xxx_wdt.patch

@@ -1,77 +0,0 @@
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -188,7 +188,7 @@ config SA1100_WATCHDOG
- 
- config MPCORE_WATCHDOG
- 	tristate "MPcore watchdog"
--	depends on HAVE_ARM_TWD
-+	depends on ARCH_CNS3XXX
- 	help
- 	  Watchdog timer embedded into the MPcore system.
- 
---- a/drivers/watchdog/mpcore_wdt.c
-+++ b/drivers/watchdog/mpcore_wdt.c
-@@ -32,11 +32,14 @@
- #include <linux/uaccess.h>
- #include <linux/slab.h>
- #include <linux/io.h>
-+#include <linux/jiffies.h>
-+#include <linux/delay.h>
- 
- #include <asm/smp_twd.h>
- 
- struct mpcore_wdt {
- 	unsigned long	timer_alive;
-+	unsigned long	timer_rate;
- 	struct device	*dev;
- 	void __iomem	*base;
- 	int		irq;
-@@ -98,14 +101,12 @@ static void mpcore_wdt_keepalive(struct
- 	unsigned long count;
- 
- 	spin_lock(&wdt_lock);
--	/* Assume prescale is set to 256 */
--	count =  __raw_readl(wdt->base + TWD_WDOG_COUNTER);
--	count = (0xFFFFFFFFU - count) * (HZ / 5);
--	count = (count / 256) * mpcore_margin;
-+	count = (wdt->timer_rate / 256) * mpcore_margin;
- 
- 	/* Reload the counter */
- 	writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
- 	wdt->perturb = wdt->perturb ? 0 : 1;
-+
- 	spin_unlock(&wdt_lock);
- }
- 
-@@ -329,6 +330,8 @@ static int __devinit mpcore_wdt_probe(st
- 	struct mpcore_wdt *wdt;
- 	struct resource *res;
- 	int ret;
-+	unsigned long count;
-+	u64 waitjiffies;
- 
- 	/* We only accept one device, and it must have an id of -1 */
- 	if (dev->id != -1)
-@@ -375,6 +378,22 @@ static int __devinit mpcore_wdt_probe(st
- 		goto err_irq;
- 	}
- 
-+	waitjiffies = get_jiffies_64() + 1;
-+	while (get_jiffies_64() < waitjiffies)
-+		udelay(10);
-+
-+	waitjiffies += 5;
-+
-+	__raw_writel(0x00000001, wdt->base + TWD_WDOG_CONTROL);
-+	__raw_writel(0xFFFFFFFFU, wdt->base + TWD_WDOG_LOAD);
-+
-+	while (get_jiffies_64() < waitjiffies)
-+		udelay(10);
-+
-+	count =  __raw_readl(wdt->base + TWD_WDOG_COUNTER);
-+
-+	wdt->timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
-+
- 	mpcore_wdt_stop(wdt);
- 	platform_set_drvdata(dev, wdt);
- 	mpcore_wdt_dev = dev;

target/linux/cns3xxx/patches-3.0/100-laguna_support.patch

@@ -555,12 +555,13 @@
 + * Watchdog
 + */
 +
-+static struct resource laguna_watchdog_resource[] = {
++static struct resource laguna_watchdog_resources[] = {
-+	{
++	[0] = {
 +		.start	= CNS3XXX_TC11MP_TWD_BASE,
 +		.end	= CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
 +		.flags	= IORESOURCE_MEM,
-+	},{
++	},
++	[1] = {
 +		.start	= IRQ_LOCALWDOG,
 +		.end	= IRQ_LOCALWDOG,
 +		.flags	= IORESOURCE_IRQ,
@@ -570,8 +571,8 @@
 +static struct platform_device laguna_watchdog = {
 +	.name		= "mpcore_wdt",
 +	.id		= -1,
-+	.num_resources = ARRAY_SIZE(laguna_watchdog_resource),
++	.num_resources	= ARRAY_SIZE(laguna_watchdog_resources),
-+	.resource = laguna_watchdog_resource,
++	.resource	= laguna_watchdog_resources,
 +};
 +
 +/*
@@ -580,6 +581,8 @@
 +
 +static void __init laguna_init(void)
 +{
++	cns3xxx_l2x0_init();
++
 +	platform_device_register(&laguna_watchdog);
 +
 +	platform_device_register(&laguna_i2c_controller);
@@ -587,7 +590,6 @@
 +	i2c_register_board_info(0, laguna_i2c_devices,
 +			ARRAY_SIZE(laguna_i2c_devices));
 +
-+
 +	pm_power_off = cns3xxx_power_off;
 +}
 +
@@ -614,11 +616,9 @@
 +{
 +	cns3xxx_map_io();
 +	iotable_init(laguna_io_desc, ARRAY_SIZE(laguna_io_desc));
-+
 +	laguna_early_serial_setup();
 +}
 +
-+
 +static int __init laguna_model_setup(void)
 +{
 +	u32 __iomem *mem;
@@ -764,12 +764,13 @@
 +MACHINE_END
 --- a/arch/arm/mach-cns3xxx/Kconfig
 +++ b/arch/arm/mach-cns3xxx/Kconfig
-@@ -10,4 +10,13 @@ config MACH_CNS3420VB
+@@ -11,4 +11,14 @@ config MACH_CNS3420VB
  	  This is a platform with an on-board ARM11 MPCore and has support
  	  for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
  
 +config MACH_GW2388
 +	bool "Support for Gateworks Laguna Platform"
++	select HAVE_ARM_SCU if SMP
 +	select MIGHT_HAVE_PCI
 +	help
 +	  Include support for the Gateworks Laguna Platform
@@ -785,10 +786,10 @@
  #include <asm/mach/irq.h>
  #include <asm/hardware/gic.h>
 +#include <asm/smp_twd.h>
+ #include <asm/hardware/cache-l2x0.h>
  #include <mach/cns3xxx.h>
  #include "core.h"
- 
+@@ -61,11 +62,24 @@ static struct map_desc cns3xxx_io_desc[]
-@@ -60,11 +61,24 @@ static struct map_desc cns3xxx_io_desc[]
  		.pfn		= __phys_to_pfn(CNS3XXX_PM_BASE),
  		.length		= SZ_4K,
  		.type		= MT_DEVICE,
@@ -962,7 +963,7 @@
 -device_initcall(cns3xxx_pcie_init);
 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -175,6 +175,8 @@ static void __init cns3420_init(void)
+@@ -199,6 +199,8 @@ static void __init cns3420_init(void)
  	cns3xxx_ahci_init();
  	cns3xxx_sdhci_init();
  

target/linux/cns3xxx/patches-3.0/102-cns3xxx_timers.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm/mach-cns3xxx/core.c
 +++ b/arch/arm/mach-cns3xxx/core.c
-@@ -117,12 +117,13 @@ static void cns3xxx_timer_set_mode(enum
+@@ -118,12 +118,13 @@ static void cns3xxx_timer_set_mode(enum
  
  	switch (mode) {
  	case CLOCK_EVT_MODE_PERIODIC:
@@ -15,7 +15,7 @@
  		ctrl |= (1 << 2) | (1 << 9);
  		break;
  	case CLOCK_EVT_MODE_UNUSED:
-@@ -147,11 +148,11 @@ static int cns3xxx_timer_set_next_event(
+@@ -148,11 +149,11 @@ static int cns3xxx_timer_set_next_event(
  
  static struct clock_event_device cns3xxx_tmr1_clockevent = {
  	.name		= "cns3xxx timer1",
@@ -29,7 +29,7 @@
  	.cpumask	= cpu_all_mask,
  };
  
-@@ -193,6 +194,35 @@ static struct irqaction cns3xxx_timer_ir
+@@ -194,6 +195,35 @@ static struct irqaction cns3xxx_timer_ir
  	.handler	= cns3xxx_timer_interrupt,
  };
  
@@ -65,7 +65,7 @@
  /*
   * Set up the clock source and clock events devices
   */
-@@ -210,13 +240,12 @@ static void __init __cns3xxx_timer_init(
+@@ -211,13 +241,12 @@ static void __init __cns3xxx_timer_init(
  	/* stop free running timer3 */
  	writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
  
@@ -82,7 +82,7 @@
  	/* mask irq, non-mask timer1 overflow */
  	irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
  	irq_mask &= ~(1 << 2);
-@@ -228,23 +257,9 @@ static void __init __cns3xxx_timer_init(
+@@ -229,23 +258,9 @@ static void __init __cns3xxx_timer_init(
  	val |= (1 << 9);
  	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
  

target/linux/cns3xxx/patches-3.0/103-cns3xxx_l2cache.patch

@@ -1,61 +0,0 @@
---- a/arch/arm/mach-cns3xxx/core.c
-+++ b/arch/arm/mach-cns3xxx/core.c
-@@ -15,6 +15,7 @@
- #include <asm/mach/map.h>
- #include <asm/mach/time.h>
- #include <asm/mach/irq.h>
-+#include <asm/hardware/cache-l2x0.h>
- #include <asm/hardware/gic.h>
- #include <asm/smp_twd.h>
- #include <mach/cns3xxx.h>
-@@ -71,15 +72,29 @@ static struct map_desc cns3xxx_io_desc[]
- 		.pfn		= __phys_to_pfn(CNS3XXX_SSP_BASE),
- 		.length		= SZ_4K,
- 		.type		= MT_DEVICE,
-+	}, {
-+		.virtual	= CNS3XXX_L2C_BASE_VIRT,
-+		.pfn		= __phys_to_pfn(CNS3XXX_L2C_BASE),
-+		.length		= SZ_4K,
-+		.type		= MT_DEVICE,
- 	},
- };
- 
- void __init cns3xxx_map_io(void)
- {
-+	iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
-+#ifdef CONFIG_CACHE_L2X0
-+	void __iomem *l2x0_base = (void __iomem *) CNS3XXX_L2C_BASE_VIRT;
-+
-+	/* set RAM latencies to 1 cycle for this core tile. */
-+	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
-+	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
-+
-+	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
-+#endif
- #ifdef CONFIG_LOCAL_TIMERS
- 	twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
- #endif
--	iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
- }
- 
- /* used by entry-macro.S */
---- a/arch/arm/mm/Kconfig
-+++ b/arch/arm/mm/Kconfig
-@@ -821,7 +821,7 @@ config CACHE_L2X0
- 	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
- 		   REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
- 		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
--		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
-+		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_CNS3XXX
- 	default y
- 	select OUTER_CACHE
- 	select OUTER_CACHE_SYNC
-@@ -866,7 +866,7 @@ config ARM_L1_CACHE_SHIFT
- config ARM_DMA_MEM_BUFFERABLE
- 	bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
- 	depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
--		     MACH_REALVIEW_PB11MP)
-+		     MACH_REALVIEW_PB11MP || ARCH_CNS3XXX)
- 	default y if CPU_V6 || CPU_V6K || CPU_V7
- 	help
- 	  Historically, the kernel has used strongly ordered mappings to

target/linux/cns3xxx/patches-3.0/104-cns3xxx_gpio.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
-@@ -191,7 +191,7 @@ static struct map_desc cns3420_io_desc[]
+@@ -215,7 +215,7 @@ static struct map_desc cns3420_io_desc[]
  
  static void __init cns3420_map_io(void)
  {
@@ -12,14 +12,14 @@
 --- a/arch/arm/mach-cns3xxx/core.c
 +++ b/arch/arm/mach-cns3xxx/core.c
 @@ -18,6 +18,7 @@
- #include <asm/hardware/cache-l2x0.h>
  #include <asm/hardware/gic.h>
  #include <asm/smp_twd.h>
+ #include <asm/hardware/cache-l2x0.h>
 +#include <asm/gpio.h>
  #include <mach/cns3xxx.h>
  #include "core.h"
  
-@@ -80,7 +81,89 @@ static struct map_desc cns3xxx_io_desc[]
+@@ -75,12 +76,96 @@ static struct map_desc cns3xxx_io_desc[]
  	},
  };
  
@@ -108,21 +108,20 @@
 +
 +void __init cns3xxx_common_init(void)
  {
- 	iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
- #ifdef CONFIG_CACHE_L2X0
-@@ -95,6 +178,7 @@ void __init cns3xxx_map_io(void)
  #ifdef CONFIG_LOCAL_TIMERS
  	twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
  #endif
+ 	iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
++
 +	gpiochip_add(&cns3xxx_gpio_chip);
  }
  
  /* used by entry-macro.S */
 --- a/arch/arm/mach-cns3xxx/core.h
 +++ b/arch/arm/mach-cns3xxx/core.h
-@@ -13,7 +13,7 @@
+@@ -19,7 +19,7 @@ void __init cns3xxx_l2x0_init(void);
- 
+ static inline void cns3xxx_l2x0_init(void) {}
- extern struct sys_timer cns3xxx_timer;
+ #endif /* CONFIG_CACHE_L2X0 */
  
 -void __init cns3xxx_map_io(void);
 +void __init cns3xxx_common_init(void);
@@ -131,12 +130,12 @@
  
 --- a/arch/arm/mach-cns3xxx/laguna.c
 +++ b/arch/arm/mach-cns3xxx/laguna.c
-@@ -609,7 +609,7 @@ static struct map_desc laguna_io_desc[]
+@@ -611,7 +611,7 @@ static struct map_desc laguna_io_desc[]
  
  static void __init laguna_map_io(void)
  {
 -	cns3xxx_map_io();
 +	cns3xxx_common_init();
  	iotable_init(laguna_io_desc, ARRAY_SIZE(laguna_io_desc));
- 
  	laguna_early_serial_setup();
+ }

target/linux/cns3xxx/patches-3.0/105-cns3xxx_pcie_io.patch

@@ -1,7 +1,7 @@
 --- a/arch/arm/mach-cns3xxx/core.c
 +++ b/arch/arm/mach-cns3xxx/core.c
-@@ -78,6 +78,16 @@ static struct map_desc cns3xxx_io_desc[]
+@@ -73,6 +73,16 @@ static struct map_desc cns3xxx_io_desc[]
- 		.pfn		= __phys_to_pfn(CNS3XXX_L2C_BASE),
+ 		.pfn		= __phys_to_pfn(CNS3XXX_SSP_BASE),
  		.length		= SZ_4K,
  		.type		= MT_DEVICE,
 +	}, {
@@ -17,7 +17,7 @@
  	},
  };
  
-@@ -184,13 +194,13 @@ void __init cns3xxx_common_init(void)
+@@ -171,13 +181,13 @@ void __init cns3xxx_common_init(void)
  /* used by entry-macro.S */
  void __init cns3xxx_init_irq(void)
  {
@@ -34,7 +34,7 @@
  	u32 clkctrl;
  
  	printk(KERN_INFO "powering system down...\n");
-@@ -364,7 +374,7 @@ static void __init __cns3xxx_timer_init(
+@@ -351,7 +361,7 @@ static void __init __cns3xxx_timer_init(
  
  static void __init cns3xxx_timer_init(void)
  {