atheros: nuke clocksoure init patch

SVN-Revision: 20937

target/linux/atheros/patches-2.6.30/002-mips_clocksource_init_war.patch

@@ -1,56 +0,0 @@
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -15,6 +15,22 @@
- #include <asm/cevt-r4k.h>
- 
- /*
-+ * Compare interrupt can be routed and latched outside the core,
-+ * so a single execution hazard barrier may not be enough to give
-+ * it time to clear as seen in the Cause register.  4 time the
-+ * pipeline depth seems reasonably conservative, and empirically
-+ * works better in configurations with high CPU/bus clock ratios.
-+ */
-+
-+#define compare_change_hazard() \
-+	do { \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+	} while (0)
-+
-+/*
-  * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
-  * of these routines with SMTC-specific variants.
-  */
-@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long
- 	cnt = read_c0_count();
- 	cnt += delta;
- 	write_c0_compare(cnt);
-+	compare_change_hazard();
- 	res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
- 	return res;
- }
-@@ -99,22 +116,6 @@ static int c0_compare_int_pending(void)
- 	return (read_c0_cause() >> cp0_compare_irq) & 0x100;
- }
- 
--/*
-- * Compare interrupt can be routed and latched outside the core,
-- * so a single execution hazard barrier may not be enough to give
-- * it time to clear as seen in the Cause register.  4 time the
-- * pipeline depth seems reasonably conservative, and empirically
-- * works better in configurations with high CPU/bus clock ratios.
-- */
--
--#define compare_change_hazard() \
--	do { \
--		irq_disable_hazard(); \
--		irq_disable_hazard(); \
--		irq_disable_hazard(); \
--		irq_disable_hazard(); \
--	} while (0)
--
- int c0_compare_int_usable(void)
- {
- 	unsigned int delta;

target/linux/atheros/patches-2.6.32/002-mips_clocksource_init_war.patch

@@ -1,56 +0,0 @@
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -16,6 +16,22 @@
- #include <asm/cevt-r4k.h>
- 
- /*
-+ * Compare interrupt can be routed and latched outside the core,
-+ * so a single execution hazard barrier may not be enough to give
-+ * it time to clear as seen in the Cause register.  4 time the
-+ * pipeline depth seems reasonably conservative, and empirically
-+ * works better in configurations with high CPU/bus clock ratios.
-+ */
-+
-+#define compare_change_hazard() \
-+	do { \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+	} while (0)
-+
-+/*
-  * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
-  * of these routines with SMTC-specific variants.
-  */
-@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
- 	cnt = read_c0_count();
- 	cnt += delta;
- 	write_c0_compare(cnt);
-+	compare_change_hazard();
- 	res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
- 	return res;
- }
-@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void)
- 	return (read_c0_cause() >> cp0_compare_irq) & 0x100;
- }
- 
--/*
-- * Compare interrupt can be routed and latched outside the core,
-- * so a single execution hazard barrier may not be enough to give
-- * it time to clear as seen in the Cause register.  4 time the
-- * pipeline depth seems reasonably conservative, and empirically
-- * works better in configurations with high CPU/bus clock ratios.
-- */
--
--#define compare_change_hazard() \
--	do { \
--		irq_disable_hazard(); \
--		irq_disable_hazard(); \
--		irq_disable_hazard(); \
--		irq_disable_hazard(); \
--	} while (0)
--
- int c0_compare_int_usable(void)
- {
- 	unsigned int delta;

target/linux/atheros/patches-2.6.33/002-mips_clocksource_init_war.patch

@@ -1,56 +0,0 @@
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -16,6 +16,22 @@
- #include <asm/cevt-r4k.h>
- 
- /*
-+ * Compare interrupt can be routed and latched outside the core,
-+ * so a single execution hazard barrier may not be enough to give
-+ * it time to clear as seen in the Cause register.  4 time the
-+ * pipeline depth seems reasonably conservative, and empirically
-+ * works better in configurations with high CPU/bus clock ratios.
-+ */
-+
-+#define compare_change_hazard() \
-+	do { \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+	} while (0)
-+
-+/*
-  * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
-  * of these routines with SMTC-specific variants.
-  */
-@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
- 	cnt = read_c0_count();
- 	cnt += delta;
- 	write_c0_compare(cnt);
-+	compare_change_hazard();
- 	res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
- 	return res;
- }
-@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void)
- 	return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
- }
- 
--/*
-- * Compare interrupt can be routed and latched outside the core,
-- * so a single execution hazard barrier may not be enough to give
-- * it time to clear as seen in the Cause register.  4 time the
-- * pipeline depth seems reasonably conservative, and empirically
-- * works better in configurations with high CPU/bus clock ratios.
-- */
--
--#define compare_change_hazard() \
--	do { \
--		irq_disable_hazard(); \
--		irq_disable_hazard(); \
--		irq_disable_hazard(); \
--		irq_disable_hazard(); \
--	} while (0)
--
- int c0_compare_int_usable(void)
- {
- 	unsigned int delta;