Revert "ramips: pci: sync with staging driver"
This reverts commit e07baec9fa.
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
parent
8a570921b5
commit
784943e3f2
1 changed files with 157 additions and 139 deletions
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@ -52,103 +52,108 @@
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <ralink_regs.h>
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extern void pcie_phy_init(void);
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extern void chk_phy_pll(void);
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/*
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* These functions and structures provide the BIOS scan and mapping of the PCI
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* devices.
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*/
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#define RALINK_PCIE0_CLK_EN (1<<24)
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#define RALINK_PCIE1_CLK_EN (1<<25)
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#define RALINK_PCIE2_CLK_EN (1<<26)
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#define RALINK_PCIE0_CLK_EN (1<<24)
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#define RALINK_PCIE1_CLK_EN (1<<25)
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#define RALINK_PCIE2_CLK_EN (1<<26)
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#define RALINK_PCI_CONFIG_ADDR 0x20
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#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
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#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
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#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
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#define RALINK_PCIE0_RST (1<<24)
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#define RALINK_PCIE1_RST (1<<25)
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#define RALINK_PCIE2_RST (1<<26)
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#define RALINK_SYSCTL_BASE 0xBE000000
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#define RALINK_PCI_CONFIG_ADDR 0x20
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#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
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#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
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#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
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#define RALINK_PCIE0_RST (1<<24)
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#define RALINK_PCIE1_RST (1<<25)
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#define RALINK_PCIE2_RST (1<<26)
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#define RALINK_SYSCTL_BASE 0xBE000000
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#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
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#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
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#define RALINK_PCI_BASE 0xBE140000
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#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
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#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
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#define RALINK_PCI_BASE 0xBE140000
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#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
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#define RT6855_PCIE0_OFFSET 0x2000
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#define RT6855_PCIE1_OFFSET 0x3000
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#define RT6855_PCIE2_OFFSET 0x4000
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#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
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#define RT6855_PCIE0_OFFSET 0x2000
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#define RT6855_PCIE1_OFFSET 0x3000
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#define RT6855_PCIE2_OFFSET 0x4000
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#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
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#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
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#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
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#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
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#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
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#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
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#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
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#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
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#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
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#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
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#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
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#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
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#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
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#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
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#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
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#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
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#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
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#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
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#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
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#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
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#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
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#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
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#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
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#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
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#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
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#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
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#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
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#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
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#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
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#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
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#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
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#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
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#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
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#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
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#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
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#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
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#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
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#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
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#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
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#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
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#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
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#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
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#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
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#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
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#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
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#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
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#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
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#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
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#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
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#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
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#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
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#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
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#define MV_WRITE(ofs, data) \
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*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
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#define MV_READ(ofs, data) \
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*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
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#define MV_READ_DATA(ofs) \
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le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
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#define MV_WRITE_16(ofs, data) \
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*(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
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#define MV_READ_16(ofs, data) \
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*(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
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#define MV_WRITE(ofs, data) \
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*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
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#define MV_READ(ofs, data) \
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*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
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#define MV_READ_DATA(ofs) \
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le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
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#define MV_WRITE_8(ofs, data) \
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*(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
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#define MV_READ_8(ofs, data) \
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*(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
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#define MV_WRITE_16(ofs, data) \
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*(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
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#define MV_READ_16(ofs, data) \
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*(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
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#define RALINK_PCI_MM_MAP_BASE 0x60000000
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#define RALINK_PCI_IO_MAP_BASE 0x1e160000
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#define MV_WRITE_8(ofs, data) \
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*(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
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#define MV_READ_8(ofs, data) \
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*(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
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#define RALINK_PCI_MM_MAP_BASE 0x60000000
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#define RALINK_PCI_IO_MAP_BASE 0x1e160000
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#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
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#define ASSERT_SYSRST_PCIE(val) \
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do { \
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if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
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RALINK_RSTCTRL |= val; \
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else \
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RALINK_RSTCTRL &= ~val; \
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} while(0)
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#define DEASSERT_SYSRST_PCIE(val) \
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do { \
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if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
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RALINK_RSTCTRL &= ~val; \
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else \
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RALINK_RSTCTRL |= val; \
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} while(0)
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#define ASSERT_SYSRST_PCIE(val) do { \
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if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
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RALINK_RSTCTRL |= val; \
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else \
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RALINK_RSTCTRL &= ~val; \
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} while(0)
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#define DEASSERT_SYSRST_PCIE(val) do { \
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if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
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RALINK_RSTCTRL &= ~val; \
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else \
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RALINK_RSTCTRL |= val; \
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} while(0)
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#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
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#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
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#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
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@ -183,6 +188,8 @@ static int pcie_link_status = 0;
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#define PCI_ACCESS_WRITE_2 4
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#define PCI_ACCESS_WRITE_4 5
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static int pcie_irq[3];
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static int config_access(unsigned char access_type, struct pci_bus *bus,
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unsigned int devfn, unsigned int where, u32 * data)
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{
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@ -268,6 +275,7 @@ write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
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{
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@ -295,12 +303,13 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u
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}
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struct pci_ops mt7621_pci_ops= {
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.read = pci_config_read,
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.read = pci_config_read,
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.write = pci_config_write,
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};
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static struct resource mt7621_res_pci_mem1;
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static struct resource mt7621_res_pci_io1;
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static struct pci_controller mt7621_controller = {
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.pci_ops = &mt7621_pci_ops,
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.mem_resource = &mt7621_res_pci_mem1,
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@ -313,10 +322,10 @@ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned l
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unsigned int address_reg, data_reg, address;
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address_reg = RALINK_PCI_CONFIG_ADDR;
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data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
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data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
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address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
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MV_WRITE(address_reg, address);
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MV_READ(data_reg, val);
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MV_WRITE(address_reg, address);
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MV_READ(data_reg, val);
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return;
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}
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@ -333,6 +342,7 @@ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned
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return;
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}
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int
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pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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@ -361,8 +371,11 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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void
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set_pcie_phy(u32 *addr, int start_b, int bits, int val)
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{
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// printk("0x%p:", addr);
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// printk(" %x", *addr);
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*(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
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*(unsigned int *)(addr) |= val << start_b;
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// printk(" -> %x\n", *addr);
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}
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void
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@ -389,75 +402,75 @@ set_phy_for_ssc(void)
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/* Debug Xtal Type */
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
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if(reg <= 5 && reg >= 3) { // 40MHz Xtal
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
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if(reg <= 5 && reg >= 3) { // 40MHz Xtal
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
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printk("***** Xtal 40MHz *****\n");
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} else { // 25MHz | 20MHz Xtal
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
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if (reg >= 6) {
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
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if (reg >= 6) {
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printk("***** Xtal 25MHz *****\n");
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
|
||||
} else {
|
||||
printk("***** Xtal 20MHz *****\n");
|
||||
}
|
||||
}
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
|
||||
if(reg <= 5 && reg >= 3) { // 40MHz Xtal
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
|
||||
if(reg <= 5 && reg >= 3) { // 40MHz Xtal
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
|
||||
}
|
||||
/* Enable PHY and disable force mode */
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
|
||||
|
||||
/* Set PCIe Port2 PHY to disable SSC */
|
||||
/* Debug Xtal Type */
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
|
||||
if(reg <= 5 && reg >= 3) { // 40MHz Xtal
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
|
||||
if(reg <= 5 && reg >= 3) { // 40MHz Xtal
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
|
||||
} else { // 25MHz | 20MHz Xtal
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
|
||||
if (reg >= 6) { // 25MHz Xtal
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
|
||||
if (reg >= 6) { // 25MHz Xtal
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
|
||||
}
|
||||
}
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
|
||||
if(reg <= 5 && reg >= 3) { // 40MHz Xtal
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
|
||||
if(reg <= 5 && reg >= 3) { // 40MHz Xtal
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
|
||||
}
|
||||
/* Enable PHY and disable force mode */
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
|
||||
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
|
||||
}
|
||||
|
||||
void setup_cm_memory_region(struct resource *mem_resource)
|
||||
|
|
@ -465,21 +478,25 @@ void setup_cm_memory_region(struct resource *mem_resource)
|
|||
resource_size_t mask;
|
||||
if (mips_cps_numiocu(0)) {
|
||||
/* FIXME: hardware doesn't accept mask values with 1s after
|
||||
* 0s (e.g. 0xffef), so it would be great to warn if that's
|
||||
* about to happen */
|
||||
0s (e.g. 0xffef), so it would be great to warn if that's
|
||||
about to happen */
|
||||
mask = ~(mem_resource->end - mem_resource->start);
|
||||
|
||||
write_gcr_reg1_base(mem_resource->start);
|
||||
write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
|
||||
printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
|
||||
(unsigned long long)read_gcr_reg1_base(),
|
||||
(unsigned long long)read_gcr_reg1_mask());
|
||||
printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
|
||||
read_gcr_reg1_base(),
|
||||
read_gcr_reg1_mask());
|
||||
}
|
||||
}
|
||||
|
||||
static int mt7621_pci_probe(struct platform_device *pdev)
|
||||
{
|
||||
unsigned long val = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 3; i++)
|
||||
pcie_irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
|
||||
|
||||
iomem_resource.start = 0;
|
||||
iomem_resource.end= ~0;
|
||||
|
|
@ -491,6 +508,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
|
|||
val |= RALINK_PCIE2_RST;
|
||||
|
||||
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
|
||||
printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
|
||||
|
||||
*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
|
||||
*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
|
||||
|
|
@ -506,17 +524,17 @@ static int mt7621_pci_probe(struct platform_device *pdev)
|
|||
val |= RALINK_PCIE2_RST;
|
||||
|
||||
DEASSERT_SYSRST_PCIE(val);
|
||||
printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
|
||||
|
||||
if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
|
||||
bypass_pipe_rst();
|
||||
set_phy_for_ssc();
|
||||
printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
|
||||
|
||||
read_config(0, 0, 0, 0x70c, &val);
|
||||
printk("Port 0 N_FTS = %x\n", (unsigned int)val);
|
||||
|
||||
read_config(0, 1, 0, 0x70c, &val);
|
||||
printk("Port 1 N_FTS = %x\n", (unsigned int)val);
|
||||
|
||||
read_config(0, 2, 0, 0x70c, &val);
|
||||
printk("Port 2 N_FTS = %x\n", (unsigned int)val);
|
||||
|
||||
|
|
@ -544,7 +562,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
|
|||
pcie_link_status |= 1<<0;
|
||||
RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
|
||||
}
|
||||
|
||||
if(( RALINK_PCI1_STATUS & 0x1) == 0)
|
||||
{
|
||||
printk("PCIE1 no card, disable it(RST&CLK)\n");
|
||||
|
|
@ -555,7 +572,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
|
|||
pcie_link_status |= 1<<1;
|
||||
RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
|
||||
}
|
||||
|
||||
if (( RALINK_PCI2_STATUS & 0x1) == 0) {
|
||||
printk("PCIE2 no card, disable it(RST&CLK)\n");
|
||||
ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
|
||||
|
|
@ -565,7 +581,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
|
|||
pcie_link_status |= 1<<2;
|
||||
RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
|
||||
}
|
||||
|
||||
if (pcie_link_status == 0)
|
||||
return 0;
|
||||
|
||||
|
|
@ -605,10 +620,12 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
|
|||
RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
|
||||
break;
|
||||
}
|
||||
printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
|
||||
//printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
|
||||
|
||||
/*
|
||||
ioport_resource.start = mt7621_res_pci_io1.start;
|
||||
ioport_resource.end = mt7621_res_pci_io1.end;
|
||||
ioport_resource.end = mt7621_res_pci_io1.end;
|
||||
*/
|
||||
|
||||
RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
|
||||
|
|
@ -621,7 +638,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
|
|||
RALINK_PCI0_CLASS = 0x06040001;
|
||||
printk("PCIE0 enabled\n");
|
||||
}
|
||||
|
||||
//PCIe1
|
||||
if ((pcie_link_status & 0x2) != 0) {
|
||||
RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
|
||||
|
|
@ -629,7 +645,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
|
|||
RALINK_PCI1_CLASS = 0x06040001;
|
||||
printk("PCIE1 enabled\n");
|
||||
}
|
||||
|
||||
//PCIe2
|
||||
if ((pcie_link_status & 0x4) != 0) {
|
||||
RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
|
||||
|
|
@ -642,6 +657,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
|
|||
case 7:
|
||||
read_config(0, 2, 0, 0x4, &val);
|
||||
write_config(0, 2, 0, 0x4, val|0x4);
|
||||
// write_config(0, 1, 0, 0x4, val|0x7);
|
||||
read_config(0, 2, 0, 0x70c, &val);
|
||||
val &= ~(0xff)<<8;
|
||||
val |= 0x50<<8;
|
||||
|
|
@ -651,6 +667,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
|
|||
case 6:
|
||||
read_config(0, 1, 0, 0x4, &val);
|
||||
write_config(0, 1, 0, 0x4, val|0x4);
|
||||
// write_config(0, 1, 0, 0x4, val|0x7);
|
||||
read_config(0, 1, 0, 0x70c, &val);
|
||||
val &= ~(0xff)<<8;
|
||||
val |= 0x50<<8;
|
||||
|
|
@ -658,6 +675,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
|
|||
default:
|
||||
read_config(0, 0, 0, 0x4, &val);
|
||||
write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
|
||||
// write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
|
||||
read_config(0, 0, 0, 0x70c, &val);
|
||||
val &= ~(0xff)<<8;
|
||||
val |= 0x50<<8;
|
||||
|
|
|
|||
Loading…
Reference in a new issue