atheros: fix too short msleep
Use msleep(20) instead of msleep(10) to make code closer to reality since msleep can sleep for up to 20ms even we request shorter delay. All updated calls are located in PCI initialization routine which is called only once upon device boot. So there should be no performance issues caused by more longer delay. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> SVN-Revision: 41096
This commit is contained in:
parent
e49636472d
commit
75b4c400c7
1 changed files with 2 additions and 2 deletions
|
@ -198,11 +198,11 @@
|
||||||
+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/
|
+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/
|
||||||
+
|
+
|
||||||
+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
|
+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
|
||||||
+ msleep(10);
|
+ msleep(20);
|
||||||
+
|
+
|
||||||
+ reg &= ~AR2315_RESET_PCIDMA;
|
+ reg &= ~AR2315_RESET_PCIDMA;
|
||||||
+ ar231x_write_reg(AR2315_RESET, reg);
|
+ ar231x_write_reg(AR2315_RESET, reg);
|
||||||
+ msleep(10);
|
+ msleep(20);
|
||||||
+
|
+
|
||||||
+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
|
+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
|
||||||
+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
|
+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
|
||||||
|
|
Loading…
Reference in a new issue