uboot-lantiq: drop unused board patches
None of the boards is supported by lede. No need to keep the patches in the lede tree. Signed-off-by: Mathias Kresin <dev@kresin.me>
This commit is contained in:
Mathias Kresin
John Crispin
parent
21bdd79b33
commit
74b1687be3
7 changed files with 6 additions and 1387 deletions
|
|
@ -1,307 +0,0 @@
|
|||
From 0597056e2ba19ea783ef5c3d14c75c4722740e48 Mon Sep 17 00:00:00 2001
|
||||
From: Luka Perkov <luka@openwrt.org>
|
||||
Date: Sun, 10 Mar 2013 17:59:56 +0100
|
||||
Subject: MIPS: add board support for ZTE ZXHN H367N
|
||||
|
||||
Signed-off-by: Luka Perkov <luka@openwrt.org>
|
||||
|
||||
--- /dev/null
|
||||
+++ b/board/zte/zxhnh367n/Makefile
|
||||
@@ -0,0 +1,27 @@
|
||||
+#
|
||||
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+include $(TOPDIR)/config.mk
|
||||
+
|
||||
+LIB = $(obj)lib$(BOARD).o
|
||||
+
|
||||
+COBJS = $(BOARD).o
|
||||
+
|
||||
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
+OBJS := $(addprefix $(obj),$(COBJS))
|
||||
+SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
+
|
||||
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
+
|
||||
+#########################################################################
|
||||
+
|
||||
+# defines $(obj).depend target
|
||||
+include $(SRCTREE)/rules.mk
|
||||
+
|
||||
+sinclude $(obj).depend
|
||||
+
|
||||
+#########################################################################
|
||||
--- /dev/null
|
||||
+++ b/board/zte/zxhnh367n/config.mk
|
||||
@@ -0,0 +1,7 @@
|
||||
+#
|
||||
+# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
|
||||
--- /dev/null
|
||||
+++ b/board/zte/zxhnh367n/ddr_settings.h
|
||||
@@ -0,0 +1,70 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
|
||||
+ *
|
||||
+ * The values have been extracted from original ZTE U-Boot.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#define MC_CCR00_VALUE 0x101
|
||||
+#define MC_CCR01_VALUE 0x1000101
|
||||
+#define MC_CCR02_VALUE 0x1010000
|
||||
+#define MC_CCR03_VALUE 0x100
|
||||
+#define MC_CCR04_VALUE 0x1000000
|
||||
+#define MC_CCR05_VALUE 0x1000101
|
||||
+#define MC_CCR06_VALUE 0x1000100
|
||||
+#define MC_CCR07_VALUE 0x1010000
|
||||
+#define MC_CCR08_VALUE 0x1000101
|
||||
+#define MC_CCR09_VALUE 0x0
|
||||
+#define MC_CCR10_VALUE 0x2000100
|
||||
+#define MC_CCR11_VALUE 0x2000401
|
||||
+#define MC_CCR12_VALUE 0x30000
|
||||
+#define MC_CCR13_VALUE 0x202
|
||||
+#define MC_CCR14_VALUE 0x7080A0F
|
||||
+#define MC_CCR15_VALUE 0x2040F
|
||||
+#define MC_CCR16_VALUE 0x40000
|
||||
+#define MC_CCR17_VALUE 0x70102
|
||||
+#define MC_CCR18_VALUE 0x4020002
|
||||
+#define MC_CCR19_VALUE 0x30302
|
||||
+#define MC_CCR20_VALUE 0x8000700
|
||||
+#define MC_CCR21_VALUE 0x40F020A
|
||||
+#define MC_CCR22_VALUE 0x0
|
||||
+#define MC_CCR23_VALUE 0xC020000
|
||||
+#define MC_CCR24_VALUE 0x4401B04
|
||||
+#define MC_CCR25_VALUE 0x0
|
||||
+#define MC_CCR26_VALUE 0x0
|
||||
+#define MC_CCR27_VALUE 0x6420000
|
||||
+#define MC_CCR28_VALUE 0x0
|
||||
+#define MC_CCR29_VALUE 0x0
|
||||
+#define MC_CCR30_VALUE 0x798
|
||||
+#define MC_CCR31_VALUE 0x0
|
||||
+#define MC_CCR32_VALUE 0x0
|
||||
+#define MC_CCR33_VALUE 0x650000
|
||||
+#define MC_CCR34_VALUE 0x200C8
|
||||
+#define MC_CCR35_VALUE 0x1D445D
|
||||
+#define MC_CCR36_VALUE 0xC8
|
||||
+#define MC_CCR37_VALUE 0xC351
|
||||
+#define MC_CCR38_VALUE 0x0
|
||||
+#define MC_CCR39_VALUE 0x141F04
|
||||
+#define MC_CCR40_VALUE 0x142704
|
||||
+#define MC_CCR41_VALUE 0x141B42
|
||||
+#define MC_CCR42_VALUE 0x141B42
|
||||
+#define MC_CCR43_VALUE 0x566504
|
||||
+#define MC_CCR44_VALUE 0x566504
|
||||
+#define MC_CCR45_VALUE 0x565F17
|
||||
+#define MC_CCR46_VALUE 0x565F17
|
||||
+#define MC_CCR47_VALUE 0x0
|
||||
+#define MC_CCR48_VALUE 0x0
|
||||
+#define MC_CCR49_VALUE 0x0
|
||||
+#define MC_CCR50_VALUE 0x0
|
||||
+#define MC_CCR51_VALUE 0x0
|
||||
+#define MC_CCR52_VALUE 0x133
|
||||
+#define MC_CCR53_VALUE 0xF3014B27
|
||||
+#define MC_CCR54_VALUE 0xF3014B27
|
||||
+#define MC_CCR55_VALUE 0xF3014B27
|
||||
+#define MC_CCR56_VALUE 0xF3014B27
|
||||
+#define MC_CCR57_VALUE 0x7800301
|
||||
+#define MC_CCR58_VALUE 0x7800301
|
||||
+#define MC_CCR59_VALUE 0x7800301
|
||||
+#define MC_CCR60_VALUE 0x7800301
|
||||
+#define MC_CCR61_VALUE 0x4
|
||||
--- /dev/null
|
||||
+++ b/board/zte/zxhnh367n/zxhnh367n.c
|
||||
@@ -0,0 +1,97 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <asm/gpio.h>
|
||||
+#include <asm/lantiq/eth.h>
|
||||
+#include <asm/lantiq/chipid.h>
|
||||
+#include <asm/lantiq/cpu.h>
|
||||
+#include <asm/arch/gphy.h>
|
||||
+
|
||||
+#if defined(CONFIG_SPL_BUILD)
|
||||
+#define do_gpio_init 1
|
||||
+#define do_pll_init 1
|
||||
+#define do_dcdc_init 0
|
||||
+#elif defined(CONFIG_SYS_BOOT_RAM)
|
||||
+#define do_gpio_init 1
|
||||
+#define do_pll_init 0
|
||||
+#define do_dcdc_init 1
|
||||
+#else
|
||||
+#define do_gpio_init 0
|
||||
+#define do_pll_init 0
|
||||
+#define do_dcdc_init 1
|
||||
+#endif
|
||||
+
|
||||
+static void gpio_init(void)
|
||||
+{
|
||||
+ /* EBU.FL_CS1 as output for NAND CE */
|
||||
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
|
||||
+ /* EBU.FL_A23 as output for NAND CLE */
|
||||
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
|
||||
+ /* EBU.FL_A24 as output for NAND ALE */
|
||||
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
|
||||
+ /* GPIO 3.0 as input for NAND Ready Busy */
|
||||
+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
|
||||
+ /* GPIO 3.1 as output for NAND Read */
|
||||
+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
|
||||
+}
|
||||
+
|
||||
+int board_early_init_f(void)
|
||||
+{
|
||||
+ if (do_gpio_init)
|
||||
+ gpio_init();
|
||||
+
|
||||
+ if (do_pll_init)
|
||||
+ ltq_pll_init();
|
||||
+
|
||||
+ if (do_dcdc_init)
|
||||
+ ltq_dcdc_init(0x7F);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int checkboard(void)
|
||||
+{
|
||||
+ puts("Board: " CONFIG_BOARD_NAME "\n");
|
||||
+ ltq_chip_print_info();
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct ltq_eth_port_config eth_port_config[] = {
|
||||
+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
|
||||
+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
|
||||
+ /* GMAC1: unused */
|
||||
+ { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
|
||||
+ /* GMAC2: internal GPHY0 with 10/100 firmware for LAN port 1 */
|
||||
+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
|
||||
+ /* GMAC3: internal GPHY0 with 10/100 firmware for LAN port 2 */
|
||||
+ { 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
|
||||
+ /* GMAC4: internal GPHY1 with 10/100 firmware for LAN port 3 */
|
||||
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
|
||||
+ /* GMAC5: internal GPHY1 with 10/100 firmware for LAN port 4 */
|
||||
+ { 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
|
||||
+};
|
||||
+
|
||||
+static const struct ltq_eth_board_config eth_board_config = {
|
||||
+ .ports = eth_port_config,
|
||||
+ .num_ports = ARRAY_SIZE(eth_port_config),
|
||||
+};
|
||||
+
|
||||
+int board_eth_init(bd_t * bis)
|
||||
+{
|
||||
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
|
||||
+ const ulong fw_addr = 0x80FF0000;
|
||||
+
|
||||
+ ltq_gphy_phy22f_a2x_load(fw_addr);
|
||||
+
|
||||
+ ltq_cgu_gphy_clk_src(clk);
|
||||
+
|
||||
+ ltq_rcu_gphy_boot(0, fw_addr);
|
||||
+ ltq_rcu_gphy_boot(1, fw_addr);
|
||||
+
|
||||
+ return ltq_eth_initialize(ð_board_config);
|
||||
+}
|
||||
--- a/boards.cfg
|
||||
+++ b/boards.cfg
|
||||
@@ -527,6 +527,9 @@ Active mips mips32 vrx20
|
||||
Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
+Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_nandspl zxhnh367n:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_ram zxhnh367n:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_zte zxhnh367n:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
|
||||
Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
|
||||
Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
|
||||
--- /dev/null
|
||||
+++ b/include/configs/zxhnh367n.h
|
||||
@@ -0,0 +1,72 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#ifndef __CONFIG_H
|
||||
+#define __CONFIG_H
|
||||
+
|
||||
+#define CONFIG_MACH_TYPE "ZXHN H367N"
|
||||
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
|
||||
+#define CONFIG_BOARD_NAME "ZTE ZXHN H367N"
|
||||
+
|
||||
+/* Configure SoC */
|
||||
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a NAND flash */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
|
||||
+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
|
||||
+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
|
||||
+
|
||||
+#define CONFIG_SYS_NAND_PAGE_COUNT 128
|
||||
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
|
||||
+#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
|
||||
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000
|
||||
+
|
||||
+#define CONFIG_SYS_DRAM_PROBE
|
||||
+
|
||||
+/* Environment */
|
||||
+#if defined(CONFIG_SYS_BOOT_NANDSPL)
|
||||
+#define CONFIG_ENV_IS_IN_NAND
|
||||
+#define CONFIG_ENV_OVERWRITE
|
||||
+#define CONFIG_ENV_OFFSET (256 * 1024)
|
||||
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
+#else
|
||||
+#define CONFIG_ENV_IS_NOWHERE
|
||||
+#endif
|
||||
+
|
||||
+#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
|
||||
+
|
||||
+#if defined(CONFIG_SYS_BOOT_ZTE)
|
||||
+#define CONFIG_SYS_TEXT_BASE 0x80800000
|
||||
+#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
+#endif
|
||||
+
|
||||
+/* Console */
|
||||
+#define CONFIG_LTQ_ADVANCED_CONSOLE
|
||||
+#define CONFIG_BAUDRATE 115200
|
||||
+#define CONFIG_CONSOLE_ASC 1
|
||||
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
|
||||
+
|
||||
+/* Pull in default board configs for Lantiq XWAY VRX200 */
|
||||
+#include <asm/lantiq/config.h>
|
||||
+#include <asm/arch/config.h>
|
||||
+
|
||||
+/* Pull in default OpenWrt configs for Lantiq SoC */
|
||||
+#include "openwrt-lantiq-common.h"
|
||||
+
|
||||
+#define CONFIG_ENV_UPDATE_UBOOT_NAND \
|
||||
+ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
|
||||
+
|
||||
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
+ CONFIG_ENV_LANTIQ_DEFAULTS \
|
||||
+ CONFIG_ENV_UPDATE_UBOOT_NAND
|
||||
+
|
||||
+#endif /* __CONFIG_H */
|
||||
|
|
@ -1,251 +0,0 @@
|
|||
From 2473526cf879ead429c6aa1fb7fb77ed3407baaa Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
Date: Sun, 9 Dec 2012 17:35:09 +0100
|
||||
Subject: MIPS: add board support for ZTE ZXV10 H201L
|
||||
|
||||
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
|
||||
--- /dev/null
|
||||
+++ b/board/zte/zxv10h201l/Makefile
|
||||
@@ -0,0 +1,27 @@
|
||||
+#
|
||||
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+include $(TOPDIR)/config.mk
|
||||
+
|
||||
+LIB = $(obj)lib$(BOARD).o
|
||||
+
|
||||
+COBJS = $(BOARD).o
|
||||
+
|
||||
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
+OBJS := $(addprefix $(obj),$(COBJS))
|
||||
+SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
+
|
||||
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
+
|
||||
+#########################################################################
|
||||
+
|
||||
+# defines $(obj).depend target
|
||||
+include $(SRCTREE)/rules.mk
|
||||
+
|
||||
+sinclude $(obj).depend
|
||||
+
|
||||
+#########################################################################
|
||||
--- /dev/null
|
||||
+++ b/board/zte/zxv10h201l/config.mk
|
||||
@@ -0,0 +1,7 @@
|
||||
+#
|
||||
+# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
|
||||
--- /dev/null
|
||||
+++ b/board/zte/zxv10h201l/ddr_settings.h
|
||||
@@ -0,0 +1,55 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+ *
|
||||
+ * The values have been extracted from original ZTE U-Boot.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#define MC_DC00_VALUE 0x1B1B
|
||||
+#define MC_DC01_VALUE 0x0
|
||||
+#define MC_DC02_VALUE 0x0
|
||||
+#define MC_DC03_VALUE 0x0
|
||||
+#define MC_DC04_VALUE 0x0
|
||||
+#define MC_DC05_VALUE 0x200
|
||||
+#define MC_DC06_VALUE 0x307
|
||||
+#define MC_DC07_VALUE 0x303
|
||||
+#define MC_DC08_VALUE 0x103
|
||||
+#define MC_DC09_VALUE 0x80B
|
||||
+#define MC_DC10_VALUE 0x203
|
||||
+#define MC_DC11_VALUE 0xE02
|
||||
+#define MC_DC12_VALUE 0x2C8
|
||||
+#define MC_DC13_VALUE 0x1
|
||||
+#define MC_DC14_VALUE 0x0
|
||||
+#define MC_DC15_VALUE 0x100
|
||||
+#define MC_DC16_VALUE 0xC800
|
||||
+#define MC_DC17_VALUE 0xF
|
||||
+#define MC_DC18_VALUE 0x301
|
||||
+#define MC_DC19_VALUE 0x200
|
||||
+#define MC_DC20_VALUE 0xA04
|
||||
+#define MC_DC21_VALUE 0x1600
|
||||
+#define MC_DC22_VALUE 0x1616
|
||||
+#define MC_DC23_VALUE 0x0
|
||||
+#define MC_DC24_VALUE 0x5D
|
||||
+#define MC_DC25_VALUE 0x0
|
||||
+#define MC_DC26_VALUE 0x0
|
||||
+#define MC_DC27_VALUE 0x0
|
||||
+#define MC_DC28_VALUE 0x5FB
|
||||
+#define MC_DC29_VALUE 0x35DF
|
||||
+#define MC_DC30_VALUE 0x99E9
|
||||
+#define MC_DC31_VALUE 0x0
|
||||
+#define MC_DC32_VALUE 0x0
|
||||
+#define MC_DC33_VALUE 0x0
|
||||
+#define MC_DC34_VALUE 0x0
|
||||
+#define MC_DC35_VALUE 0x0
|
||||
+#define MC_DC36_VALUE 0x0
|
||||
+#define MC_DC37_VALUE 0x0
|
||||
+#define MC_DC38_VALUE 0x0
|
||||
+#define MC_DC39_VALUE 0x0
|
||||
+#define MC_DC40_VALUE 0x0
|
||||
+#define MC_DC41_VALUE 0x0
|
||||
+#define MC_DC42_VALUE 0x0
|
||||
+#define MC_DC43_VALUE 0x0
|
||||
+#define MC_DC44_VALUE 0x0
|
||||
+#define MC_DC45_VALUE 0x600
|
||||
+#define MC_DC46_VALUE 0x0
|
||||
--- /dev/null
|
||||
+++ b/board/zte/zxv10h201l/zxv10h201l.c
|
||||
@@ -0,0 +1,51 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <switch.h>
|
||||
+#include <asm/gpio.h>
|
||||
+#include <asm/lantiq/eth.h>
|
||||
+#include <asm/lantiq/reset.h>
|
||||
+#include <asm/lantiq/chipid.h>
|
||||
+
|
||||
+int board_early_init_f(void)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int checkboard(void)
|
||||
+{
|
||||
+ puts("Board: " CONFIG_BOARD_NAME "\n");
|
||||
+ ltq_chip_print_info();
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct ltq_eth_port_config eth_port_config[] = {
|
||||
+ /* MAC0: REALTEK RTL8306 switch */
|
||||
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
|
||||
+};
|
||||
+
|
||||
+static const struct ltq_eth_board_config eth_board_config = {
|
||||
+ .ports = eth_port_config,
|
||||
+ .num_ports = ARRAY_SIZE(eth_port_config),
|
||||
+};
|
||||
+
|
||||
+int board_eth_init(bd_t *bis)
|
||||
+{
|
||||
+ return ltq_eth_initialize(ð_board_config);
|
||||
+}
|
||||
+
|
||||
+static struct switch_device rtl8306_dev = {
|
||||
+ .name = "rtl8306",
|
||||
+ .cpu_port = 5,
|
||||
+ .port_mask = 0xF,
|
||||
+};
|
||||
+
|
||||
+int board_switch_init(void)
|
||||
+{
|
||||
+ return switch_device_register(&rtl8306_dev);
|
||||
+}
|
||||
--- a/boards.cfg
|
||||
+++ b/boards.cfg
|
||||
@@ -496,6 +496,9 @@ Active mips mips32 -
|
||||
Active mips mips32 - micronas vct vct_premium_onenand vct:VCT_PREMIUM,VCT_ONENAND -
|
||||
Active mips mips32 - micronas vct vct_premium_onenand_small vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE -
|
||||
Active mips mips32 - micronas vct vct_premium_small vct:VCT_PREMIUM,VCT_SMALL_IMAGE -
|
||||
+Active mips mips32 arx100 zte zxv10h201l zxv10h201l_nor zxv10h201l:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 arx100 zte zxv10h201l zxv10h201l_ram zxv10h201l:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 arx100 zte zxv10h201l zxv10h201l_zte zxv10h201l:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se>
|
||||
Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se>
|
||||
Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se>
|
||||
--- /dev/null
|
||||
+++ b/include/configs/zxv10h201l.h
|
||||
@@ -0,0 +1,77 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#ifndef __CONFIG_H
|
||||
+#define __CONFIG_H
|
||||
+
|
||||
+#define CONFIG_MACH_TYPE "ZXV10 H201L"
|
||||
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
|
||||
+#define CONFIG_BOARD_NAME "ZTE ZXV10 H201L"
|
||||
+
|
||||
+/* Configure SoC */
|
||||
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
|
||||
+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
|
||||
+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
|
||||
+
|
||||
+/* Switch devices */
|
||||
+#define CONFIG_SWITCH_MULTI
|
||||
+#define CONFIG_SWITCH_RTL8306
|
||||
+
|
||||
+/* Environment */
|
||||
+#if defined(CONFIG_SYS_BOOT_NOR)
|
||||
+#define CONFIG_ENV_IS_IN_FLASH
|
||||
+#define CONFIG_ENV_OVERWRITE
|
||||
+#define CONFIG_ENV_OFFSET (256 * 1024)
|
||||
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
+#elif defined(CONFIG_SYS_BOOT_NORSPL)
|
||||
+#define CONFIG_ENV_IS_IN_FLASH
|
||||
+#define CONFIG_ENV_OVERWRITE
|
||||
+#define CONFIG_ENV_OFFSET (128 * 1024)
|
||||
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
+#else
|
||||
+#define CONFIG_ENV_IS_NOWHERE
|
||||
+#endif
|
||||
+
|
||||
+#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
|
||||
+
|
||||
+#if defined(CONFIG_SYS_BOOT_ZTE)
|
||||
+#define CONFIG_SYS_TEXT_BASE 0x80800000
|
||||
+#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
+#endif
|
||||
+
|
||||
+/* Console */
|
||||
+#define CONFIG_LTQ_ADVANCED_CONSOLE
|
||||
+#define CONFIG_BAUDRATE 115200
|
||||
+#define CONFIG_CONSOLE_ASC 1
|
||||
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
|
||||
+
|
||||
+/* Pull in default board configs for Lantiq XWAY Danube */
|
||||
+#include <asm/lantiq/config.h>
|
||||
+#include <asm/arch/config.h>
|
||||
+
|
||||
+#if defined(CONFIG_SYS_BOOT_ZTE)
|
||||
+#define CONFIG_SYS_TEXT_BASE 0x80800000
|
||||
+#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
+#endif
|
||||
+
|
||||
+/* Pull in default OpenWrt configs for Lantiq SoC */
|
||||
+#include "openwrt-lantiq-common.h"
|
||||
+
|
||||
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
|
||||
+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
|
||||
+
|
||||
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
+ CONFIG_ENV_LANTIQ_DEFAULTS \
|
||||
+ CONFIG_ENV_UPDATE_UBOOT_NOR
|
||||
+
|
||||
+#endif /* __CONFIG_H */
|
||||
|
|
@ -1,304 +0,0 @@
|
|||
From a18f994f373db4467a4680f83ead997c8122908e Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
Date: Wed, 22 May 2013 17:48:08 +0200
|
||||
Subject: MIPS: add board support for ZyXEL P-661HNU-Fx
|
||||
|
||||
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
|
||||
--- /dev/null
|
||||
+++ b/board/zyxel/p661hnufx/Makefile
|
||||
@@ -0,0 +1,27 @@
|
||||
+#
|
||||
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+include $(TOPDIR)/config.mk
|
||||
+
|
||||
+LIB = $(obj)lib$(BOARD).o
|
||||
+
|
||||
+COBJS = $(BOARD).o
|
||||
+
|
||||
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
+OBJS := $(addprefix $(obj),$(COBJS))
|
||||
+SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
+
|
||||
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
+
|
||||
+#########################################################################
|
||||
+
|
||||
+# defines $(obj).depend target
|
||||
+include $(SRCTREE)/rules.mk
|
||||
+
|
||||
+sinclude $(obj).depend
|
||||
+
|
||||
+#########################################################################
|
||||
--- /dev/null
|
||||
+++ b/board/zyxel/p661hnufx/config.mk
|
||||
@@ -0,0 +1,7 @@
|
||||
+#
|
||||
+# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
|
||||
--- /dev/null
|
||||
+++ b/board/zyxel/p661hnufx/ddr_settings.h
|
||||
@@ -0,0 +1,55 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+ *
|
||||
+ * The values have been extracted from original ZyXEL U-Boot.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#define MC_DC00_VALUE 0x1B1B
|
||||
+#define MC_DC01_VALUE 0x0
|
||||
+#define MC_DC02_VALUE 0x0
|
||||
+#define MC_DC03_VALUE 0x0
|
||||
+#define MC_DC04_VALUE 0x0
|
||||
+#define MC_DC05_VALUE 0x200
|
||||
+#define MC_DC06_VALUE 0x307
|
||||
+#define MC_DC07_VALUE 0x303
|
||||
+#define MC_DC08_VALUE 0x103
|
||||
+#define MC_DC09_VALUE 0x80B
|
||||
+#define MC_DC10_VALUE 0x203
|
||||
+#define MC_DC11_VALUE 0xE02
|
||||
+#define MC_DC12_VALUE 0x2C8
|
||||
+#define MC_DC13_VALUE 0x1
|
||||
+#define MC_DC14_VALUE 0x0
|
||||
+#define MC_DC15_VALUE 0x100
|
||||
+#define MC_DC16_VALUE 0xC800
|
||||
+#define MC_DC17_VALUE 0xF
|
||||
+#define MC_DC18_VALUE 0x301
|
||||
+#define MC_DC19_VALUE 0x200
|
||||
+#define MC_DC20_VALUE 0xA04
|
||||
+#define MC_DC21_VALUE 0x1600
|
||||
+#define MC_DC22_VALUE 0x1616
|
||||
+#define MC_DC23_VALUE 0x0
|
||||
+#define MC_DC24_VALUE 0x5D
|
||||
+#define MC_DC25_VALUE 0x0
|
||||
+#define MC_DC26_VALUE 0x0
|
||||
+#define MC_DC27_VALUE 0x0
|
||||
+#define MC_DC28_VALUE 0x5FB
|
||||
+#define MC_DC29_VALUE 0x35DF
|
||||
+#define MC_DC30_VALUE 0x99E9
|
||||
+#define MC_DC31_VALUE 0x0
|
||||
+#define MC_DC32_VALUE 0x0
|
||||
+#define MC_DC33_VALUE 0x0
|
||||
+#define MC_DC34_VALUE 0x0
|
||||
+#define MC_DC35_VALUE 0x0
|
||||
+#define MC_DC36_VALUE 0x0
|
||||
+#define MC_DC37_VALUE 0x0
|
||||
+#define MC_DC38_VALUE 0x0
|
||||
+#define MC_DC39_VALUE 0x0
|
||||
+#define MC_DC40_VALUE 0x0
|
||||
+#define MC_DC41_VALUE 0x0
|
||||
+#define MC_DC42_VALUE 0x0
|
||||
+#define MC_DC43_VALUE 0x0
|
||||
+#define MC_DC44_VALUE 0x0
|
||||
+#define MC_DC45_VALUE 0x600
|
||||
+#define MC_DC46_VALUE 0x0
|
||||
--- /dev/null
|
||||
+++ b/board/zyxel/p661hnufx/p661hnufx.c
|
||||
@@ -0,0 +1,102 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <switch.h>
|
||||
+#include <spi.h>
|
||||
+#include <asm/gpio.h>
|
||||
+#include <asm/lantiq/eth.h>
|
||||
+#include <asm/lantiq/reset.h>
|
||||
+#include <asm/lantiq/chipid.h>
|
||||
+
|
||||
+static void gpio_init(void)
|
||||
+{
|
||||
+ /* SPI CS 0.4 to serial flash */
|
||||
+ gpio_direction_output(10, 1);
|
||||
+}
|
||||
+
|
||||
+int board_early_init_f(void)
|
||||
+{
|
||||
+ gpio_init();
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int checkboard(void)
|
||||
+{
|
||||
+ puts("Board: " CONFIG_BOARD_NAME "\n");
|
||||
+ ltq_chip_print_info();
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct ltq_eth_port_config eth_port_config[] = {
|
||||
+ /* MAC0: Lantiq Tantos switch */
|
||||
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
|
||||
+ /* MAC1: unused */
|
||||
+ { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
|
||||
+};
|
||||
+
|
||||
+static const struct ltq_eth_board_config eth_board_config = {
|
||||
+ .ports = eth_port_config,
|
||||
+ .num_ports = ARRAY_SIZE(eth_port_config),
|
||||
+};
|
||||
+
|
||||
+int board_eth_init(bd_t *bis)
|
||||
+{
|
||||
+ return ltq_eth_initialize(ð_board_config);
|
||||
+}
|
||||
+
|
||||
+static struct switch_device psb697x_dev = {
|
||||
+ .name = "psb697x",
|
||||
+ .cpu_port = 5,
|
||||
+ .port_mask = 0xF,
|
||||
+};
|
||||
+
|
||||
+int board_switch_init(void)
|
||||
+{
|
||||
+ printf("%s\n", __func__);
|
||||
+
|
||||
+#if 0
|
||||
+ ltq_reset_once(LTQ_RESET_HARD, 200000);
|
||||
+ __udelay(50000);
|
||||
+#endif
|
||||
+
|
||||
+ return switch_device_register(&psb697x_dev);
|
||||
+}
|
||||
+
|
||||
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
||||
+{
|
||||
+ if (bus)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (cs == 4)
|
||||
+ return 1;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+void spi_cs_activate(struct spi_slave *slave)
|
||||
+{
|
||||
+ switch (slave->cs) {
|
||||
+ case 4:
|
||||
+ gpio_set_value(10, 0);
|
||||
+ break;
|
||||
+ default:
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+void spi_cs_deactivate(struct spi_slave *slave)
|
||||
+{
|
||||
+ switch (slave->cs) {
|
||||
+ case 4:
|
||||
+ gpio_set_value(10, 1);
|
||||
+ break;
|
||||
+ default:
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
--- a/boards.cfg
|
||||
+++ b/boards.cfg
|
||||
@@ -499,6 +499,9 @@ Active mips mips32 -
|
||||
Active mips mips32 arx100 zte zxv10h201l zxv10h201l_nor zxv10h201l:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 arx100 zte zxv10h201l zxv10h201l_ram zxv10h201l:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 arx100 zte zxv10h201l zxv10h201l_zte zxv10h201l:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 arx100 zyxel p661hnufx p661hnufx_ram p661hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 arx100 zyxel p661hnufx p661hnufx_sfspl p661hnufx:SYS_BOOT_SFSPL Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 arx100 zyxel p661hnufx p661hnufx_zyxel p661hnufx:SYS_BOOT_ZYXEL Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se>
|
||||
Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se>
|
||||
Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se>
|
||||
--- /dev/null
|
||||
+++ b/include/configs/p661hnufx.h
|
||||
@@ -0,0 +1,79 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#ifndef __CONFIG_H
|
||||
+#define __CONFIG_H
|
||||
+
|
||||
+#define CONFIG_MACH_TYPE "P-661HNU-Fx"
|
||||
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
|
||||
+#define CONFIG_BOARD_NAME "ZyXEL P-661HNU-Fx"
|
||||
+
|
||||
+/* Configure SoC */
|
||||
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
|
||||
+#define CONFIG_SPI_FLASH_MACRONIX /* Supports Macronix serial flash */
|
||||
+#define CONFIG_SPI_FLASH_4BYTE_MODE
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
|
||||
+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
|
||||
+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
|
||||
+
|
||||
+#define CONFIG_SPL_SPI_BUS 0
|
||||
+#define CONFIG_SPL_SPI_CS 4
|
||||
+#define CONFIG_SPL_SPI_MAX_HZ 25000000
|
||||
+#define CONFIG_SPL_SPI_MODE 0
|
||||
+
|
||||
+/* Switch devices */
|
||||
+#define CONFIG_SWITCH_MULTI
|
||||
+#define CONFIG_SWITCH_PSB697X
|
||||
+
|
||||
+/* Environment */
|
||||
+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
|
||||
+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
|
||||
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
|
||||
+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
|
||||
+
|
||||
+#if defined(CONFIG_SYS_BOOT_SFSPL)
|
||||
+#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
+#define CONFIG_ENV_OVERWRITE
|
||||
+#define CONFIG_ENV_OFFSET (512 * 1024)
|
||||
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
+#else
|
||||
+#define CONFIG_ENV_IS_NOWHERE
|
||||
+#endif
|
||||
+
|
||||
+#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
|
||||
+
|
||||
+#if defined(CONFIG_SYS_BOOT_ZYXEL)
|
||||
+#define CONFIG_SYS_TEXT_BASE 0x80800000
|
||||
+#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
+#endif
|
||||
+
|
||||
+/* Console */
|
||||
+#define CONFIG_LTQ_ADVANCED_CONSOLE
|
||||
+#define CONFIG_BAUDRATE 115200
|
||||
+#define CONFIG_CONSOLE_ASC 1
|
||||
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
|
||||
+
|
||||
+/* Pull in default board configs for Lantiq XWAY Danube */
|
||||
+#include <asm/lantiq/config.h>
|
||||
+#include <asm/arch/config.h>
|
||||
+
|
||||
+/* Pull in default OpenWrt configs for Lantiq SoC */
|
||||
+#include "openwrt-lantiq-common.h"
|
||||
+
|
||||
+#define CONFIG_ENV_UPDATE_UBOOT_SF \
|
||||
+ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
|
||||
+
|
||||
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
+ CONFIG_ENV_LANTIQ_DEFAULTS \
|
||||
+ CONFIG_ENV_UPDATE_UBOOT_SF
|
||||
+
|
||||
+#endif /* __CONFIG_H */
|
||||
|
|
@ -1,242 +0,0 @@
|
|||
From 4bfa74583bc938d2da41f255f22baa1845332893 Mon Sep 17 00:00:00 2001
|
||||
From: Luka Perkov <luka@openwrt.org>
|
||||
Date: Tue, 12 Mar 2013 01:42:46 +0100
|
||||
Subject: MIPS: add board support for ZyXEL P-2601HN-Fx
|
||||
|
||||
Signed-off-by: Luka Perkov <luka@openwrt.org>
|
||||
|
||||
--- /dev/null
|
||||
+++ b/board/zyxel/p2601hnfx/Makefile
|
||||
@@ -0,0 +1,27 @@
|
||||
+#
|
||||
+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+include $(TOPDIR)/config.mk
|
||||
+
|
||||
+LIB = $(obj)lib$(BOARD).o
|
||||
+
|
||||
+COBJS = $(BOARD).o
|
||||
+
|
||||
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
+OBJS := $(addprefix $(obj),$(COBJS))
|
||||
+SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
+
|
||||
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
+
|
||||
+#########################################################################
|
||||
+
|
||||
+# defines $(obj).depend target
|
||||
+include $(SRCTREE)/rules.mk
|
||||
+
|
||||
+sinclude $(obj).depend
|
||||
+
|
||||
+#########################################################################
|
||||
--- /dev/null
|
||||
+++ b/board/zyxel/p2601hnfx/config.mk
|
||||
@@ -0,0 +1,7 @@
|
||||
+#
|
||||
+# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
|
||||
--- /dev/null
|
||||
+++ b/board/zyxel/p2601hnfx/ddr_settings.h
|
||||
@@ -0,0 +1,55 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
|
||||
+ *
|
||||
+ * The values have been extracted from original ZyXEL U-Boot.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#define MC_DC00_VALUE 0x1B1B
|
||||
+#define MC_DC01_VALUE 0x0
|
||||
+#define MC_DC02_VALUE 0x0
|
||||
+#define MC_DC03_VALUE 0x0
|
||||
+#define MC_DC04_VALUE 0x0
|
||||
+#define MC_DC05_VALUE 0x200
|
||||
+#define MC_DC06_VALUE 0x306
|
||||
+#define MC_DC07_VALUE 0x303
|
||||
+#define MC_DC08_VALUE 0x102
|
||||
+#define MC_DC09_VALUE 0x70A
|
||||
+#define MC_DC10_VALUE 0x203
|
||||
+#define MC_DC11_VALUE 0xC02
|
||||
+#define MC_DC12_VALUE 0x1C8
|
||||
+#define MC_DC13_VALUE 0x1
|
||||
+#define MC_DC14_VALUE 0x0
|
||||
+#define MC_DC15_VALUE 0x144
|
||||
+#define MC_DC16_VALUE 0xC800
|
||||
+#define MC_DC17_VALUE 0xD
|
||||
+#define MC_DC18_VALUE 0x301
|
||||
+#define MC_DC19_VALUE 0x200
|
||||
+#define MC_DC20_VALUE 0xA03
|
||||
+#define MC_DC21_VALUE 0x1900
|
||||
+#define MC_DC22_VALUE 0x1919
|
||||
+#define MC_DC23_VALUE 0x0
|
||||
+#define MC_DC24_VALUE 0x66
|
||||
+#define MC_DC25_VALUE 0x0
|
||||
+#define MC_DC26_VALUE 0x0
|
||||
+#define MC_DC27_VALUE 0x0
|
||||
+#define MC_DC28_VALUE 0x50A
|
||||
+#define MC_DC29_VALUE 0x2D65
|
||||
+#define MC_DC30_VALUE 0x81B1
|
||||
+#define MC_DC31_VALUE 0x0
|
||||
+#define MC_DC32_VALUE 0x0
|
||||
+#define MC_DC33_VALUE 0x0
|
||||
+#define MC_DC34_VALUE 0x0
|
||||
+#define MC_DC35_VALUE 0x0
|
||||
+#define MC_DC36_VALUE 0x0
|
||||
+#define MC_DC37_VALUE 0x0
|
||||
+#define MC_DC38_VALUE 0x0
|
||||
+#define MC_DC39_VALUE 0x0
|
||||
+#define MC_DC40_VALUE 0x0
|
||||
+#define MC_DC41_VALUE 0x0
|
||||
+#define MC_DC42_VALUE 0x0
|
||||
+#define MC_DC43_VALUE 0x0
|
||||
+#define MC_DC44_VALUE 0x0
|
||||
+#define MC_DC45_VALUE 0x600
|
||||
+#define MC_DC46_VALUE 0x0
|
||||
--- /dev/null
|
||||
+++ b/board/zyxel/p2601hnfx/p2601hnfx.c
|
||||
@@ -0,0 +1,51 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <switch.h>
|
||||
+#include <asm/gpio.h>
|
||||
+#include <asm/lantiq/eth.h>
|
||||
+#include <asm/lantiq/reset.h>
|
||||
+#include <asm/lantiq/chipid.h>
|
||||
+
|
||||
+int board_early_init_f(void)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int checkboard(void)
|
||||
+{
|
||||
+ puts("Board: " CONFIG_BOARD_NAME "\n");
|
||||
+ ltq_chip_print_info();
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct ltq_eth_port_config eth_port_config[] = {
|
||||
+ /* MAC0: REALTEK RTL8306 switch */
|
||||
+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
|
||||
+};
|
||||
+
|
||||
+static const struct ltq_eth_board_config eth_board_config = {
|
||||
+ .ports = eth_port_config,
|
||||
+ .num_ports = ARRAY_SIZE(eth_port_config),
|
||||
+};
|
||||
+
|
||||
+int board_eth_init(bd_t *bis)
|
||||
+{
|
||||
+ return ltq_eth_initialize(ð_board_config);
|
||||
+}
|
||||
+
|
||||
+static struct switch_device rtl8306_dev = {
|
||||
+ .name = "rtl8306",
|
||||
+ .cpu_port = 5,
|
||||
+ .port_mask = 0xF,
|
||||
+};
|
||||
+
|
||||
+int board_switch_init(void)
|
||||
+{
|
||||
+ return switch_device_register(&rtl8306_dev);
|
||||
+}
|
||||
--- a/boards.cfg
|
||||
+++ b/boards.cfg
|
||||
@@ -499,6 +499,10 @@ Active mips mips32 -
|
||||
Active mips mips32 arx100 zte zxv10h201l zxv10h201l_nor zxv10h201l:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 arx100 zte zxv10h201l zxv10h201l_ram zxv10h201l:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 arx100 zte zxv10h201l zxv10h201l_zte zxv10h201l:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 arx100 zyxel p2601hnfx p2601hnfx_nor p2601hnfx:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 arx100 zyxel p2601hnfx p2601hnfx_norspl p2601hnfx:SYS_BOOT_NORSPL Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 arx100 zyxel p2601hnfx p2601hnfx_ram p2601hnfx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 arx100 zyxel p2601hnfx p2601hnfx_zyxel p2601hnfx:SYS_BOOT_ZYXEL Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 arx100 zyxel p661hnufx p661hnufx_ram p661hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 arx100 zyxel p661hnufx p661hnufx_sfspl p661hnufx:SYS_BOOT_SFSPL Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 arx100 zyxel p661hnufx p661hnufx_zyxel p661hnufx:SYS_BOOT_ZYXEL Luka Perkov <luka@openwrt.org>
|
||||
--- /dev/null
|
||||
+++ b/include/configs/p2601hnfx.h
|
||||
@@ -0,0 +1,67 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#ifndef __CONFIG_H
|
||||
+#define __CONFIG_H
|
||||
+
|
||||
+#define CONFIG_MACH_TYPE "P-2601HN-Fx"
|
||||
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
|
||||
+#define CONFIG_BOARD_NAME "ZyXEL P-2601HN-Fx"
|
||||
+
|
||||
+/* Configure SoC */
|
||||
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
|
||||
+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
|
||||
+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
|
||||
+
|
||||
+/* Environment */
|
||||
+#if defined(CONFIG_SYS_BOOT_NOR)
|
||||
+#define CONFIG_ENV_IS_IN_FLASH
|
||||
+#define CONFIG_ENV_OVERWRITE
|
||||
+#define CONFIG_ENV_OFFSET (256 * 1024)
|
||||
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
+#elif defined(CONFIG_SYS_BOOT_NORSPL)
|
||||
+#define CONFIG_ENV_IS_IN_FLASH
|
||||
+#define CONFIG_ENV_OVERWRITE
|
||||
+#define CONFIG_ENV_OFFSET (128 * 1024)
|
||||
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
+#else
|
||||
+#define CONFIG_ENV_IS_NOWHERE
|
||||
+#endif
|
||||
+
|
||||
+#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
|
||||
+
|
||||
+#if defined(CONFIG_SYS_BOOT_ZYXEL)
|
||||
+#define CONFIG_SYS_TEXT_BASE 0x80800000
|
||||
+#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
+#endif
|
||||
+
|
||||
+/* Console */
|
||||
+#define CONFIG_LTQ_ADVANCED_CONSOLE
|
||||
+#define CONFIG_BAUDRATE 115200
|
||||
+#define CONFIG_CONSOLE_ASC 1
|
||||
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
|
||||
+
|
||||
+/* Pull in default board configs for Lantiq XWAY Danube */
|
||||
+#include <asm/lantiq/config.h>
|
||||
+#include <asm/arch/config.h>
|
||||
+
|
||||
+/* Pull in default OpenWrt configs for Lantiq SoC */
|
||||
+#include "openwrt-lantiq-common.h"
|
||||
+
|
||||
+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
|
||||
+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
|
||||
+
|
||||
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
+ CONFIG_ENV_LANTIQ_DEFAULTS \
|
||||
+ CONFIG_ENV_UPDATE_UBOOT_NOR \
|
||||
+ "kernel_addr=0xB0040000\0"
|
||||
+
|
||||
+#endif /* __CONFIG_H */
|
||||
|
|
@ -220,10 +220,10 @@ Signed-off-by: Luka Perkov <luka@openwrt.org>
|
|||
+}
|
||||
--- a/boards.cfg
|
||||
+++ b/boards.cfg
|
||||
@@ -540,6 +540,8 @@ Active mips mips32 vrx20
|
||||
Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_nandspl zxhnh367n:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_ram zxhnh367n:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_zte zxhnh367n:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org>
|
||||
@@ -527,6 +527,8 @@ Active mips mips32 vrx20
|
||||
Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
+Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_nandspl p2812hnufx:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org>
|
||||
+Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_ram p2812hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
|
||||
Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
|
||||
|
|
|
|||
|
|
@ -1,277 +0,0 @@
|
|||
From 60856fa8f9866f292df740ea98752a70738eb59a Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
Date: Fri, 9 Aug 2013 18:11:07 +0200
|
||||
Subject: MIPS: add board support for Arcadyan Easybox 904
|
||||
|
||||
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
|
||||
--- /dev/null
|
||||
+++ b/board/arcadyan/easybox904/Makefile
|
||||
@@ -0,0 +1,27 @@
|
||||
+#
|
||||
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+include $(TOPDIR)/config.mk
|
||||
+
|
||||
+LIB = $(obj)lib$(BOARD).o
|
||||
+
|
||||
+COBJS = $(BOARD).o
|
||||
+
|
||||
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
+OBJS := $(addprefix $(obj),$(COBJS))
|
||||
+SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
+
|
||||
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
+
|
||||
+#########################################################################
|
||||
+
|
||||
+# defines $(obj).depend target
|
||||
+include $(SRCTREE)/rules.mk
|
||||
+
|
||||
+sinclude $(obj).depend
|
||||
+
|
||||
+#########################################################################
|
||||
--- /dev/null
|
||||
+++ b/board/arcadyan/easybox904/config.mk
|
||||
@@ -0,0 +1,7 @@
|
||||
+#
|
||||
+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+#
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
|
||||
--- /dev/null
|
||||
+++ b/board/arcadyan/easybox904/ddr_settings.h
|
||||
@@ -0,0 +1,68 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#define MC_CCR00_VALUE 0x101
|
||||
+#define MC_CCR01_VALUE 0x1000100
|
||||
+#define MC_CCR02_VALUE 0x1010000
|
||||
+#define MC_CCR03_VALUE 0x101
|
||||
+#define MC_CCR04_VALUE 0x1000000
|
||||
+#define MC_CCR05_VALUE 0x1000101
|
||||
+#define MC_CCR06_VALUE 0x1000100
|
||||
+#define MC_CCR07_VALUE 0x1010000
|
||||
+#define MC_CCR08_VALUE 0x1000101
|
||||
+#define MC_CCR09_VALUE 0x1000000
|
||||
+#define MC_CCR10_VALUE 0x2000100
|
||||
+#define MC_CCR11_VALUE 0x2000300
|
||||
+#define MC_CCR12_VALUE 0x30000
|
||||
+#define MC_CCR13_VALUE 0x202
|
||||
+#define MC_CCR14_VALUE 0x7080A0F
|
||||
+#define MC_CCR15_VALUE 0x2040F
|
||||
+#define MC_CCR16_VALUE 0x40000
|
||||
+#define MC_CCR17_VALUE 0x70102
|
||||
+#define MC_CCR18_VALUE 0x4020002
|
||||
+#define MC_CCR19_VALUE 0x30302
|
||||
+#define MC_CCR20_VALUE 0x8000700
|
||||
+#define MC_CCR21_VALUE 0x40F020A
|
||||
+#define MC_CCR22_VALUE 0x0
|
||||
+#define MC_CCR23_VALUE 0xC020000
|
||||
+#define MC_CCR24_VALUE 0x4401503
|
||||
+#define MC_CCR25_VALUE 0x0
|
||||
+#define MC_CCR26_VALUE 0x0
|
||||
+#define MC_CCR27_VALUE 0x6420000
|
||||
+#define MC_CCR28_VALUE 0x0
|
||||
+#define MC_CCR29_VALUE 0x0
|
||||
+#define MC_CCR30_VALUE 0x798
|
||||
+#define MC_CCR31_VALUE 0x0
|
||||
+#define MC_CCR32_VALUE 0x0
|
||||
+#define MC_CCR33_VALUE 0x650000
|
||||
+#define MC_CCR34_VALUE 0x200C8
|
||||
+#define MC_CCR35_VALUE 0x1536B0
|
||||
+#define MC_CCR36_VALUE 0xC8
|
||||
+#define MC_CCR37_VALUE 0xC351
|
||||
+#define MC_CCR38_VALUE 0x0
|
||||
+#define MC_CCR39_VALUE 0x142404
|
||||
+#define MC_CCR40_VALUE 0x142604
|
||||
+#define MC_CCR41_VALUE 0x141B42
|
||||
+#define MC_CCR42_VALUE 0x141B42
|
||||
+#define MC_CCR43_VALUE 0x566504
|
||||
+#define MC_CCR44_VALUE 0x566504
|
||||
+#define MC_CCR45_VALUE 0x565F17
|
||||
+#define MC_CCR46_VALUE 0x565F17
|
||||
+#define MC_CCR47_VALUE 0x0
|
||||
+#define MC_CCR48_VALUE 0x0
|
||||
+#define MC_CCR49_VALUE 0x0
|
||||
+#define MC_CCR50_VALUE 0x0
|
||||
+#define MC_CCR51_VALUE 0x0
|
||||
+#define MC_CCR52_VALUE 0x133
|
||||
+#define MC_CCR53_VALUE 0xF3014B27
|
||||
+#define MC_CCR54_VALUE 0xF3014B27
|
||||
+#define MC_CCR55_VALUE 0xF3014B27
|
||||
+#define MC_CCR56_VALUE 0xF3014B27
|
||||
+#define MC_CCR57_VALUE 0x7C00301
|
||||
+#define MC_CCR58_VALUE 0x7C00301
|
||||
+#define MC_CCR59_VALUE 0x7C00301
|
||||
+#define MC_CCR60_VALUE 0x7C00301
|
||||
+#define MC_CCR61_VALUE 0x4
|
||||
--- /dev/null
|
||||
+++ b/board/arcadyan/easybox904/easybox904.c
|
||||
@@ -0,0 +1,98 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#include <common.h>
|
||||
+#include <spi.h>
|
||||
+#include <asm/gpio.h>
|
||||
+#include <asm/lantiq/eth.h>
|
||||
+#include <asm/lantiq/chipid.h>
|
||||
+#include <asm/lantiq/cpu.h>
|
||||
+#include <asm/arch/gphy.h>
|
||||
+
|
||||
+#if defined(CONFIG_SPL_BUILD)
|
||||
+#define do_gpio_init 1
|
||||
+#define do_pll_init 1
|
||||
+#define do_dcdc_init 0
|
||||
+#elif defined(CONFIG_SYS_BOOT_RAM)
|
||||
+#define do_gpio_init 1
|
||||
+#define do_pll_init 0
|
||||
+#define do_dcdc_init 1
|
||||
+#else
|
||||
+#define do_gpio_init 0
|
||||
+#define do_pll_init 0
|
||||
+#define do_dcdc_init 1
|
||||
+#endif
|
||||
+
|
||||
+static inline void gpio_init(void)
|
||||
+{
|
||||
+ /* EBU.FL_CS1 as output for NAND CE */
|
||||
+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
|
||||
+ /* EBU.FL_A23 as output for NAND CLE */
|
||||
+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
|
||||
+ /* EBU.FL_A24 as output for NAND ALE */
|
||||
+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
|
||||
+ /* GPIO 3.0 as input for NAND Ready Busy */
|
||||
+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
|
||||
+ /* GPIO 3.1 as output for NAND Read */
|
||||
+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
|
||||
+}
|
||||
+
|
||||
+int board_early_init_f(void)
|
||||
+{
|
||||
+ if (do_gpio_init)
|
||||
+ gpio_init();
|
||||
+
|
||||
+ if (do_pll_init)
|
||||
+ ltq_pll_init();
|
||||
+
|
||||
+ if (do_dcdc_init)
|
||||
+ ltq_dcdc_init(0x7F);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int checkboard(void)
|
||||
+{
|
||||
+ puts("Board: " CONFIG_BOARD_NAME "\n");
|
||||
+ ltq_chip_print_info();
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct ltq_eth_port_config eth_port_config[] = {
|
||||
+ /* GMAC0: ??? */
|
||||
+ { 0, 0x0, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
|
||||
+ /* GMAC1: ??? */
|
||||
+ { 1, 0x1, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
|
||||
+ /* GMAC2: ??? */
|
||||
+ { 2, 0x11, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
|
||||
+ /* GMAC3: unused */
|
||||
+ { 3, 0x0, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
|
||||
+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for WANoE port */
|
||||
+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
|
||||
+ /* GMAC5: ??? */
|
||||
+ { 5, 0x5, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE },
|
||||
+};
|
||||
+
|
||||
+static const struct ltq_eth_board_config eth_board_config = {
|
||||
+ .ports = eth_port_config,
|
||||
+ .num_ports = ARRAY_SIZE(eth_port_config),
|
||||
+};
|
||||
+
|
||||
+int board_eth_init(bd_t * bis)
|
||||
+{
|
||||
+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
|
||||
+ const ulong fw_ge_addr = 0x80FE0000;
|
||||
+
|
||||
+ ltq_gphy_phy11g_a2x_load(fw_ge_addr);
|
||||
+
|
||||
+ ltq_cgu_gphy_clk_src(clk);
|
||||
+
|
||||
+ ltq_rcu_gphy_boot(0, fw_ge_addr);
|
||||
+ ltq_rcu_gphy_boot(1, fw_ge_addr);
|
||||
+
|
||||
+ return ltq_eth_initialize(ð_board_config);
|
||||
+}
|
||||
--- a/boards.cfg
|
||||
+++ b/boards.cfg
|
||||
@@ -529,6 +529,7 @@ Active mips mips32 incai
|
||||
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
|
||||
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
|
||||
Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
|
||||
+Active mips mips32 vrx200 arcadyan easybox904 easybox904_ram easybox904:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
--- /dev/null
|
||||
+++ b/include/configs/easybox904.h
|
||||
@@ -0,0 +1,45 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0+
|
||||
+ */
|
||||
+
|
||||
+#ifndef __CONFIG_H
|
||||
+#define __CONFIG_H
|
||||
+
|
||||
+#define CONFIG_MACH_TYPE "EASYBOX904"
|
||||
+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
|
||||
+#define CONFIG_BOARD_NAME "Arcadyan EasyBox 904"
|
||||
+
|
||||
+/* Configure SoC */
|
||||
+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
|
||||
+
|
||||
+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
|
||||
+
|
||||
+#define CONFIG_SYS_DRAM_PROBE
|
||||
+
|
||||
+/* Environment */
|
||||
+#define CONFIG_ENV_IS_NOWHERE
|
||||
+
|
||||
+#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
|
||||
+
|
||||
+/* Console */
|
||||
+#define CONFIG_LTQ_ADVANCED_CONSOLE
|
||||
+#define CONFIG_BAUDRATE 115200
|
||||
+#define CONFIG_CONSOLE_ASC 1
|
||||
+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
|
||||
+
|
||||
+/* Pull in default board configs for Lantiq XWAY VRX200 */
|
||||
+#include <asm/lantiq/config.h>
|
||||
+#include <asm/arch/config.h>
|
||||
+
|
||||
+/* Pull in default OpenWrt configs for Lantiq SoC */
|
||||
+#include "openwrt-lantiq-common.h"
|
||||
+
|
||||
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
+ CONFIG_ENV_LANTIQ_DEFAULTS
|
||||
+
|
||||
+#endif /* __CONFIG_H */
|
||||
|
|
@ -253,10 +253,10 @@
|
|||
+#define MC_CCR61_VALUE 0x4
|
||||
--- a/boards.cfg
|
||||
+++ b/boards.cfg
|
||||
@@ -542,6 +542,9 @@
|
||||
@@ -531,6 +531,9 @@ Active mips mips32 incai
|
||||
Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
|
||||
Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
|
||||
Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
|
||||
Active mips mips32 vrx200 arcadyan easybox904 easybox904_ram easybox904:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|
||||
+Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
+Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
+Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
|
|
|
|||
Loading…
Reference in a new issue