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fix GPIOLIB support

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SVN-Revision: 17446
This commit is contained in:
Gabor Juhos 2009-08-31 08:29:19 +00:00
parent 5af113eb7c
commit 73ef265227
8 changed files with 278 additions and 42 deletions
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44
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/gpio.h
View file

@ -1,5 +1,5 @@
/*
* Ralink RT288x GPIO API definitions
* Ralink SoC GPIO API support
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
@ -10,43 +10,15 @@
*
*/
#ifndef __ASM_MACH_RT288X_GPIO_H
#define __ASM_MACH_RT288X_GPIO_H
#ifndef __ASM_MACH_RALINK_GPIO_H
#define __ASM_MACH_RALINK_GPIO_H
#define ARCH_NR_GPIOS 64
#define ARCH_NR_GPIOS 128
#include <asm-generic/gpio.h>
#include <asm/mach-ralink/rt288x.h>
extern void __rt288x_gpio_set_value(unsigned gpio, int value);
extern int __rt288x_gpio_get_value(unsigned gpio);
static inline int gpio_to_irq(unsigned gpio)
{
return RT288X_GPIO_IRQ(gpio);
}
static inline int irq_to_gpio(unsigned irq)
{
return irq - RT288X_GPIO_IRQ_BASE;
}
static inline int gpio_get_value(unsigned gpio)
{
if (gpio < RT288X_GPIO_COUNT)
return __rt288x_gpio_get_value(gpio);
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
if (gpio < RT288X_GPIO_COUNT)
__rt288x_gpio_set_value(gpio, value);
else
__gpio_set_value(gpio, value);
}
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
#endif /* __ASM_MACH_RT288X_GPIO_H */
#endif /* __ASM_MACH_RALINK_GPIO_H */

20
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/ralink_soc.h Normal file
View file

@ -0,0 +1,20 @@
/*
* Ralink RT288x specific SOC defines
*
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __RT288X_RALINK_SOC_H
#define __RT288X_RALINK_SOC_H
#define RALINK_SOC_GPIO_BASE 0x300600
#define RALINK_SOC_GPIO0_COUNT 24
#define RALINK_SOC_GPIO1_COUNT 16
#define RALINK_SOC_GPIO2_COUNT 32
#endif /* __RT288X_RALINK_SOC_H */

1
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h
View file

@ -16,7 +16,6 @@
#define RT2880_SYSC_BASE 0x00300000
#define RT2880_TIMER_BASE 0x00300100
#define RT2880_INTC_BASE 0x00300200
#define RT2880_MEMC_BASE 0x00300300
#define RT2880_UART0_BASE 0x00300500
#define RT2880_PIO_BASE 0x00300600

20
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/ralink_soc.h Normal file
View file

@ -0,0 +1,20 @@
/*
* Ralink RT305x specific SOC defines
*
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __RT288X_RALINK_SOC_H
#define __RT288X_RALINK_SOC_H
#define RALINK_SOC_GPIO_BASE 0x10000600
#define RALINK_SOC_GPIO0_COUNT 24
#define RALINK_SOC_GPIO1_COUNT 16
#define RALINK_SOC_GPIO2_COUNT 12
#endif /* __RT288X_RALINK_SOC_H */

1
target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h
View file

@ -20,7 +20,6 @@
#define RT305X_MEMC_BASE 0x10000300
#define RT305X_PCM_BASE 0x10000400
#define RT305X_UART0_BASE 0x10000500
#define RT305X_PIO_BASE 0x10000600
#define RT305X_GDMA_BASE 0x10000700
#define RT305X_NANDC_BASE 0x10000800
#define RT305X_I2C_BASE 0x10000900

2
target/linux/ramips/files/arch/mips/ralink/common/Makefile
View file

@ -7,4 +7,4 @@
# under the terms of the GNU General Public License version 2 as published
# by the Free Software Foundation.
obj-y := intc.o
obj-y := intc.o gpio.o

224
target/linux/ramips/files/arch/mips/ralink/common/gpio.c Normal file
View file

@ -0,0 +1,224 @@
/*
* Ralink SoC specific GPIO support
*
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <ralink_soc.h>
#define GPIO0_REG_INT 0x00
#define GPIO0_REG_EDGE 0x04
#define GPIO0_REG_RENA 0x08
#define GPIO0_REG_FENA 0x0c
#define GPIO0_REG_DATA 0x20
#define GPIO0_REG_DIR 0x24
#define GPIO0_REG_POL 0x28
#define GPIO0_REG_SET 0x2c
#define GPIO0_REG_RESET 0x30
#define GPIO0_REG_TOGGLE 0x34
#define GPIO1_REG_INT 0x38
#define GPIO1_REG_EDGE 0x3c
#define GPIO1_REG_RENA 0x40
#define GPIO1_REG_FENA 0x44
#define GPIO1_REG_DATA 0x48
#define GPIO1_REG_DIR 0x4c
#define GPIO1_REG_POL 0x50
#define GPIO1_REG_SET 0x54
#define GPIO1_REG_RESET 0x58
#define GPIO1_REG_TOGGLE 0x5c
#define GPIO2_REG_INT 0x60
#define GPIO2_REG_EDGE 0x64
#define GPIO2_REG_RENA 0x68
#define GPIO2_REG_FENA 0x6c
#define GPIO2_REG_DATA 0x70
#define GPIO2_REG_DIR 0x74
#define GPIO2_REG_POL 0x78
#define GPIO2_REG_SET 0x7c
#define GPIO2_REG_RESET 0x80
#define GPIO2_REG_TOGGLE 0x84
enum ramips_pio_reg {
RAMIPS_GPIO_REG_INT, /* Interrupt status */
RAMIPS_GPIO_REG_EDGE,
RAMIPS_GPIO_REG_RENA,
RAMIPS_GPIO_REG_DATA,
RAMIPS_GPIO_REG_DIR, /* Direction, 0:in, 1: out */
RAMIPS_GPIO_REG_POL, /* Polarity, 0: normal, 1: invert */
RAMIPS_GPIO_REG_SET,
RAMIPS_GPIO_REG_RESET,
RAMIPS_GPIO_REG_TOGGLE,
RAMIPS_GPIO_REG_MAX
};
struct ramips_gpio_chip {
struct gpio_chip chip;
u8 regs[RAMIPS_GPIO_REG_MAX];
};
static void __iomem *ramips_gpio_base;
static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip)
{
struct ramips_gpio_chip *rg;
rg = container_of(chip, struct ramips_gpio_chip, chip);
return rg;
}
static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val)
{
__raw_writel(val, ramips_gpio_base + rg->regs[reg]);
}
static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg)
{
return __raw_readl(ramips_gpio_base + rg->regs[reg]);
}
static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
u32 t;
t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
t &= ~(1 << offset);
ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
return 0;
}
static int ramips_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
u32 reg;
u32 t;
reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
ramips_gpio_wr(rg, reg, 1 << offset);
t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
t |= 1 << offset;
ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
return 0;
}
static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
u32 reg;
reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
ramips_gpio_wr(rg, reg, 1 << offset);
}
static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
u32 t;
t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA);
return (t & (1 << offset));
}
static struct ramips_gpio_chip ramips_gpio_chip0 = {
.chip = {
.label = "ramips-gpio0",
.direction_input = ramips_gpio_direction_input,
.direction_output = ramips_gpio_direction_output,
.get = ramips_gpio_get,
.set = ramips_gpio_set,
.base = 0,
.ngpio = RALINK_SOC_GPIO0_COUNT,
},
.regs = {
[RAMIPS_GPIO_REG_INT] = GPIO0_REG_INT,
[RAMIPS_GPIO_REG_EDGE] = GPIO0_REG_EDGE,
[RAMIPS_GPIO_REG_RENA] = GPIO0_REG_RENA,
[RAMIPS_GPIO_REG_DATA] = GPIO0_REG_DATA,
[RAMIPS_GPIO_REG_DIR] = GPIO0_REG_DIR,
[RAMIPS_GPIO_REG_POL] = GPIO0_REG_POL,
[RAMIPS_GPIO_REG_SET] = GPIO0_REG_SET,
[RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET,
[RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE,
},
};
static struct ramips_gpio_chip ramips_gpio_chip1 = {
.chip = {
.label = "ramips-gpio1",
.direction_input = ramips_gpio_direction_input,
.direction_output = ramips_gpio_direction_output,
.get = ramips_gpio_get,
.set = ramips_gpio_set,
.base = 32,
.ngpio = RALINK_SOC_GPIO1_COUNT,
},
.regs = {
[RAMIPS_GPIO_REG_INT] = GPIO1_REG_INT,
[RAMIPS_GPIO_REG_EDGE] = GPIO1_REG_EDGE,
[RAMIPS_GPIO_REG_RENA] = GPIO1_REG_RENA,
[RAMIPS_GPIO_REG_DATA] = GPIO1_REG_DATA,
[RAMIPS_GPIO_REG_DIR] = GPIO1_REG_DIR,
[RAMIPS_GPIO_REG_POL] = GPIO1_REG_POL,
[RAMIPS_GPIO_REG_SET] = GPIO1_REG_SET,
[RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET,
[RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE,
},
};
static struct ramips_gpio_chip ramips_gpio_chip2 = {
.chip = {
.label = "ramips-gpio2",
.direction_input = ramips_gpio_direction_input,
.direction_output = ramips_gpio_direction_output,
.get = ramips_gpio_get,
.set = ramips_gpio_set,
.base = 64,
.ngpio = RALINK_SOC_GPIO2_COUNT,
},
.regs = {
[RAMIPS_GPIO_REG_INT] = GPIO2_REG_INT,
[RAMIPS_GPIO_REG_EDGE] = GPIO2_REG_EDGE,
[RAMIPS_GPIO_REG_RENA] = GPIO2_REG_RENA,
[RAMIPS_GPIO_REG_DATA] = GPIO2_REG_DATA,
[RAMIPS_GPIO_REG_DIR] = GPIO2_REG_DIR,
[RAMIPS_GPIO_REG_POL] = GPIO2_REG_POL,
[RAMIPS_GPIO_REG_SET] = GPIO2_REG_SET,
[RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET,
[RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE,
},
};
static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg)
{
/* set priority to low for all lines */
ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0);
gpiochip_add(&rg->chip);
}
__init int ramips_gpio_init(void)
{
ramips_gpio_base = ioremap_nocache(RALINK_SOC_GPIO_BASE, PAGE_SIZE);
ramips_gpio_chip_add(&ramips_gpio_chip0);
ramips_gpio_chip_add(&ramips_gpio_chip1);
ramips_gpio_chip_add(&ramips_gpio_chip2);
return 0;
}
arch_initcall(ramips_gpio_init);

8
target/linux/ramips/patches-2.6.30/100-mips-ralink-core.patch
View file

@ -1,6 +1,6 @@
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -603,6 +603,24 @@ else
@@ -603,6 +603,26 @@
load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
endif
@ -14,12 +14,14 @@
+# Ralink RT288x
+#
+core-$(CONFIG_RALINK_RT288X) += arch/mips/ralink/rt288x/
+cflags-$(CONFIG_RALINK_RT288X) += -I$(srctree)//arch/mips/include/asm/mach-ralink/rt305x
+load-$(CONFIG_RALINK_RT288X) += 0xffffffff88000000
+
+#
+# Ralink RT305x
+#
+core-$(CONFIG_RALINK_RT305X) += arch/mips/ralink/rt305x/
+cflags-$(CONFIG_RALINK_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
+load-$(CONFIG_RALINK_RT305X) += 0xffffffff80000000
+
# temporary until string.h is fixed
@ -27,7 +29,7 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -22,6 +22,9 @@ choice
@@ -22,6 +22,9 @@
config MACH_ALCHEMY
bool "Alchemy processor based machines"
@ -37,7 +39,7 @@
config BASLER_EXCITE
bool "Basler eXcite smart camera"
select CEVT_R4K
@@ -638,6 +641,7 @@ source "arch/mips/basler/excite/Kconfig"
@@ -638,6 +641,7 @@
source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"