ralink: fix rcu_sched stalls on mt7621
there were 2 bugs *) core1 came up with a bad bogo mips, looks like the clock needed time to stabilize *) HPT frequency was not set making r4k timers not come up properly Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
parent
77645ffcd9
commit
6acb53c526
2 changed files with 132 additions and 0 deletions
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@ -42,6 +42,8 @@
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clock-frequency = <50000000>;
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clock-frequency = <50000000>;
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};
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};
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palmbus: palmbus@1E000000 {
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palmbus: palmbus@1E000000 {
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compatible = "palmbus";
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compatible = "palmbus";
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reg = <0x1E000000 0x100000>;
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reg = <0x1E000000 0x100000>;
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@ -129,6 +131,17 @@
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status = "disabled";
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status = "disabled";
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};
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};
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systick: systick@d00 {
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compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
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reg = <0xd00 0x10>;
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resets = <&rstctrl 28>;
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reset-names = "intc";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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memc: memc@5000 {
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memc: memc@5000 {
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compatible = "mtk,mt7621-memc";
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compatible = "mtk,mt7621-memc";
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reg = <0x300 0x100>;
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reg = <0x300 0x100>;
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119
target/linux/ramips/patches-4.9/101-mt7621-timer.patch
Normal file
119
target/linux/ramips/patches-4.9/101-mt7621-timer.patch
Normal file
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@ -0,0 +1,119 @@
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Index: linux-4.9.37/arch/mips/kernel/smp-cmp.c
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===================================================================
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--- linux-4.9.37.orig/arch/mips/kernel/smp-cmp.c
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+++ linux-4.9.37/arch/mips/kernel/smp-cmp.c
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@@ -43,6 +43,10 @@ static void cmp_init_secondary(void)
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{
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struct cpuinfo_mips *c __maybe_unused = ¤t_cpu_data;
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+ printk("%s:%s[%d]%x\n", __FILE__, __func__, __LINE__, c->core);
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+ c->core = (read_c0_ebase() & 0x3ff) >> (fls(smp_num_siblings)-1);
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+ printk("%s:%s[%d]%x\n", __FILE__, __func__, __LINE__, c->core);
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+
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/* Assume GIC is present */
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change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
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STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
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Index: linux-4.9.37/arch/mips/ralink/mt7621.c
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===================================================================
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--- linux-4.9.37.orig/arch/mips/ralink/mt7621.c
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+++ linux-4.9.37/arch/mips/ralink/mt7621.c
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@@ -18,6 +18,7 @@
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7621.h>
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#include <asm/mips-boards/launch.h>
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+#include <asm/delay.h>
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#include <pinmux.h>
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@@ -179,6 +180,58 @@ bool plat_cpu_core_present(int core)
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return true;
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}
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+#define LPS_PREC 8
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+/*
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+* Re-calibration lpj(loop-per-jiffy).
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+* (derived from kernel/calibrate.c)
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+*/
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+static int udelay_recal(void)
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+{
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+ unsigned int i, lpj = 0;
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+ unsigned long ticks, loopbit;
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+ int lps_precision = LPS_PREC;
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+
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+ lpj = (1<<12);
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+
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+ while ((lpj <<= 1) != 0) {
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+ /* wait for "start of" clock tick */
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+ ticks = jiffies;
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+ while (ticks == jiffies)
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+ /* nothing */;
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+
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+ /* Go .. */
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+ ticks = jiffies;
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+ __delay(lpj);
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+ ticks = jiffies - ticks;
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+ if (ticks)
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+ break;
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+ }
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+
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+ /*
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+ * Do a binary approximation to get lpj set to
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+ * equal one clock (up to lps_precision bits)
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+ */
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+ lpj >>= 1;
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+ loopbit = lpj;
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+ while (lps_precision-- && (loopbit >>= 1)) {
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+ lpj |= loopbit;
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+ ticks = jiffies;
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+ while (ticks == jiffies)
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+ /* nothing */;
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+ ticks = jiffies;
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+ __delay(lpj);
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+ if (jiffies != ticks) /* longer than 1 tick */
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+ lpj &= ~loopbit;
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+ }
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+ printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
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+
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+ for(i=0; i< NR_CPUS; i++)
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+ cpu_data[i].udelay_val = lpj;
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+
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+ return 0;
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+}
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+device_initcall(udelay_recal);
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+
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void prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
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Index: linux-4.9.37/arch/mips/ralink/Kconfig
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===================================================================
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--- linux-4.9.37.orig/arch/mips/ralink/Kconfig
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+++ linux-4.9.37/arch/mips/ralink/Kconfig
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@@ -56,6 +56,7 @@ choice
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select COMMON_CLK
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select CLKSRC_MIPS_GIC
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select HW_HAS_PCI
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+ select GENERIC_CLOCKEVENTS_BROADCAST
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endchoice
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choice
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Index: linux-4.9.37/arch/mips/ralink/timer-gic.c
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===================================================================
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--- linux-4.9.37.orig/arch/mips/ralink/timer-gic.c
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+++ linux-4.9.37/arch/mips/ralink/timer-gic.c
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@@ -12,6 +12,7 @@
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#include <linux/of.h>
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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+#include <asm/time.h>
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#include "common.h"
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@@ -19,6 +20,8 @@ void __init plat_time_init(void)
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{
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ralink_of_remap();
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+ mips_hpt_frequency = 880000000 / 2;
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+
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of_clk_init(NULL);
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clocksource_probe();
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}
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