ar71xx: refresh patches
Signed-off-by: Roman Yeryomin <roman@advem.lv> SVN-Revision: 47983
This commit is contained in:
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502f91b22e
commit
698edbbc32
7 changed files with 19 additions and 19 deletions
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@ -236,7 +236,7 @@
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static bool __init
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static bool __init
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ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
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ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
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{
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{
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@@ -392,6 +410,8 @@ void __init ath79_register_wmac(u8 *cal_
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@@ -392,6 +412,8 @@ void __init ath79_register_wmac(u8 *cal_
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qca953x_wmac_setup();
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qca953x_wmac_setup();
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else if (soc_is_qca955x())
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else if (soc_is_qca955x())
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qca955x_wmac_setup();
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qca955x_wmac_setup();
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@ -9,7 +9,7 @@
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static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
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static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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{
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@@ -149,8 +151,7 @@ static void ar934x_ip2_irq_init(void)
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@@ -150,8 +152,7 @@ static void ar934x_ip2_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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@ -19,7 +19,7 @@
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irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
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}
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}
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@@ -182,7 +183,7 @@ static void qca953x_irq_init(void)
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@@ -183,7 +184,7 @@ static void qca953x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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@ -28,7 +28,7 @@
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
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}
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}
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@@ -256,15 +257,13 @@ static void qca955x_irq_init(void)
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@@ -257,15 +258,13 @@ static void qca955x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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@ -46,7 +46,7 @@
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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}
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}
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@@ -345,13 +344,13 @@ static void qca956x_irq_init(void)
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@@ -346,13 +345,13 @@ static void qca956x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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@ -62,7 +62,7 @@
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
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@@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void)
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@@ -467,8 +466,35 @@ static void qca953x_ip3_handler(void)
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do_IRQ(ATH79_CPU_IRQ(3));
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do_IRQ(ATH79_CPU_IRQ(3));
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}
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}
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@ -1,6 +1,6 @@
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--- a/arch/mips/ath79/dev-wmac.c
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -398,6 +398,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
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@@ -400,6 +400,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
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ar934x_set_ext_lna_gpio(chain, gpio);
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ar934x_set_ext_lna_gpio(chain, gpio);
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}
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}
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@ -29,7 +29,7 @@
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static void __ath79_gpio_set_value(unsigned gpio, int value)
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static void __ath79_gpio_set_value(unsigned gpio, int value)
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{
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{
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void __iomem *base = ath79_gpio_base;
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void __iomem *base = ath79_gpio_base;
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@@ -233,6 +245,132 @@ void __init ath79_gpio_output_select(uns
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@@ -235,6 +247,132 @@ void __init ath79_gpio_output_select(uns
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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}
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}
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@ -162,7 +162,7 @@
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void __init ath79_gpio_init(void)
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void __init ath79_gpio_init(void)
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{
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{
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int err;
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int err;
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@@ -269,6 +407,10 @@ void __init ath79_gpio_init(void)
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@@ -271,6 +409,10 @@ void __init ath79_gpio_init(void)
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err = gpiochip_add(&ath79_gpio_chip);
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err = gpiochip_add(&ath79_gpio_chip);
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if (err)
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if (err)
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panic("cannot add AR71xx GPIO chip, error=%d", err);
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panic("cannot add AR71xx GPIO chip, error=%d", err);
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@ -173,7 +173,7 @@
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}
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}
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int gpio_get_value(unsigned gpio)
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int gpio_get_value(unsigned gpio)
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@@ -291,14 +433,22 @@ EXPORT_SYMBOL(gpio_set_value);
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@@ -293,14 +435,22 @@ EXPORT_SYMBOL(gpio_set_value);
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int gpio_to_irq(unsigned gpio)
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int gpio_to_irq(unsigned gpio)
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{
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{
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@ -1,6 +1,6 @@
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--- a/arch/mips/ath79/gpio.c
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--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -221,15 +221,30 @@ void __init ath79_gpio_output_select(uns
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@@ -223,15 +223,30 @@ void __init ath79_gpio_output_select(uns
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{
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{
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void __iomem *base = ath79_gpio_base;
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void __iomem *base = ath79_gpio_base;
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unsigned long flags;
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unsigned long flags;
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@ -37,7 +37,7 @@
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -868,6 +868,14 @@
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@@ -875,6 +875,14 @@
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#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
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#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
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#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
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#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
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@ -52,7 +52,7 @@
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#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
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#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
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#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
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#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
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#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
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#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
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@@ -1007,6 +1015,8 @@
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@@ -1014,6 +1022,8 @@
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#define AR934X_GPIO_OUT_EXT_LNA0 46
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#define AR934X_GPIO_OUT_EXT_LNA0 46
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#define AR934X_GPIO_OUT_EXT_LNA1 47
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#define AR934X_GPIO_OUT_EXT_LNA1 47
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@ -1,7 +1,7 @@
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -1098,5 +1098,11 @@
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@@ -1105,5 +1105,11 @@
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#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
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#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
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#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
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#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
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+#define QCA955X_ETH_CFG_RXD_DELAY BIT(14)
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+#define QCA955X_ETH_CFG_RXD_DELAY BIT(14)
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@ -10,5 +10,5 @@
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+#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
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+#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
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+#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
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+#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
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+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
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+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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@ -14,7 +14,7 @@ functions on the Arduino Yun.
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void ath79_gpio_init(void);
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void ath79_gpio_init(void);
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--- a/arch/mips/ath79/gpio.c
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--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -193,6 +193,36 @@ static void __iomem *ath79_gpio_get_func
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@@ -195,6 +195,36 @@ static void __iomem *ath79_gpio_get_func
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return ath79_gpio_base + reg;
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return ath79_gpio_base + reg;
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}
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}
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@ -53,7 +53,7 @@ functions on the Arduino Yun.
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void __iomem *reg = ath79_gpio_get_function_reg();
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void __iomem *reg = ath79_gpio_get_function_reg();
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -840,6 +840,7 @@
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@@ -847,6 +847,7 @@
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#define AR71XX_GPIO_REG_INT_PENDING 0x20
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#define AR71XX_GPIO_REG_INT_PENDING 0x20
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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#define AR71XX_GPIO_REG_FUNC 0x28
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@ -61,7 +61,7 @@ functions on the Arduino Yun.
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#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
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#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
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#define AR934X_GPIO_REG_OUT_FUNC1 0x30
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#define AR934X_GPIO_REG_OUT_FUNC1 0x30
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@@ -964,6 +965,8 @@
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@@ -971,6 +972,8 @@
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#define AR724X_GPIO_FUNC_UART_EN BIT(1)
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#define AR724X_GPIO_FUNC_UART_EN BIT(1)
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#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
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#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
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