ramips: mt7621: setup memory region for pcie controller memory
Only compile tested since I do not have any hardware with devices on pcie bus. Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com> SVN-Revision: 47904
This commit is contained in:
parent
e8890c6be0
commit
622e268710
1 changed files with 42 additions and 0 deletions
|
@ -0,0 +1,42 @@
|
|||
--- a/arch/mips/pci/pci-mt7621.c
|
||||
+++ b/arch/mips/pci/pci-mt7621.c
|
||||
@@ -46,6 +46,7 @@
|
||||
#include <linux/version.h>
|
||||
#include <asm/pci.h>
|
||||
#include <asm/io.h>
|
||||
+#include <asm/mips-cm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/delay.h>
|
||||
@@ -553,6 +554,23 @@ set_phy_for_ssc(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
+void setup_cm_memory_region(struct resource *mem_resource)
|
||||
+{
|
||||
+ resource_size_t mask;
|
||||
+ if (mips_cm_numiocu()) {
|
||||
+ /* FIXME: hardware doesn't accept mask values with 1s after
|
||||
+ 0s (e.g. 0xffef), so it would be great to warn if that's
|
||||
+ about to happen */
|
||||
+ mask = ~(mem_resource->end - mem_resource->start);
|
||||
+
|
||||
+ write_gcr_reg1_base(mem_resource->start);
|
||||
+ write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
|
||||
+ printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
|
||||
+ read_gcr_reg1_base(),
|
||||
+ read_gcr_reg1_mask());
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static int mt7621_pci_probe(struct platform_device *pdev)
|
||||
{
|
||||
unsigned long val = 0;
|
||||
@@ -780,6 +798,7 @@ pcie(2/1/0) link status pcie2_num pcie1_
|
||||
}
|
||||
|
||||
pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
|
||||
+ setup_cm_memory_region(mt7621_controller.mem_resource);
|
||||
register_pci_controller(&mt7621_controller);
|
||||
return 0;
|
||||
|
Loading…
Reference in a new issue