brcm63xx: fix number of switch ports for BCM63168/63268
BCM63168 has 6 ports (3 FE PHY, 1 GE PHY, two RGMII) and BCM63268 has two additional RGMII ports, making it 8. Fix this by checking the chip variant and applying an appropriate limit. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 39677
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2 changed files with 10 additions and 6 deletions
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@ -744,11 +744,15 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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return -ENODEV;
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ret = register_shared();
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@@ -297,6 +299,8 @@ bcm63xx_enetsw_register(const struct bcm
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@@ -295,8 +297,11 @@ bcm63xx_enetsw_register(const struct bcm
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if (BCMCPU_IS_6328())
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enetsw_pd.num_ports = ENETSW_PORTS_6328;
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else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
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- else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
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+ else if (BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
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+ BCMCPU_VARIANT_IS_63168() || BCMCPU_VARIANT_IS_63169())
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enetsw_pd.num_ports = ENETSW_PORTS_6368;
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+ else if (BCMCPU_IS_63268())
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+ else if (BCMCPU_VARIANT_IS_63268() || BCMCPU_VARIANT_IS_63269())
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+ enetsw_pd.num_ports = ENETSW_PORTS_63268;
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enetsw_pd.dma_has_sram = true;
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@ -759,7 +763,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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#define ENETSW_MAX_PORT 8
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#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
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#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
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+#define ENETSW_PORTS_63268 4 /* 3 FE PHY + 1 RGMII */
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+#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */
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#define ENETSW_RGMII_PORT0 4
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@ -644,8 +644,8 @@ Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318
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- if (BCMCPU_IS_6328())
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+ if (BCMCPU_IS_6318() || BCMCPU_IS_6328())
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enetsw_pd.num_ports = ENETSW_PORTS_6328;
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else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
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enetsw_pd.num_ports = ENETSW_PORTS_6368;
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else if (BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
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BCMCPU_VARIANT_IS_63168() || BCMCPU_VARIANT_IS_63169())
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
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@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
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