ar71xx: add kernel support for Atheros AP132 Reference Board
Based on http://patchwork.openwrt.org/patch/3162/ Signed-off-by: Embedded Wireless GmbH <info at embeddedwireless.de> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 35395
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Gabor Juhos
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8a9d92f125
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5ca187570f
3 changed files with 231 additions and 0 deletions
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@ -28,6 +28,7 @@ CONFIG_ATH79_MACH_ALL0258N=y
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CONFIG_ATH79_MACH_ALL0315N=y
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CONFIG_ATH79_MACH_AP113=y
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CONFIG_ATH79_MACH_AP121=y
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CONFIG_ATH79_MACH_AP132=y
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CONFIG_ATH79_MACH_AP136=y
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CONFIG_ATH79_MACH_AP81=y
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CONFIG_ATH79_MACH_AP83=y
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189
target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c
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target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c
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@ -0,0 +1,189 @@
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/*
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* Atheros AP132 reference board support
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*
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* Copyright (c) 2012 Qualcomm Atheros
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* Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2013 Embedded Wireless GmbH <info@embeddedwireless.de>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/ar8216_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-gpio-buttons.h"
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#include "dev-eth.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define AP132_GPIO_LED_USB 4
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#define AP132_GPIO_LED_WLAN_5G 12
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#define AP132_GPIO_LED_WLAN_2G 13
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#define AP132_GPIO_LED_STATUS_RED 14
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#define AP132_GPIO_LED_WPS_RED 15
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#define AP132_GPIO_BTN_WPS 16
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#define AP132_KEYS_POLL_INTERVAL 20 /* msecs */
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#define AP132_KEYS_DEBOUNCE_INTERVAL (3 * AP132_KEYS_POLL_INTERVAL)
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#define AP132_MAC0_OFFSET 0
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#define AP132_WMAC_CALDATA_OFFSET 0x1000
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static struct gpio_led ap132_leds_gpio[] __initdata = {
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{
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.name = "ap132:red:status",
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.gpio = AP132_GPIO_LED_STATUS_RED,
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.active_low = 1,
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},
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{
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.name = "ap132:red:wps",
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.gpio = AP132_GPIO_LED_WPS_RED,
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.active_low = 1,
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},
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{
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.name = "ap132:red:wlan-2g",
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.gpio = AP132_GPIO_LED_WLAN_2G,
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.active_low = 1,
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},
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{
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.name = "ap132:red:usb",
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.gpio = AP132_GPIO_LED_USB,
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.active_low = 1,
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}
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};
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static struct gpio_keys_button ap132_gpio_keys[] __initdata = {
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{
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.desc = "WPS button",
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.type = EV_KEY,
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.code = KEY_WPS_BUTTON,
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.debounce_interval = AP132_KEYS_DEBOUNCE_INTERVAL,
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.gpio = AP132_GPIO_BTN_WPS,
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.active_low = 1,
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},
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};
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static struct ar8327_pad_cfg ap132_ar8327_pad0_cfg;
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static struct ar8327_platform_data ap132_ar8327_data = {
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.pad0_cfg = &ap132_ar8327_pad0_cfg,
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.port0_cfg = {
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.force_link = 1,
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.speed = AR8327_PORT_SPEED_1000,
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.duplex = 1,
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.txpause = 1,
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.rxpause = 1,
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},
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};
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static struct mdio_board_info ap132_mdio1_info[] = {
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{
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.bus_id = "ag71xx-mdio.1",
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.phy_addr = 0,
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.platform_data = &ap132_ar8327_data,
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},
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};
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static void __init ap132_mdio_setup(void)
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{
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void __iomem *base;
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u32 t;
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#define GPIO_IN_ENABLE3_ADDRESS 0x0050
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#define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK 0x00ff0000
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#define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB 16
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#define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x) (((x) << GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK)
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#define GPIO_OUT_FUNCTION4_ADDRESS 0x003c
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#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK 0xff000000
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#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB 24
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#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK)
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#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00
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#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8
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#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK)
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base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
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t = __raw_readl(base + GPIO_IN_ENABLE3_ADDRESS);
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t &= ~GPIO_IN_ENABLE3_MII_GE1_MDI_MASK;
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t |= GPIO_IN_ENABLE3_MII_GE1_MDI_SET(19);
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__raw_writel(t, base + GPIO_IN_ENABLE3_ADDRESS);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 19), base + AR71XX_GPIO_REG_OE);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 17), base + AR71XX_GPIO_REG_OE);
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t = __raw_readl(base + GPIO_OUT_FUNCTION4_ADDRESS);
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t &= ~(GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK);
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t |= GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(0x20) | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(0x21);
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__raw_writel(t, base + GPIO_OUT_FUNCTION4_ADDRESS);
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iounmap(base);
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}
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static void __init ap132_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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ath79_register_m25p80(NULL);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(ap132_leds_gpio),
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ap132_leds_gpio);
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ath79_register_gpio_keys_polled(-1, AP132_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(ap132_gpio_keys),
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ap132_gpio_keys);
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ath79_register_usb();
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ath79_register_wmac(art + AP132_WMAC_CALDATA_OFFSET, NULL);
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/* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
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ap132_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
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ap132_ar8327_pad0_cfg.sgmii_delay_en = true;
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ath79_eth1_pll_data.pll_1000 = 0x03000101;
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ap132_mdio_setup();
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ath79_register_mdio(1, 0x0);
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ath79_init_mac(ath79_eth1_data.mac_addr, art + AP132_MAC0_OFFSET, 0);
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mdiobus_register_board_info(ap132_mdio1_info,
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ARRAY_SIZE(ap132_mdio1_info));
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/* GMAC1 is connected to the SGMII interface */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
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ath79_eth1_data.speed = SPEED_1000;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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ath79_eth1_data.phy_mask = BIT(0);
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ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
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ath79_register_eth(1);
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}
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MIPS_MACHINE(ATH79_MACH_AP132, "AP132",
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"Atheros AP132 reference board",
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ap132_setup);
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@ -0,0 +1,41 @@
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -70,6 +70,18 @@ config ATH79_MACH_AP121
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Say 'Y' here if you want your kernel to support the
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Atheros AP121 reference board.
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+config ATH79_MACH_AP132
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+ bool "Atheros AP132 reference board"
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+ select SOC_QCA955X
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_SPI
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+ select ATH79_DEV_USB
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+ select ATH79_DEV_WMAC
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+ help
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+ Say 'Y' here if you want your kernel to support the
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+ Atheros AP132 reference boards.
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+
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config ATH79_MACH_AP136
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bool "Atheros AP136/AP135 reference board"
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select SOC_QCA955X
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--- a/arch/mips/ath79/machtypes.h
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+++ b/arch/mips/ath79/machtypes.h
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@@ -24,6 +24,7 @@ enum ath79_mach_type {
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ATH79_MACH_AP113, /* Atheros AP113 reference board */
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ATH79_MACH_AP121, /* Atheros AP121 reference board */
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ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
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+ ATH79_MACH_AP132, /* Atheros AP132 reference board */
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ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */
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ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
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ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */
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--- a/arch/mips/ath79/Makefile
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+++ b/arch/mips/ath79/Makefile
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@@ -44,6 +44,7 @@ obj-$(CONFIG_ATH79_MACH_ALL0258N) += mac
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obj-$(CONFIG_ATH79_MACH_ALL0315N) += mach-all0315n.o
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obj-$(CONFIG_ATH79_MACH_AP113) += mach-ap113.o
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obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
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+obj-$(CONFIG_ATH79_MACH_AP132) += mach-ap132.o
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obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
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obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
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obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o
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