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* adds stage1 lzma * new boards * fixes settings for PSC ram * lost of cleanups

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SVN-Revision: 25694
This commit is contained in:
John Crispin 2011-02-24 07:41:10 +00:00
parent cf3b7563cf
commit 54734b3d7d
30 changed files with 3216 additions and 453 deletions
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52
package/uboot-lantiq/Makefile
View file

@ -46,23 +46,35 @@ DDR_CONFIG_easy50712_DDR166M_ramboot:=easy50712_DDR166M
DDR_CONFIG_easy50812_DDR166M_ramboot:=easy50812
#Arcadyan
Package/uboot-lantiq-arv4518PW=$(call Package/uboot-lantiq-template,arv4518PW_flash,NOR)
Package/uboot-lantiq-arv3527P_flash=$(call Package/uboot-lantiq-template,arv3527P_flash,NOR)
Package/uboot-lantiq-arv3527P_ramboot=$(call Package/uboot-lantiq-template,arv3527P_ramboot,RAM)
Package/uboot-lantiq-arv3527P_brnboot=$(call Package/uboot-lantiq-template,arv3527P_brnboot,BRN)
Package/uboot-lantiq-arv4518PW_flash=$(call Package/uboot-lantiq-template,arv4518PW_flash,NOR)
Package/uboot-lantiq-arv4518PW_ramboot=$(call Package/uboot-lantiq-template,arv4518PW_ramboot,RAM)
Package/uboot-lantiq-arv4518PW_brnboot=$(call Package/uboot-lantiq-template,arv4518PW_brnboot,BRN)
Package/uboot-lantiq-arv452CPW=$(call Package/uboot-lantiq-template,arv452CPW_flash,NOR)
Package/uboot-lantiq-arv4520PW_flash=$(call Package/uboot-lantiq-template,arv4520PW_flash,NOR)
Package/uboot-lantiq-arv4520PW_ramboot=$(call Package/uboot-lantiq-template,arv4520PW_ramboot,RAM)
Package/uboot-lantiq-arv4520PW_brnboot=$(call Package/uboot-lantiq-template,arv4520PW_brnboot,BRN)
Package/uboot-lantiq-arv4525PW_flash=$(call Package/uboot-lantiq-template,arv4525PW_flash,NOR)
Package/uboot-lantiq-arv4525PW_ramboot=$(call Package/uboot-lantiq-template,arv4525PW_ramboot,RAM)
Package/uboot-lantiq-arv4525PW_brnboot=$(call Package/uboot-lantiq-template,arv4525PW_brnboot,BRN)
Package/uboot-lantiq-arv452CPW_flash=$(call Package/uboot-lantiq-template,arv452CPW_flash,NOR)
Package/uboot-lantiq-arv452CPW_ramboot=$(call Package/uboot-lantiq-template,arv452CPW_ramboot,RAM)
Package/uboot-lantiq-arv452CPW_brnboot=$(call Package/uboot-lantiq-template,arv452CPW_brnboot,BRN)
Package/uboot-lantiq-arv752DPW=$(call Package/uboot-lantiq-template,arv752DPW_flash,NOR)
Package/uboot-lantiq-arv752DPW_flash=$(call Package/uboot-lantiq-template,arv752DPW_flash,NOR)
Package/uboot-lantiq-arv752DPW_ramboot=$(call Package/uboot-lantiq-template,arv752DPW_ramboot,RAM)
Package/uboot-lantiq-arv752DPW_brnboot=$(call Package/uboot-lantiq-template,arv752DPW_brnboot,BRN)
Package/uboot-lantiq-arv752DPW22=$(call Package/uboot-lantiq-template,arv752DPW22_flash,NOR)
Package/uboot-lantiq-arv752DPW22_flash=$(call Package/uboot-lantiq-template,arv752DPW22_flash,NOR)
Package/uboot-lantiq-arv752DPW22_ramboot=$(call Package/uboot-lantiq-template,arv752DPW22_ramboot,RAM)
Package/uboot-lantiq-arv752DPW22_brnboot=$(call Package/uboot-lantiq-template,arv752DPW22_brnboot,BRN)
DDR_CONFIG_arv4518_ramboot:=arcadyan_psc166
DDR_CONFIG_arv452C_ramboot:=arcadyan_psc166
DDR_CONFIG_arv752DPW_ramboot:=arcadyan_psc166
DDR_CONFIG_arv752DPW22_ramboot:=arcadyan_psc166
DDR_CONFIG_arv3527P_ramboot:=arcadyan_psc166_32
DDR_CONFIG_arv4518PW_ramboot:=arcadyan_psc166_64
DDR_CONFIG_arv4520PW_ramboot:=arcadyan_psc166_32
DDR_CONFIG_arv4525PW_ramboot:=arcadyan_psc166_32
DDR_CONFIG_arv452CPW_ramboot:=arcadyan_psc166_32
DDR_CONFIG_arv752DPW_ramboot:=arcadyan_psc166_64
DDR_CONFIG_arv752DPW22_ramboot:=arcadyan_psc166_64
define Build/Prepare
$(PKG_UNPACK)
@ -100,10 +112,17 @@ endef
define Package/uboot-lantiq-$(BUILD_VARIANT)/install
mkdir -p $(1)
ifneq ($(findstring flash,$(BUILD_VARIANT)),)
dd \
if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot-bootstrap.bin \
of=$(1)/u-boot-bootstrap.bin \
bs=64k conv=sync
else
dd \
if=$(PKG_BUILD_DIR)/$(BUILD_VARIANT)/u-boot.bin \
of=$(1)/u-boot.bin \
bs=64k conv=sync
endif
ifneq ($(findstring ramboot,$(BUILD_VARIANT)),)
if [ -e $(DDR_CONFIG_$(BUILD_VARIANT)).conf ]; then \
perl ./gct \
@ -118,16 +137,25 @@ $(eval $(call BuildPackage,uboot-lantiq-easy50712_DDR166M))
$(eval $(call BuildPackage,uboot-lantiq-easy50712_DDR166M_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-easy50812_DDR166M))
$(eval $(call BuildPackage,uboot-lantiq-easy50812_DDR166M_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4518PW))
#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_flash))
#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_brnboot))
#$(eval $(call BuildPackage,uboot-lantiq-arv3527P_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4518PW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv452CPW))
$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4520PW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW_ramboot))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_flash))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_brnboot))
$(eval $(call BuildPackage,uboot-lantiq-arv752DPW22_ramboot))

71
package/uboot-lantiq/arcadyan_psc166_32.conf Normal file
View file

@ -0,0 +1,71 @@
0xbf800060 0x7
0xbf800010 0x0
0xbf800020 0x0
0xbf800200 0x02
0xbf800210 0x0
0xbf801000 0x1b1b
0xbf801010 0x0
0xbf801020 0x0
0xbf801030 0x0
0xbf801040 0x0
0xbf801050 0x200
0xbf801060 0x605
0xbf801070 0x0303
0xbf801080 0x102
0xbf801090 0x70a
0xbf8010a0 0x203
0xbf8010b0 0xc02
0xbf8010c0 0x1c8
0xbf8010d0 0x1
0xbf8010e0 0x0
0xbf8010f0 0x120
0xbf801100 0xc800
0xbf801110 0xd
0xbf801120 0x301
0xbf801130 0x200
0xbf801140 0xa04
0xbf801150 0x1700
0xbf801160 0x1717
0xbf801170 0x0
0xbf801180 0x52
0xbf801190 0x0
0xbf8011a0 0x0
0xbf8011b0 0x0
0xbf8011c0 0x510
0xbf8011d0 0x4e20
0xbf8011e0 0x8235
0xbf8011f0 0x0
0xbf801200 0x0
0xbf801210 0x0
0xbf801220 0x0
0xbf801230 0x0
0xbf801240 0x0
0xbf801250 0x0
0xbf801260 0x0
0xbf801270 0x0
0xbf801280 0x0
0xbf801290 0x0
0xbf8012a0 0x0
0xbf8012b0 0x0
0xbf8012c0 0x0
0xbf8012d0 0x500
0xbf8012e0 0x0
0xbf800060 0x05
0xbf801030 0x100

0
package/uboot-lantiq/arcadyan_psc166.conf → package/uboot-lantiq/arcadyan_psc166_64.conf
View file

18
package/uboot-lantiq/files/board/arcadyan/Makefile
View file

@ -24,18 +24,34 @@
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
BOOTSTRAP_LIB = $(obj)lib$(BOARD)_bootstrap.a
BOOTSTRAP_LIB-$(CONFIG_BOOTSTRAP) = $(BOOTSTRAP_LIB)
COBJS-y += board.o athrs26_phy.o
SOBJS = lowlevel_init.o pmuenable.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
BOOTSTRAP_COBJS-$(CONFIG_BOOTSTRAP) = $(BOARD)_bootstrap.o
BOOTSTRAP_SOBJS-$(CONFIG_BOOTSTRAP) = lowlevel_bootstrap_init.o
BOOTSTRAP_SRCS := $(BOOTSTRAP_SOBJS-y:.o=.S) $(BOOTSTRAP_COBJS-y:.o=.c)
SRCS := $(sort $(SOBJS:.o=.S) $(COBJS:.o=.c) $(BOOTSTRAP_SOBJS:.o=.S))
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
BOOTSTRAP_OBJS := $(addprefix $(obj),$(BOOTSTRAP_COBJS-y))
BOOTSTRAP_SOBJS := $(addprefix $(obj),$(BOOTSTRAP_SOBJS-y))
all: $(obj).depend $(LIB) $(BOOTSTRAP_LIB)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
$(BOOTSTRAP_LIB): $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
$(AR) $(ARFLAGS) $@ $(BOOTSTRAP_OBJS) $(BOOTSTRAP_SOBJS)
#########################################################################
# defines $(obj).depend target

48
package/uboot-lantiq/files/board/arcadyan/arcadyan_bootstrap.c Normal file
View file

@ -0,0 +1,48 @@
/*
* (C) Copyright 2010 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
*
* (C) Copyright 2007
* Vlad Lungu vlad.lungu@windriver.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
phys_size_t bootstrap_initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
return CONFIG_SYS_MAX_RAM;
}
int bootstrap_checkboard(void)
{
return 0;
}
int bootstrap_misc_init_r(void)
{
set_io_port_base(0);
return 0;
}

16
package/uboot-lantiq/files/board/arcadyan/athrs26_phy.c
View file

@ -201,7 +201,7 @@ static int cmd = 1;
/* Forward references */
BOOL athrs26_phy_is_link_alive(int phyUnit);
static uint32_t athrs26_reg_read(uint16_t reg_addr);
//static uint32_t athrs26_reg_read(uint16_t reg_addr);
static void athrs26_reg_write(uint16_t reg_addr,
uint32_t reg_val);
@ -214,7 +214,7 @@ static void athrs26_reg_write(uint16_t reg_addr,
* FALSE --> link is down
*/
void athrs26_reg_init()
void athrs26_reg_init(void)
{
athrs26_reg_write(0x200, 0x200);
@ -751,7 +751,7 @@ void athrs26_reg_dev(struct eth_device *mac)
#endif
static uint32_t
/*static uint32_t
athrs26_reg_read(uint16_t reg_addr)
{
#ifndef CFG_ATHRHDR_REG
@ -759,15 +759,13 @@ athrs26_reg_read(uint16_t reg_addr)
uint32_t phy_addr;
uint8_t phy_reg;
/* configure register high address */
phy_addr = 0x18;
phy_reg = 0x0;
phy_val = (reg_word_addr >> 8) & 0x1ff; /* bit16-8 of reg address*/
phy_val = (reg_word_addr >> 8) & 0x1ff;
phy_reg_write (0, phy_addr, phy_reg, phy_val);
/* read register with low address */
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
phy_reg = reg_word_addr & 0x1f; /* bit 4-0 of reg address*/
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7);
phy_reg = reg_word_addr & 0x1f;
phy_reg_read(0, phy_addr, phy_reg, &phy_val);
return phy_val;
@ -779,7 +777,7 @@ athrs26_reg_read(uint16_t reg_addr)
return (reg_data[0] | (reg_data[1] << 8) | (reg_data[2] << 16) | (reg_data[3] << 24));
#endif
}
*/
static void
athrs26_reg_write(uint16_t reg_addr, uint32_t reg_val)
{

8
package/uboot-lantiq/files/board/arcadyan/board.c
View file

@ -214,7 +214,13 @@ static void gpio_default(void)
setenv("bootcmd", "httpd");
}
#endif
#ifdef CONFIG_ARV4525
*DANUBE_GPIO_P0_ALTSEL0 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
*DANUBE_GPIO_P0_ALTSEL1 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
*DANUBE_GPIO_P0_OD |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
*DANUBE_GPIO_P0_DIR |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
*DANUBE_GPIO_P0_OUT &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
#endif
}
int checkboard (void)

34
package/uboot-lantiq/files/board/arcadyan/config.mk
View file

@ -20,41 +20,17 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Danube board with MIPS 24Kc CPU core
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifdef CONFIG_LZMA_BOOTSTRAP
ifdef BUILD_BOOTSTRAP
$(info BUILD_BOOTSTRAP )
#TEXT_BASE = 0xB0000000
TEXT_BASE = 0x80010000
else # BUILD_BOOTSTRAP
ifndef TEXT_BASE
$(info redefine TEXT_BASE = 0x80040000 )
TEXT_BASE = 0x80040000
endif
endif # BUILD_BOOTSTRAP
ifdef CONFIG_BOOTSTRAP
TEXT_BASE = 0x80001000
CONFIG_BOOTSTRAP_TEXT_BASE = 0xb0000000
CONFIG_SYS_RAMBOOT = y
else
ifdef BUILD_BOOTSTRAP
$(error BUILD_BOOTSTRAP but not enabled in config)
endif
ifndef TEXT_BASE
## Standard: boot from ebu
$(info redefine TEXT_BASE = 0xB0000000 )
TEXT_BASE = 0xB0000000
## For testing: boot from RAM
# TEXT_BASE = 0x80100000
endif
endif # CONFIG_LZMA_BOOTSTRAP
endif

0
package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_166.h → package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_32.h
View file

29
package/uboot-lantiq/files/board/arcadyan/ddr_settings_qimonda.h → package/uboot-lantiq/files/board/arcadyan/ddr_settings_psc_64.h
View file

@ -1,12 +1,9 @@
/* Settings for Denali DDR SDRAM controller */
/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */
#define MC_DC0_VALUE 0x1B1B
#define MC_DC1_VALUE 0xc0
#define MC_DC1_VALUE 0x0
#define MC_DC2_VALUE 0x0
#define MC_DC3_VALUE 0x100
#define MC_DC4_VALUE 0xd0f
#define MC_DC5_VALUE 0x204
#define MC_DC3_VALUE 0x0
#define MC_DC4_VALUE 0x0
#define MC_DC5_VALUE 0x200
#define MC_DC6_VALUE 0x605
#define MC_DC7_VALUE 0x303
#define MC_DC8_VALUE 0x102
@ -16,22 +13,22 @@
#define MC_DC12_VALUE 0x1C8
#define MC_DC13_VALUE 0x1
#define MC_DC14_VALUE 0x0
#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
#define MC_DC15_VALUE 0x134 /* WDQS tuning for clk_wr*/
#define MC_DC16_VALUE 0xC800
#define MC_DC17_VALUE 0xd
#define MC_DC18_VALUE 0x300
#define MC_DC18_VALUE 0x301
#define MC_DC19_VALUE 0x200
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0xd47
#define MC_DC22_VALUE 0xd0d
#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
#define MC_DC21_VALUE 0x1400
#define MC_DC22_VALUE 0x1414
#define MC_DC23_VALUE 0x0
#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */
#define MC_DC24_VALUE 0x5b /* WDQS Tuning for DQS */
#define MC_DC25_VALUE 0x0
#define MC_DC26_VALUE 0x0
#define MC_DC27_VALUE 0x2040
#define MC_DC27_VALUE 0x0
#define MC_DC28_VALUE 0x510
#define MC_DC29_VALUE 0x2d89
#define MC_DC30_VALUE 0x8300
#define MC_DC29_VALUE 0x4e20
#define MC_DC30_VALUE 0x8235
#define MC_DC31_VALUE 0x0
#define MC_DC32_VALUE 0x0
#define MC_DC33_VALUE 0x0

583
package/uboot-lantiq/files/board/arcadyan/lowlevel_bootstrap_init.S Normal file
View file

@ -0,0 +1,583 @@
/*
* Memory sub-system initialization code for Danube board.
* Andre Messerschmidt
* Copyright (c) 2005 Infineon Technologies AG
*
* Based on Inca-IP code
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* History:
peng liu May 25, 2006, for PLL setting after reset, 05252006
*/
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#if defined(CONFIG_USE_DDR_PSC_32)
#include "ddr_settings_psc_32.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_PSC_64)
#include "ddr_settings_psc_64.h"
#define DDR166
#else
#error "missing definition for RAM"
#endif
#define EBU_MODUL_BASE 0xBE105300
#define EBU_CLC(value) 0x0000(value)
#define EBU_CON(value) 0x0010(value)
#define EBU_ADDSEL0(value) 0x0020(value)
#define EBU_ADDSEL1(value) 0x0024(value)
#define EBU_ADDSEL2(value) 0x0028(value)
#define EBU_ADDSEL3(value) 0x002C(value)
#define EBU_BUSCON0(value) 0x0060(value)
#define EBU_BUSCON1(value) 0x0064(value)
#define EBU_BUSCON2(value) 0x0068(value)
#define EBU_BUSCON3(value) 0x006C(value)
#define MC_MODUL_BASE 0xBF800000
#define MC_ERRCAUSE(value) 0x0010(value)
#define MC_ERRADDR(value) 0x0020(value)
#define MC_CON(value) 0x0060(value)
#define MC_SRAM_ENABLE 0x00000004
#define MC_SDRAM_ENABLE 0x00000002
#define MC_DDRRAM_ENABLE 0x00000001
#define MC_SDR_MODUL_BASE 0xBF800200
#define MC_IOGP(value) 0x0000(value)
#define MC_CTRLENA(value) 0x0010(value)
#define MC_MRSCODE(value) 0x0020(value)
#define MC_CFGDW(value) 0x0030(value)
#define MC_CFGPB0(value) 0x0040(value)
#define MC_LATENCY(value) 0x0080(value)
#define MC_TREFRESH(value) 0x0090(value)
#define MC_SELFRFSH(value) 0x00A0(value)
#define MC_DDR_MODUL_BASE 0xBF801000
#define MC_DC00(value) 0x0000(value)
#define MC_DC01(value) 0x0010(value)
#define MC_DC02(value) 0x0020(value)
#define MC_DC03(value) 0x0030(value)
#define MC_DC04(value) 0x0040(value)
#define MC_DC05(value) 0x0050(value)
#define MC_DC06(value) 0x0060(value)
#define MC_DC07(value) 0x0070(value)
#define MC_DC08(value) 0x0080(value)
#define MC_DC09(value) 0x0090(value)
#define MC_DC10(value) 0x00A0(value)
#define MC_DC11(value) 0x00B0(value)
#define MC_DC12(value) 0x00C0(value)
#define MC_DC13(value) 0x00D0(value)
#define MC_DC14(value) 0x00E0(value)
#define MC_DC15(value) 0x00F0(value)
#define MC_DC16(value) 0x0100(value)
#define MC_DC17(value) 0x0110(value)
#define MC_DC18(value) 0x0120(value)
#define MC_DC19(value) 0x0130(value)
#define MC_DC20(value) 0x0140(value)
#define MC_DC21(value) 0x0150(value)
#define MC_DC22(value) 0x0160(value)
#define MC_DC23(value) 0x0170(value)
#define MC_DC24(value) 0x0180(value)
#define MC_DC25(value) 0x0190(value)
#define MC_DC26(value) 0x01A0(value)
#define MC_DC27(value) 0x01B0(value)
#define MC_DC28(value) 0x01C0(value)
#define MC_DC29(value) 0x01D0(value)
#define MC_DC30(value) 0x01E0(value)
#define MC_DC31(value) 0x01F0(value)
#define MC_DC32(value) 0x0200(value)
#define MC_DC33(value) 0x0210(value)
#define MC_DC34(value) 0x0220(value)
#define MC_DC35(value) 0x0230(value)
#define MC_DC36(value) 0x0240(value)
#define MC_DC37(value) 0x0250(value)
#define MC_DC38(value) 0x0260(value)
#define MC_DC39(value) 0x0270(value)
#define MC_DC40(value) 0x0280(value)
#define MC_DC41(value) 0x0290(value)
#define MC_DC42(value) 0x02A0(value)
#define MC_DC43(value) 0x02B0(value)
#define MC_DC44(value) 0x02C0(value)
#define MC_DC45(value) 0x02D0(value)
#define MC_DC46(value) 0x02E0(value)
#define RCU_OFFSET 0xBF203000
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
#define RCU_STS (RCU_OFFSET + 0x0014)
#define CGU_OFFSET 0xBF103000
#define PLL0_CFG (CGU_OFFSET + 0x0004)
#define PLL1_CFG (CGU_OFFSET + 0x0008)
#define PLL2_CFG (CGU_OFFSET + 0x000C)
#define CGU_SYS (CGU_OFFSET + 0x0010)
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
#define IF_CLK (CGU_OFFSET + 0x0018)
#define CGU_SMD (CGU_OFFSET + 0x0020)
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
//05252006
#define pll0_35MHz_CONFIG 0x9D861059
#define pll1_35MHz_CONFIG 0x1A260CD9
#define pll2_35MHz_CONFIG 0x8000f1e5
#define pll0_36MHz_CONFIG 0x1000125D
#define pll1_36MHz_CONFIG 0x1B1E0C99
#define pll2_36MHz_CONFIG 0x8002f2a1
//05252006
//06063001-joelin disable the PCI CFRAME mask -start
/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
*/
#define PCI_CR_PR_OFFSET 0xBE105400
#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
#define PCI_CONFIG_SPACE 0xB7000000
#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
//06063001-joelin disable the PCI CFRAME mask -end
.set noreorder
/*
* void ebu_init(void)
*/
.globl ebu_init
.ent ebu_init
ebu_init:
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
li t1, EBU_MODUL_BASE
#if defined(CONFIG_EBU_ADDSEL0)
li t2, CONFIG_EBU_ADDSEL0
sw t2, EBU_ADDSEL0(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL1)
li t2, CONFIG_EBU_ADDSEL1
sw t2, EBU_ADDSEL1(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL2)
li t2, CONFIG_EBU_ADDSEL2
sw t2, EBU_ADDSEL2(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL3)
li t2, CONFIG_EBU_ADDSEL3
sw t2, EBU_ADDSEL3(t1)
#endif
#if defined(CONFIG_EBU_BUSCON0)
li t2, CONFIG_EBU_BUSCON0
sw t2, EBU_BUSCON0(t1)
#endif
#if defined(CONFIG_EBU_BUSCON1)
li t2, CONFIG_EBU_BUSCON1
sw t2, EBU_BUSCON1(t1)
#endif
#if defined(CONFIG_EBU_BUSCON2)
li t2, CONFIG_EBU_BUSCON2
sw t2, EBU_BUSCON2(t1)
#endif
#if defined(CONFIG_EBU_BUSCON3)
li t2, CONFIG_EBU_BUSCON3
sw t2, EBU_BUSCON3(t1)
#endif
#endif
j ra
nop
.end ebu_init
/*
* void cgu_init(long)
*
* a0 has the clock value
*/
.globl cgu_init
.ent cgu_init
cgu_init:
li t2, CGU_SYS
lw t2,0(t2)
beq t2,a0,freq_up2date
nop
li t2, RCU_STS
lw t2, 0(t2)
and t2,0x00020000
beq t2,0x00020000,boot_36MHZ
nop
//05252006
li t1, PLL0_CFG
li t2, pll0_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_35MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_35MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
b wait_reset
nop
boot_36MHZ:
li t1, PLL0_CFG
li t2, pll0_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL1_CFG
li t2, pll1_36MHz_CONFIG
sw t2,0(t1)
li t1, PLL2_CFG
li t2, pll2_36MHz_CONFIG
sw t2,0(t1)
li t1, CGU_SYS
sw a0,0(t1)
li t1, RCU_RST_REQ
li t2, 0x40000008
sw t2,0(t1)
//05252006
wait_reset:
b wait_reset
nop
freq_up2date:
j ra
nop
.end cgu_init
#ifndef CONFIG_USE_DDR_RAM
/*
* void sdram_init(long)
*
* a0 has the clock value
*/
.globl sdram_init
.ent sdram_init
sdram_init:
/* SDRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable SDRAM module in memory controller */
li t3, MC_SDRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_SDR_MODUL_BASE
/* disable the controller */
li t2, 0
sw t2, MC_CTRLENA(t1)
li t2, 0x822
sw t2, MC_IOGP(t1)
li t2, 0x2
sw t2, MC_CFGDW(t1)
/* Set CAS Latency */
li t2, 0x00000020
sw t2, MC_MRSCODE(t1)
/* Set CS0 to SDRAM parameters */
li t2, 0x000014d8
sw t2, MC_CFGPB0(t1)
/* Set SDRAM latency parameters */
li t2, 0x00036325; /* BC PC100 */
sw t2, MC_LATENCY(t1)
/* Set SDRAM refresh rate */
li t2, 0x00000C30
sw t2, MC_TREFRESH(t1)
/* Clear Power-down registers */
sw zero, MC_SELFRFSH(t1)
/* Finally enable the controller */
li t2, 1
sw t2, MC_CTRLENA(t1)
j ra
nop
.end sdram_init
#endif /* !CONFIG_USE_DDR_RAM */
#ifdef CONFIG_USE_DDR_RAM
/*
* void ddrram_init(long)
*
* a0 has the clock value
*/
.globl ddrram_init
.ent ddrram_init
ddrram_init:
/* DDR-DRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable DDR module in memory controller */
li t3, MC_DDRRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_DDR_MODUL_BASE
/* Write configuration to DDR controller registers */
li t2, MC_DC0_VALUE
sw t2, MC_DC00(t1)
li t2, MC_DC1_VALUE
sw t2, MC_DC01(t1)
li t2, MC_DC2_VALUE
sw t2, MC_DC02(t1)
li t2, MC_DC3_VALUE
sw t2, MC_DC03(t1)
li t2, MC_DC4_VALUE
sw t2, MC_DC04(t1)
li t2, MC_DC5_VALUE
sw t2, MC_DC05(t1)
li t2, MC_DC6_VALUE
sw t2, MC_DC06(t1)
li t2, MC_DC7_VALUE
sw t2, MC_DC07(t1)
li t2, MC_DC8_VALUE
sw t2, MC_DC08(t1)
li t2, MC_DC9_VALUE
sw t2, MC_DC09(t1)
li t2, MC_DC10_VALUE
sw t2, MC_DC10(t1)
li t2, MC_DC11_VALUE
sw t2, MC_DC11(t1)
li t2, MC_DC12_VALUE
sw t2, MC_DC12(t1)
li t2, MC_DC13_VALUE
sw t2, MC_DC13(t1)
li t2, MC_DC14_VALUE
sw t2, MC_DC14(t1)
li t2, MC_DC15_VALUE
sw t2, MC_DC15(t1)
li t2, MC_DC16_VALUE
sw t2, MC_DC16(t1)
li t2, MC_DC17_VALUE
sw t2, MC_DC17(t1)
li t2, MC_DC18_VALUE
sw t2, MC_DC18(t1)
li t2, MC_DC19_VALUE
sw t2, MC_DC19(t1)
li t2, MC_DC20_VALUE
sw t2, MC_DC20(t1)
li t2, MC_DC21_VALUE
sw t2, MC_DC21(t1)
li t2, MC_DC22_VALUE
sw t2, MC_DC22(t1)
li t2, MC_DC23_VALUE
sw t2, MC_DC23(t1)
li t2, MC_DC24_VALUE
sw t2, MC_DC24(t1)
li t2, MC_DC25_VALUE
sw t2, MC_DC25(t1)
li t2, MC_DC26_VALUE
sw t2, MC_DC26(t1)
li t2, MC_DC27_VALUE
sw t2, MC_DC27(t1)
li t2, MC_DC28_VALUE
sw t2, MC_DC28(t1)
li t2, MC_DC29_VALUE
sw t2, MC_DC29(t1)
li t2, MC_DC30_VALUE
sw t2, MC_DC30(t1)
li t2, MC_DC31_VALUE
sw t2, MC_DC31(t1)
li t2, MC_DC32_VALUE
sw t2, MC_DC32(t1)
li t2, MC_DC33_VALUE
sw t2, MC_DC33(t1)
li t2, MC_DC34_VALUE
sw t2, MC_DC34(t1)
li t2, MC_DC35_VALUE
sw t2, MC_DC35(t1)
li t2, MC_DC36_VALUE
sw t2, MC_DC36(t1)
li t2, MC_DC37_VALUE
sw t2, MC_DC37(t1)
li t2, MC_DC38_VALUE
sw t2, MC_DC38(t1)
li t2, MC_DC39_VALUE
sw t2, MC_DC39(t1)
li t2, MC_DC40_VALUE
sw t2, MC_DC40(t1)
li t2, MC_DC41_VALUE
sw t2, MC_DC41(t1)
li t2, MC_DC42_VALUE
sw t2, MC_DC42(t1)
li t2, MC_DC43_VALUE
sw t2, MC_DC43(t1)
li t2, MC_DC44_VALUE
sw t2, MC_DC44(t1)
li t2, MC_DC45_VALUE
sw t2, MC_DC45(t1)
li t2, MC_DC46_VALUE
sw t2, MC_DC46(t1)
li t2, 0x00000100
sw t2, MC_DC03(t1)
j ra
nop
.end ddrram_init
#endif /* CONFIG_USE_DDR_RAM */
.globl lowlevel_init
.ent lowlevel_init
lowlevel_init:
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
*/
move t0, ra
/* We rely on the fact that non of the following ..._init() functions
* modify t0
*/
#if defined(DDR166)
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
li a0,0xe8
#elif defined(DDR133)
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
li a0,0xe9
#else /* defined(DDR111) */
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
li a0,0xea
#endif
bal cgu_init
nop
bal ebu_init
nop
//06063001-joelin disable the PCI CFRAME mask-start
#ifdef DISABLE_CFRAME
li t1, PCI_CR_PCI //mw bf103034 80000000
li t2, 0x80000000
sw t2,0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x103
sw t2,0(t1)
li t1, CS_CFM //mw b700006c 0
li t2, 0x00
sw t2, 0(t1)
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
li t2, 0x1000103
sw t2, 0(t1)
#endif
//06063001-joelin disable the PCI CFRAME mask-end
#ifdef CONFIG_USE_DDR_RAM
bal ddrram_init
nop
#else
bal sdram_init
nop
#endif
move ra, t0
j ra
nop
.end lowlevel_init

353
package/uboot-lantiq/files/board/arcadyan/lowlevel_init.S
View file

@ -31,46 +31,14 @@
#include <version.h>
#include <asm/regdef.h>
#if 0
#if defined(CONFIG_USE_DDR_RAM)
#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
#include "ddr_settings_r111.h"
#define DDR111
#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
#include "ddr_settings_r166.h"
#if defined(CONFIG_USE_DDR_PSC_32)
#include "ddr_settings_psc_32.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
#include "ddr_settings_e111.h"
#define DDR111
#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
#include "ddr_settings_e166.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
#include "ddr_settings_PROMOSDDR400.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
#include "ddr_settings_Samsung_166.h"
#define DDR166
#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
#include "ddr_settings_psc_166.h"
#elif defined(CONFIG_USE_DDR_PSC_64)
#include "ddr_settings_psc_64.h"
#define DDR166
#else
#warning "missing definition for ddr_settings.h, use default!"
#include "ddr_settings.h"
#endif
#endif /* CONFIG_USE_DDR_RAM */
#else
#include "ddr_settings_psc_166.h"
#define DDR166
#endif
#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
#error "missing include of ddr_settings.h"
#error "missing definition for RAM"
#endif
#define EBU_MODUL_BASE 0xBE105300
@ -204,48 +172,6 @@ The side effect is the entire PCI block will see CFRAME low all the time meaning
.ent ebu_init
ebu_init:
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
li t1, EBU_MODUL_BASE
#if defined(CONFIG_EBU_ADDSEL0)
li t2, CONFIG_EBU_ADDSEL0
sw t2, EBU_ADDSEL0(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL1)
li t2, CONFIG_EBU_ADDSEL1
sw t2, EBU_ADDSEL1(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL2)
li t2, CONFIG_EBU_ADDSEL2
sw t2, EBU_ADDSEL2(t1)
#endif
#if defined(CONFIG_EBU_ADDSEL3)
li t2, CONFIG_EBU_ADDSEL3
sw t2, EBU_ADDSEL3(t1)
#endif
#if defined(CONFIG_EBU_BUSCON0)
li t2, CONFIG_EBU_BUSCON0
sw t2, EBU_BUSCON0(t1)
#endif
#if defined(CONFIG_EBU_BUSCON1)
li t2, CONFIG_EBU_BUSCON1
sw t2, EBU_BUSCON1(t1)
#endif
#if defined(CONFIG_EBU_BUSCON2)
li t2, CONFIG_EBU_BUSCON2
sw t2, EBU_BUSCON2(t1)
#endif
#if defined(CONFIG_EBU_BUSCON3)
li t2, CONFIG_EBU_BUSCON3
sw t2, EBU_BUSCON3(t1)
#endif
#endif
j ra
nop
@ -313,249 +239,6 @@ freq_up2date:
.end cgu_init
#ifndef CONFIG_USE_DDR_RAM
/*
* void sdram_init(long)
*
* a0 has the clock value
*/
.globl sdram_init
.ent sdram_init
sdram_init:
/* SDRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable SDRAM module in memory controller */
li t3, MC_SDRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_SDR_MODUL_BASE
/* disable the controller */
li t2, 0
sw t2, MC_CTRLENA(t1)
li t2, 0x822
sw t2, MC_IOGP(t1)
li t2, 0x2
sw t2, MC_CFGDW(t1)
/* Set CAS Latency */
li t2, 0x00000020
sw t2, MC_MRSCODE(t1)
/* Set CS0 to SDRAM parameters */
li t2, 0x000014d8
sw t2, MC_CFGPB0(t1)
/* Set SDRAM latency parameters */
li t2, 0x00036325; /* BC PC100 */
sw t2, MC_LATENCY(t1)
/* Set SDRAM refresh rate */
li t2, 0x00000C30
sw t2, MC_TREFRESH(t1)
/* Clear Power-down registers */
sw zero, MC_SELFRFSH(t1)
/* Finally enable the controller */
li t2, 1
sw t2, MC_CTRLENA(t1)
j ra
nop
.end sdram_init
#endif /* !CONFIG_USE_DDR_RAM */
#ifdef CONFIG_USE_DDR_RAM
/*
* void ddrram_init(long)
*
* a0 has the clock value
*/
.globl ddrram_init
.ent ddrram_init
ddrram_init:
/* DDR-DRAM Initialization
*/
li t1, MC_MODUL_BASE
/* Clear Error log registers */
sw zero, MC_ERRCAUSE(t1)
sw zero, MC_ERRADDR(t1)
/* Enable DDR module in memory controller */
li t3, MC_DDRRAM_ENABLE
lw t2, MC_CON(t1)
or t3, t2, t3
sw t3, MC_CON(t1)
li t1, MC_DDR_MODUL_BASE
/* Write configuration to DDR controller registers */
li t2, MC_DC0_VALUE
sw t2, MC_DC00(t1)
li t2, MC_DC1_VALUE
sw t2, MC_DC01(t1)
li t2, MC_DC2_VALUE
sw t2, MC_DC02(t1)
li t2, MC_DC3_VALUE
sw t2, MC_DC03(t1)
li t2, MC_DC4_VALUE
sw t2, MC_DC04(t1)
li t2, MC_DC5_VALUE
sw t2, MC_DC05(t1)
li t2, MC_DC6_VALUE
sw t2, MC_DC06(t1)
li t2, MC_DC7_VALUE
sw t2, MC_DC07(t1)
li t2, MC_DC8_VALUE
sw t2, MC_DC08(t1)
li t2, MC_DC9_VALUE
sw t2, MC_DC09(t1)
li t2, MC_DC10_VALUE
sw t2, MC_DC10(t1)
li t2, MC_DC11_VALUE
sw t2, MC_DC11(t1)
li t2, MC_DC12_VALUE
sw t2, MC_DC12(t1)
li t2, MC_DC13_VALUE
sw t2, MC_DC13(t1)
li t2, MC_DC14_VALUE
sw t2, MC_DC14(t1)
li t2, MC_DC15_VALUE
sw t2, MC_DC15(t1)
li t2, MC_DC16_VALUE
sw t2, MC_DC16(t1)
li t2, MC_DC17_VALUE
sw t2, MC_DC17(t1)
li t2, MC_DC18_VALUE
sw t2, MC_DC18(t1)
li t2, MC_DC19_VALUE
sw t2, MC_DC19(t1)
li t2, MC_DC20_VALUE
sw t2, MC_DC20(t1)
li t2, MC_DC21_VALUE
sw t2, MC_DC21(t1)
li t2, MC_DC22_VALUE
sw t2, MC_DC22(t1)
li t2, MC_DC23_VALUE
sw t2, MC_DC23(t1)
li t2, MC_DC24_VALUE
sw t2, MC_DC24(t1)
li t2, MC_DC25_VALUE
sw t2, MC_DC25(t1)
li t2, MC_DC26_VALUE
sw t2, MC_DC26(t1)
li t2, MC_DC27_VALUE
sw t2, MC_DC27(t1)
li t2, MC_DC28_VALUE
sw t2, MC_DC28(t1)
li t2, MC_DC29_VALUE
sw t2, MC_DC29(t1)
li t2, MC_DC30_VALUE
sw t2, MC_DC30(t1)
li t2, MC_DC31_VALUE
sw t2, MC_DC31(t1)
li t2, MC_DC32_VALUE
sw t2, MC_DC32(t1)
li t2, MC_DC33_VALUE
sw t2, MC_DC33(t1)
li t2, MC_DC34_VALUE
sw t2, MC_DC34(t1)
li t2, MC_DC35_VALUE
sw t2, MC_DC35(t1)
li t2, MC_DC36_VALUE
sw t2, MC_DC36(t1)
li t2, MC_DC37_VALUE
sw t2, MC_DC37(t1)
li t2, MC_DC38_VALUE
sw t2, MC_DC38(t1)
li t2, MC_DC39_VALUE
sw t2, MC_DC39(t1)
li t2, MC_DC40_VALUE
sw t2, MC_DC40(t1)
li t2, MC_DC41_VALUE
sw t2, MC_DC41(t1)
li t2, MC_DC42_VALUE
sw t2, MC_DC42(t1)
li t2, MC_DC43_VALUE
sw t2, MC_DC43(t1)
li t2, MC_DC44_VALUE
sw t2, MC_DC44(t1)
li t2, MC_DC45_VALUE
sw t2, MC_DC45(t1)
li t2, MC_DC46_VALUE
sw t2, MC_DC46(t1)
li t2, 0x00000100
sw t2, MC_DC03(t1)
j ra
nop
.end ddrram_init
#endif /* CONFIG_USE_DDR_RAM */
.globl lowlevel_init
.ent lowlevel_init
lowlevel_init:
@ -565,20 +248,6 @@ lowlevel_init:
/* We rely on the fact that non of the following ..._init() functions
* modify t0
*/
#if defined(CONFIG_SYS_EBU_BOOT)
#if defined(DDR166)
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
li a0,0xe8
#elif defined(DDR133)
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
li a0,0xe9
#else /* defined(DDR111) */
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
li a0,0xea
#endif
bal cgu_init
nop
#endif /* CONFIG_SYS_EBU_BOOT */
bal ebu_init
nop
@ -603,18 +272,6 @@ lowlevel_init:
#endif
//06063001-joelin disable the PCI CFRAME mask-end
#ifdef CONFIG_SYS_EBU_BOOT
#ifndef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_USE_DDR_RAM
bal ddrram_init
nop
#else
bal sdram_init
nop
#endif
#endif /* CONFIG_SYS_RAMBOOT */
#endif /* CONFIG_SYS_EBU_BOOT */
move ra, t0
j ra
nop

74
package/uboot-lantiq/files/board/arcadyan/u-boot-bootstrap.lds Normal file
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@ -0,0 +1,74 @@
/*
* (C) Copyright 2010 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
*
* (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = .;
_gp = ALIGN(16) +0x7ff0;
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
. = ALIGN(4);
.sdata : { *(.sdata) }
. = .;
. = ALIGN(4);
.payload : { *(.payload) }
. = ALIGN(4);
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) . = ALIGN(4); }
uboot_end = .;
}

67
package/uboot-lantiq/files/cpu/mips/ar9-clock.c Normal file
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@ -0,0 +1,67 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/ar9.h>
ulong ifx_get_ddr_hz(void)
{
switch((*AR9_CGU_SYS) & 0x05) {
case 0x01:
case 0x05:
return CLOCK_111M;
case 0x00:
case 0x04:
return CLOCK_166M;
}
return 0;
}
ulong ifx_get_cpuclk(void)
{
switch((*AR9_CGU_SYS) & 0x05) {
case 0x00:
case 0x01:
return CLOCK_333M;
case 0x04:
return CLOCK_166M;
case 0x05:
return CLOCK_111M;
}
return 0;
}
ulong get_bus_freq(ulong dummy)
{
unsigned int ddr_clock=ifx_get_ddr_hz();
if((*AR9_CGU_SYS) & 0x40){
return ddr_clock/2;
} else {
return ddr_clock;
}
}

65
package/uboot-lantiq/files/cpu/mips/danube-clock.c Normal file
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@ -0,0 +1,65 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/danube.h>
ulong ifx_get_ddr_hz(void)
{
static const ulong ddr_freq[] = {166666667,133333333,111111111,83333333};
return ddr_freq[((*DANUBE_CGU_SYS) & 0x3)];
}
ulong ifx_get_cpuclk(void)
{
#ifdef CONFIG_USE_EMULATOR
return EMULATOR_CPU_SPEED;
#else //NOT CONFIG_USE_EMULATOR
unsigned int ddr_clock=ifx_get_ddr_hz();
switch((*DANUBE_CGU_SYS) & 0xc){
case 0:
default:
return 323333333;
case 4:
return ddr_clock;
case 8:
return ddr_clock << 1;
}
#endif
}
ulong get_bus_freq(ulong dummy)
{
#ifdef CONFIG_USE_EMULATOR
unsigned int clkCPU;
clkCPU = ifx_get_cpuclk();
return clkCPU >> 2;
#else //NOT CONFIG_USE_EMULATOR
unsigned int ddr_clock=ifx_get_ddr_hz();
if ((*DANUBE_CGU_SYS) & 0x40){
return ddr_clock >> 1;
}
return ddr_clock;
#endif
}

218
package/uboot-lantiq/files/cpu/mips/ifx_asc.c Normal file
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@ -0,0 +1,218 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* (C) Copyright 2009
* Infineon Technologies AG, http://www.infineon.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include "ifx_asc.h"
#define SET_BIT(reg, mask) asc_writel(reg, asc_readl(reg) | (mask))
#define CLEAR_BIT(reg, mask) asc_writel(reg, asc_readl(reg) & (~mask))
#define SET_BITFIELD(reg, mask, off, val) asc_writel(reg, (asc_readl(reg) & (~mask)) | (val << off) )
#undef DEBUG_ASC_RAW
#ifdef DEBUG_ASC_RAW
#define DEBUG_ASC_RAW_RX_BUF 0xA0800000
#define DEBUG_ASC_RAW_TX_BUF 0xA0900000
#endif
DECLARE_GLOBAL_DATA_PTR;
static IfxAsc_t *pAsc = (IfxAsc_t *)CKSEG1ADDR(CONFIG_SYS_IFX_ASC_BASE);
/*
* FDV fASC
* BaudRate = ----- * --------------------
* 512 16 * (ReloadValue+1)
*/
/*
* FDV fASC
* ReloadValue = ( ----- * --------------- ) - 1
* 512 16 * BaudRate
*/
static void serial_divs(u32 baudrate, u32 fasc, u32 *pfdv, u32 *preload)
{
u32 clock = fasc / 16;
u32 fdv; /* best fdv */
u32 reload = 0; /* best reload */
u32 diff; /* smallest diff */
u32 idiff; /* current diff */
u32 ireload; /* current reload */
u32 i; /* current fdv */
u32 result; /* current resulting baudrate */
if (clock > 0x7FFFFF)
clock /= 512;
else
baudrate *= 512;
fdv = 512; /* start with 1:1 fraction */
diff = baudrate; /* highest possible */
/* i is the test fdv value -- start with the largest possible */
for (i = 512; i > 0; i--)
{
ireload = (clock * i) / baudrate;
if (ireload < 1)
break; /* already invalid */
result = (clock * i) / ireload;
idiff = (result > baudrate) ? (result - baudrate) : (baudrate - result);
if (idiff == 0)
{
fdv = i;
reload = ireload;
break; /* can't do better */
}
else if (idiff < diff)
{
fdv = i; /* best so far */
reload = ireload;
diff = idiff; /* update lowest diff*/
}
}
*pfdv = (fdv == 512) ? 0 : fdv;
*preload = reload - 1;
}
void serial_setbrg (void)
{
u32 ReloadValue, fdv;
serial_divs(gd->baudrate, get_bus_freq(0), &fdv, &ReloadValue);
/* Disable Baud Rate Generator; BG should only be written when R=0 */
CLEAR_BIT(asc_con, ASCCON_R);
/* Enable Fractional Divider */
SET_BIT(asc_con, ASCCON_FDE); /* FDE = 1 */
/* Set fractional divider value */
asc_writel(asc_fdv, fdv & ASCFDV_VALUE_MASK);
/* Set reload value in BG */
asc_writel(asc_bg, ReloadValue);
/* Enable Baud Rate Generator */
SET_BIT(asc_con, ASCCON_R); /* R = 1 */
}
int serial_init (void)
{
/* and we have to set CLC register*/
CLEAR_BIT(asc_clc, ASCCLC_DISS);
SET_BITFIELD(asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
/* initialy we are in async mode */
asc_writel(asc_con, ASCCON_M_8ASYNC);
/* select input port */
asc_writel(asc_pisel, CONSOLE_TTY & 0x1);
/* TXFIFO's filling level */
SET_BITFIELD(asc_txfcon, ASCTXFCON_TXFITLMASK,
ASCTXFCON_TXFITLOFF, ASC_TXFIFO_FL);
/* enable TXFIFO */
SET_BIT(asc_txfcon, ASCTXFCON_TXFEN);
/* RXFIFO's filling level */
SET_BITFIELD(asc_txfcon, ASCRXFCON_RXFITLMASK,
ASCRXFCON_RXFITLOFF, ASC_RXFIFO_FL);
/* enable RXFIFO */
SET_BIT(asc_rxfcon, ASCRXFCON_RXFEN);
/* set baud rate */
serial_setbrg();
/* enable error signals & Receiver enable */
SET_BIT(asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
return 0;
}
void serial_putc (const char c)
{
u32 txFl = 0;
#ifdef DEBUG_ASC_RAW
static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
*debug++=c;
#endif
if (c == '\n')
serial_putc ('\r');
/* check do we have a free space in the TX FIFO */
/* get current filling level */
do {
txFl = ( asc_readl(asc_fstat) & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
}
while ( txFl == ASC_TXFIFO_FULL );
asc_writel(asc_tbuf, c); /* write char to Transmit Buffer Register */
/* check for errors */
if ( asc_readl(asc_state) & ASCSTATE_TOE ) {
SET_BIT(asc_whbstate, ASCWHBSTATE_CLRTOE);
return;
}
}
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
int serial_getc (void)
{
char c;
while ((asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 );
c = (char)(asc_readl(asc_rbuf) & 0xff);
#ifdef DEBUG_ASC_RAW
static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
*debug++=c;
#endif
return c;
}
int serial_tstc (void)
{
int res = 1;
if ( (asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ) {
res = 0;
}
return res;
}

199
package/uboot-lantiq/files/cpu/mips/ifx_asc.h Normal file
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@ -0,0 +1,199 @@
/*****************************************************************************
* DANUBE BootROM
* Copyright (c) 2005, Infineon Technologies AG, All rights reserved
* IFAP DC COM SD
*****************************************************************************/
#ifndef __ASC_H
#define __ASC_H
/* channel operating modes */
#define ASCOPT_CSIZE 0x00000003
#define ASCOPT_CS7 0x00000001
#define ASCOPT_CS8 0x00000002
#define ASCOPT_PARENB 0x00000004
#define ASCOPT_STOPB 0x00000008
#define ASCOPT_PARODD 0x00000010
#define ASCOPT_CREAD 0x00000020
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
#define ASC_TXFIFO_FL 1
#define ASC_RXFIFO_FL 1
#define ASC_TXFIFO_FULL 16
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
#define ASCCLC_DISS 0x00000002
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
/* CON register's bits and bitfields */
#define ASCCON_MODEMASK 0x0000000f
#define ASCCON_M_8ASYNC 0x0
#define ASCCON_M_8IRDA 0x1
#define ASCCON_M_7ASYNC 0x2
#define ASCCON_M_7IRDA 0x3
#define ASCCON_WLSMASK 0x0000000c
#define ASCCON_WLSOFFSET 2
#define ASCCON_WLS_8BIT 0x0
#define ASCCON_WLS_7BIT 0x1
#define ASCCON_PEN 0x00000010
#define ASCCON_ODD 0x00000020
#define ASCCON_SP 0x00000040
#define ASCCON_STP 0x00000080
#define ASCCON_BRS 0x00000100
#define ASCCON_FDE 0x00000200
#define ASCCON_ERRCLK 0x00000400
#define ASCCON_EMMASK 0x00001800
#define ASCCON_EMOFFSET 11
#define ASCCON_EM_ECHO_OFF 0x0
#define ASCCON_EM_ECHO_AB 0x1
#define ASCCON_EM_ECHO_ON 0x2
#define ASCCON_LB 0x00002000
#define ASCCON_ACO 0x00004000
#define ASCCON_R 0x00008000
#define ASCCON_PAL 0x00010000
#define ASCCON_FEN 0x00020000
#define ASCCON_RUEN 0x00040000
#define ASCCON_ROEN 0x00080000
#define ASCCON_TOEN 0x00100000
#define ASCCON_BEN 0x00200000
#define ASCCON_TXINV 0x01000000
#define ASCCON_RXINV 0x02000000
#define ASCCON_TXMSB 0x04000000
#define ASCCON_RXMSB 0x08000000
/* STATE register's bits and bitfields */
#define ASCSTATE_REN 0x00000001
#define ASCSTATE_PE 0x00010000
#define ASCSTATE_FE 0x00020000
#define ASCSTATE_RUE 0x00040000
#define ASCSTATE_ROE 0x00080000
#define ASCSTATE_TOE 0x00100000
#define ASCSTATE_BE 0x00200000
#define ASCSTATE_TXBVMASK 0x07000000
#define ASCSTATE_TXBVOFFSET 24
#define ASCSTATE_TXEOM 0x08000000
#define ASCSTATE_RXBVMASK 0x70000000
#define ASCSTATE_RXBVOFFSET 28
#define ASCSTATE_RXEOM 0x80000000
/* WHBSTATE register's bits and bitfields */
#define ASCWHBSTATE_CLRREN 0x00000001
#define ASCWHBSTATE_SETREN 0x00000002
#define ASCWHBSTATE_CLRPE 0x00000004
#define ASCWHBSTATE_CLRFE 0x00000008
#define ASCWHBSTATE_CLRRUE 0x00000010
#define ASCWHBSTATE_CLRROE 0x00000020
#define ASCWHBSTATE_CLRTOE 0x00000040
#define ASCWHBSTATE_CLRBE 0x00000080
#define ASCWHBSTATE_SETPE 0x00000100
#define ASCWHBSTATE_SETFE 0x00000200
#define ASCWHBSTATE_SETRUE 0x00000400
#define ASCWHBSTATE_SETROE 0x00000800
#define ASCWHBSTATE_SETTOE 0x00001000
#define ASCWHBSTATE_SETBE 0x00002000
/* ABCON register's bits and bitfields */
#define ASCABCON_ABEN 0x0001
#define ASCABCON_AUREN 0x0002
#define ASCABCON_ABSTEN 0x0004
#define ASCABCON_ABDETEN 0x0008
#define ASCABCON_FCDETEN 0x0010
/* FDV register mask, offset and bitfields*/
#define ASCFDV_VALUE_MASK 0x000001FF
/* WHBABCON register's bits and bitfields */
#define ASCWHBABCON_CLRABEN 0x0001
#define ASCWHBABCON_SETABEN 0x0002
/* ABSTAT register's bits and bitfields */
#define ASCABSTAT_FCSDET 0x0001
#define ASCABSTAT_FCCDET 0x0002
#define ASCABSTAT_SCSDET 0x0004
#define ASCABSTAT_SCCDET 0x0008
#define ASCABSTAT_DETWAIT 0x0010
/* WHBABSTAT register's bits and bitfields */
#define ASCWHBABSTAT_CLRFCSDET 0x0001
#define ASCWHBABSTAT_SETFCSDET 0x0002
#define ASCWHBABSTAT_CLRFCCDET 0x0004
#define ASCWHBABSTAT_SETFCCDET 0x0008
#define ASCWHBABSTAT_CLRSCSDET 0x0010
#define ASCWHBABSTAT_SETSCSDET 0x0020
#define ASCWHBABSTAT_CLRSCCDET 0x0040
#define ASCWHBABSTAT_SETSCCDET 0x0080
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
#define ASCWHBABSTAT_SETDETWAIT 0x0200
/* TXFCON register's bits and bitfields */
#define ASCTXFCON_TXFIFO1 0x00000400
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
/* RXFCON register's bits and bitfields */
#define ASCRXFCON_RXFIFO1 0x00000400
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
/* FSTAT register's bits and bitfields */
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
typedef struct IfxAsc_s
{
unsigned long asc_clc; /*0x0000*/
unsigned long asc_pisel; /*0x0004*/
unsigned long asc_id; /*0x0008*/
unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/
unsigned long asc_con; /*0x0010*/
unsigned long asc_state; /*0x0014*/
unsigned long asc_whbstate; /*0x0018*/
unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/
unsigned long asc_tbuf; /*0x0020*/
unsigned long asc_rbuf; /*0x0024*/
unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/
unsigned long asc_abcon; /*0x0030*/
unsigned long asc_abstat; /* not used */ /*0x0034*/
unsigned long asc_whbabcon; /*0x0038*/
unsigned long asc_whbabstat; /* not used */ /*0x003C*/
unsigned long asc_rxfcon; /*0x0040*/
unsigned long asc_txfcon; /*0x0044*/
unsigned long asc_fstat; /*0x0048*/
unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/
unsigned long asc_bg; /*0x0050*/
unsigned long asc_bg_timer; /*0x0054*/
unsigned long asc_fdv; /*0x0058*/
unsigned long asc_pmw; /*0x005C*/
unsigned long asc_modcon; /*0x0060*/
unsigned long asc_modstat; /*0x0064*/
unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/
unsigned long asc_sfcc; /*0x0070*/
unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/
unsigned long asc_eomcon; /*0x0080*/
unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/
unsigned long asc_dmacon; /*0x00EC*/
unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/
unsigned long asc_irnen; /*0x00F4*/
unsigned long asc_irnicr; /*0x00F8*/
unsigned long asc_irncr; /*0x00FC*/
} IfxAsc_t;
/* Register access macros */
#define asc_readl(reg) \
readl(&pAsc->reg)
#define asc_writel(reg,value) \
writel((value), &pAsc->reg)
#endif /* __ASC_H */

18
package/uboot-lantiq/files/include/configs/arcadyan-common.h
View file

@ -28,8 +28,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/* #define DEBUG */
#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */
#define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */
#define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */
@ -67,7 +65,7 @@
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"ram_addr=0x80500000\0" \
"kernel_addr=0xb0050000\0" \
"kernel_addr=0xb0020000\0" \
"flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath} \0" \
@ -89,7 +87,7 @@
"update_uboot=tftp 0x80500000 ${tftppath}u-boot-" CONFIG_ARCADYAN ".bin;era 0xb0000000 +${filesize};" \
"cp.b 0x80500000 0xb0000000 ${filesize}\0" \
"update_openwrt=tftp ${ram_addr} " \
"${tftppath}openwrt-lantiq-xway-" CONFIG_ARCADYAN "-squashfs.image;" \
"${tftppath}" CONFIG_ARCADYAN "-squashfs.image;" \
"era ${kernel_addr} +${filesize};" \
"cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
@ -107,7 +105,7 @@
//#define CLK_OUT2_25MHZ
#define CONFIG_MII
#define CONFIG_CMD_MII
#undef CONFIG_CMD_MII
#define CONFIG_IFX_ASC
@ -135,4 +133,14 @@
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_ROOTPATH "/export"
#ifdef CONFIG_BOOTSTRAP
#define CONFIG_BOOTSTRAP_BASE CONFIG_BOOTSTRAP_TEXT_BASE
#define CONFIG_BOOTSTRAP_BAUDRATE CONFIG_BAUDRATE
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOOTSTRAP_LZMA
//#define CONFIG_BOOTSTRAP_SERIAL
#endif
#endif /* __CONFIG_H */

17
package/uboot-lantiq/files/include/configs/arv3527P.h Normal file
View file

@ -0,0 +1,17 @@
#ifndef __CONFIG_H_3527
#define __CONFIG_H_3527
#define CONFIG_ARV3527 1
#define CONFIG_ARCADYAN "ARV3527P"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV3527 => "
/*#define CONFIG_BUTTON_PORT1
#define CONFIG_BUTTON_PIN 13
#define CONFIG_BUTTON_LEVEL 0
*/
#include "arcadyan-common.h"
#endif

6
package/uboot-lantiq/files/include/configs/arv4518PW.h
View file

@ -5,9 +5,11 @@
#define CONFIG_ARCADYAN "ARV4518PW"
#define CONFIG_SYS_MAX_RAM 64*1024*1024
#define CONFIG_USE_DDR_PSC_64 1
#define CONFIG_SYS_PROMPT "ARV4518 => "
//#define CONFIG_RMII
#define CONFIG_AR8216_SWITCH 1
//#define CONFIG_RMII 1
#define CONFIG_RTL8306_SWITCH 1
#include "arcadyan-common.h"

20
package/uboot-lantiq/files/include/configs/arv4520PW.h Normal file
View file

@ -0,0 +1,20 @@
#ifndef __CONFIG_H_4520
#define __CONFIG_H_4520
#define CONFIG_ARV4520 1
#define CONFIG_ARCADYAN "ARV4520PW"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV4520 => "
#define CONFIG_RMII 1
#define CONFIG_ADM6996_SWITCH 1
#define CONFIG_EBU_GPIO 0x400
#define CONFIG_BUTTON_PORT0
#define CONFIG_BUTTON_PIN 11
#define CONFIG_BUTTON_LEVEL 0
#include "arcadyan-common.h"
#endif

18
package/uboot-lantiq/files/include/configs/arv4525PW.h Normal file
View file

@ -0,0 +1,18 @@
#ifndef __CONFIG_H_4525
#define __CONFIG_H_4525
#define CONFIG_ARV4525 1
#define CONFIG_ARCADYAN "ARV4525PW"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV4525 => "
#define CONFIG_BUTTON_PORT1
#define CONFIG_BUTTON_PIN 13
#define CONFIG_BUTTON_LEVEL 0
#include "arcadyan-common.h"
#endif

8
package/uboot-lantiq/files/include/configs/arv452CPW.h
View file

@ -1,13 +1,19 @@
#ifndef __CONFIG_H_452C
#define __CONFIG_H_452C
#define CONFIG_ARV4518 1
#define CONFIG_ARV452C 1
#define CONFIG_ARCADYAN "ARV452CPW"
#define CONFIG_SYS_MAX_RAM 32*1024*1024
#define CONFIG_USE_DDR_PSC_32 1
#define CONFIG_SYS_PROMPT "ARV452c => "
#define CONFIG_RMII 1
#define CONFIG_RTL8306_SWITCH 1
#define CONFIG_EBU_GPIO 0xf00
#define CONFIG_BUTTON_PORT0
#define CONFIG_BUTTON_PIN 11
#define CONFIG_BUTTON_LEVEL 0
#include "arcadyan-common.h"

5
package/uboot-lantiq/files/include/configs/arv752DPW.h
View file

@ -5,10 +5,11 @@
#define CONFIG_ARCADYAN "ARV752DPW"
#define CONFIG_SYS_MAX_RAM 64*1024*1024
#define CONFIG_USE_DDR_PSC_64 1
#define CONFIG_SYS_PROMPT "ARV752DPW => "
//#define CONFIG_RMII
#define CONFIG_RTL8306_SWITCH 1
#define CONFIG_RMII
#define CONFIG_RTL8306G_SWITCH 1
//#define CONFIG_EBU_GPIO 0x2
#define CONFIG_SWITCH_PORT1
#define CONFIG_SWITCH_PIN 3

1
package/uboot-lantiq/files/include/configs/arv752DPW22.h
View file

@ -5,6 +5,7 @@
#define CONFIG_ARCADYAN "ARV752DPW22"
#define CONFIG_SYS_MAX_RAM 64*1024*1024
#define CONFIG_USE_DDR_PSC_64 1
#define CONFIG_SYS_PROMPT "ARV752DPW22 => "
#define CONFIG_AR8216_SWITCH 1

38
package/uboot-lantiq/files/include/configs/ifx-common.h
View file

@ -32,14 +32,12 @@
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_PREBOOT
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"ram_addr=0x80500000\0" \
"kernel_addr=0xb0050000\0" \
"kernel_addr=0xb0020000\0" \
"mtdparts=mtdparts=ifx-nor:256k(uboot)ro,64k(uboot_env)ro,64k(kernel),-(rootfs)\0" \
"flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@ -85,23 +83,17 @@
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_XIMG
//#define CONFIG_CMD_ASKENV
//#define CONFIG_CMD_DHCP
//#define CONFIG_CMD_ELF
#define CONFIG_CMD_PING
//#define CONFIG_CMD_JFFS2
//#define CONFIG_CMD_SNTP
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_IMI
#undef CONFIG_CMD_PING
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
#undef CONFIG_SYS_HUSH_PARSER
/*
* Miscellaneous configurable options
@ -109,7 +101,7 @@
#define CONFIG_LZMA
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#undef CONFIG_SYS_LONGHELP /* undef to save memory */
#ifndef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#endif
@ -129,7 +121,7 @@
#define CONFIG_SYS_MEMTEST_END 0x80800000
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#undef CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE /* include version env variable */
@ -166,7 +158,7 @@
#define CONFIG_ENV_IS_IN_FLASH 1
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_ADDR 0xB0040000
#define CONFIG_ENV_ADDR 0xB0010000
#define CONFIG_ENV_SIZE 0x10000
#ifdef CONFIG_FLASH_CFI_DRIVER

7
package/uboot-lantiq/patches/000-build-infos.patch
View file

@ -10,7 +10,7 @@ $ make -s V=1
--- a/config.mk
+++ b/config.mk
@@ -234,17 +234,42 @@ export TEXT_BASE PLATFORM_CPPFLAGS PLATF
@@ -234,17 +234,47 @@ export TEXT_BASE PLATFORM_CPPFLAGS PLATF
#########################################################################
@ -38,18 +38,23 @@ $ make -s V=1
+
$(obj)%.s: %.S
+ $(call MESSAGE, [CPP],$(subst $(SRCTREE)/,,$(CURDIR)),$<)
+ #echo $(CPP) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $<
$(CPP) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $<
$(obj)%.o: %.S
+ $(call MESSAGE, [AS], $(subst $(SRCTREE)/,,$(CURDIR)),$<)
+ #echo $(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c
$(CC) $(AFLAGS) $(AFLAGS_$(@F)) $(AFLAGS_$(BCURDIR)) -o $@ $< -c
$(obj)%.o: %.c
+ $(call MESSAGE, [CC], $(subst $(SRCTREE)/,,$(CURDIR)),$<)
+ #echo $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(obj)%.i: %.c
+ $(call MESSAGE, [CPP],$(subst $(SRCTREE)/,,$(CURDIR)),$<)
+ #echo $(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(CPP) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c
$(obj)%.s: %.c
+ $(call MESSAGE, [CC], $(subst $(SRCTREE)/,,$(CURDIR)),$<)
+ #echo $(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S
$(CC) $(CFLAGS) $(CFLAGS_$(@F)) $(CFLAGS_$(BCURDIR)) -o $@ $< -c -S
#########################################################################

4
package/uboot-lantiq/patches/200-httpd.patch
View file

@ -4609,7 +4609,7 @@
+static void
+uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr)
+{
+ register struct arp_entry *tabptr;
+ register struct arp_entry *tabptr = 0;
+ /* Walk through the ARP mapping table and try to find an entry to
+ update. If none is found, the IP -> MAC address mapping is
+ inserted in the ARP table. */
@ -4801,7 +4801,7 @@
+void
+uip_arp_out(void)
+{
+ struct arp_entry *tabptr;
+ struct arp_entry *tabptr = 0;
+ /* Find the destination IP address in the ARP table and construct
+ the Ethernet header. If the destination IP addres isn't on the
+ local network, we use the default router's IP address instead.

5
package/uboot-lantiq/patches/300-arcadyan.patch
View file

@ -39,7 +39,7 @@
SRCS := $(COBJS:.o=.c)
--- a/Makefile
+++ b/Makefile
@@ -3414,6 +3414,37 @@
@@ -3414,6 +3414,40 @@
## MIPS32 ifxcpe
#########################################################################
@ -59,12 +59,15 @@
+ $(XECHO) "... with ramboot configuration" ; \
+ }
+ @if [ "$$(findstring flash,$$@)" ] ; then \
+ echo "#TEXT_BASE = 0xB0050000" >$(obj)board/arcadyan/config.tmp ; \
+ echo "#define CONFIG_BOOTSTRAP" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_USE_DDR_RAM_CFG_psc166" >>$(obj)include/config.h ; \
+ fi
+ @$(MKCONFIG) -a $$(word 1,$$(subst _, ,$$@)) mips mips arcadyan "" danube
+endef
+
+$(eval $(call arcadyan, arv3527P%config))
+$(eval $(call arcadyan, arv4520PW%config))
+$(eval $(call arcadyan, arv452CPW%config))
+$(eval $(call arcadyan, arv4525PW%config))

1687
package/uboot-lantiq/patches/400-lzma.patch Normal file
View file

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