mvebu: Add support for kernel 4.14
Add support for kernel 4.14 to the mvebu target. This also replaces the old sfp and phylink patches with new versions from Russell's clearfog-4.13 branch http://git.arm.linux.org.uk/cgit/linux-arm.git/log/?h=clearfog-4.13 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
parent
47106f55e0
commit
4ccad92229
29 changed files with 3893 additions and 0 deletions
486
target/linux/mvebu/config-4.14
Normal file
486
target/linux/mvebu/config-4.14
Normal file
|
@ -0,0 +1,486 @@
|
|||
CONFIG_AHCI_MVEBU=y
|
||||
CONFIG_ALIGNMENT_TRAP=y
|
||||
CONFIG_ARCH_CLOCKSOURCE_DATA=y
|
||||
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
|
||||
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
|
||||
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
|
||||
CONFIG_ARCH_HAS_SET_MEMORY=y
|
||||
CONFIG_ARCH_HAS_SG_CHAIN=y
|
||||
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
|
||||
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
|
||||
CONFIG_ARCH_HAS_TICK_BROADCAST=y
|
||||
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
|
||||
CONFIG_ARCH_MULTIPLATFORM=y
|
||||
# CONFIG_ARCH_MULTI_CPU_AUTO is not set
|
||||
CONFIG_ARCH_MULTI_V6_V7=y
|
||||
CONFIG_ARCH_MULTI_V7=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_ARCH_NR_GPIO=0
|
||||
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
|
||||
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
|
||||
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
|
||||
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
|
||||
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
|
||||
CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
|
||||
CONFIG_ARCH_SUPPORTS_UPROBES=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
|
||||
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
|
||||
# CONFIG_ARCH_WANTS_THP_SWAP is not set
|
||||
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
|
||||
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARMADA_370_CLK=y
|
||||
CONFIG_ARMADA_370_XP_IRQ=y
|
||||
CONFIG_ARMADA_370_XP_TIMER=y
|
||||
CONFIG_ARMADA_38X_CLK=y
|
||||
CONFIG_ARMADA_THERMAL=y
|
||||
CONFIG_ARMADA_XP_CLK=y
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
|
||||
CONFIG_ARM_CPU_SUSPEND=y
|
||||
CONFIG_ARM_CRYPTO=y
|
||||
CONFIG_ARM_ERRATA_720789=y
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_GLOBAL_TIMER=y
|
||||
CONFIG_ARM_HAS_SG_CHAIN=y
|
||||
CONFIG_ARM_HEAVY_MB=y
|
||||
CONFIG_ARM_L1_CACHE_SHIFT=6
|
||||
CONFIG_ARM_L1_CACHE_SHIFT_6=y
|
||||
# CONFIG_ARM_LPAE is not set
|
||||
CONFIG_ARM_MVEBU_V7_CPUIDLE=y
|
||||
CONFIG_ARM_PATCH_IDIV=y
|
||||
CONFIG_ARM_PATCH_PHYS_VIRT=y
|
||||
CONFIG_ARM_THUMB=y
|
||||
# CONFIG_ARM_THUMBEE is not set
|
||||
CONFIG_ARM_UNWIND=y
|
||||
CONFIG_ARM_VIRT_EXT=y
|
||||
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_ATAGS=y
|
||||
CONFIG_AUTO_ZRELADDR=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BLK_SCSI_REQUEST=y
|
||||
CONFIG_BOUNCE=y
|
||||
# CONFIG_CACHE_FEROCEON_L2 is not set
|
||||
CONFIG_CACHE_L2X0=y
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_CPU_32v6K=y
|
||||
CONFIG_CPU_32v7=y
|
||||
CONFIG_CPU_ABRT_EV7=y
|
||||
# CONFIG_CPU_BIG_ENDIAN is not set
|
||||
# CONFIG_CPU_BPREDICT_DISABLE is not set
|
||||
CONFIG_CPU_CACHE_V7=y
|
||||
CONFIG_CPU_CACHE_VIPT=y
|
||||
CONFIG_CPU_COPY_V6=y
|
||||
CONFIG_CPU_CP15=y
|
||||
CONFIG_CPU_CP15_MMU=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
CONFIG_CPU_FREQ_GOV_COMMON=y
|
||||
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
|
||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_HAS_ASID=y
|
||||
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
|
||||
# CONFIG_CPU_ICACHE_DISABLE is not set
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_CPU_IDLE_GOV_LADDER=y
|
||||
CONFIG_CPU_PABRT_V7=y
|
||||
CONFIG_CPU_PJ4B=y
|
||||
CONFIG_CPU_PM=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CPU_THUMB_CAPABLE=y
|
||||
CONFIG_CPU_TLB_V7=y
|
||||
CONFIG_CPU_V7=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_CRYPTO_ACOMP2=y
|
||||
CONFIG_CRYPTO_AEAD=y
|
||||
CONFIG_CRYPTO_AEAD2=y
|
||||
CONFIG_CRYPTO_AES_ARM=y
|
||||
CONFIG_CRYPTO_AES_ARM_BS=y
|
||||
# CONFIG_CRYPTO_AES_ARM_CE is not set
|
||||
# CONFIG_CRYPTO_CHACHA20_NEON is not set
|
||||
CONFIG_CRYPTO_CRC32=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
# CONFIG_CRYPTO_CRC32_ARM_CE is not set
|
||||
CONFIG_CRYPTO_CRYPTD=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
|
||||
# CONFIG_CRYPTO_GHASH_ARM_CE is not set
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_HASH2=y
|
||||
CONFIG_CRYPTO_HW=y
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_MANAGER2=y
|
||||
CONFIG_CRYPTO_NULL2=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_SHA1_ARM=y
|
||||
# CONFIG_CRYPTO_SHA1_ARM_CE is not set
|
||||
CONFIG_CRYPTO_SHA1_ARM_NEON=y
|
||||
CONFIG_CRYPTO_SHA256_ARM=y
|
||||
# CONFIG_CRYPTO_SHA2_ARM_CE is not set
|
||||
CONFIG_CRYPTO_SHA512_ARM=y
|
||||
CONFIG_CRYPTO_SIMD=y
|
||||
CONFIG_CRYPTO_WORKQUEUE=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_ALIGN_RODATA=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
|
||||
CONFIG_DEBUG_MVEBU_UART0=y
|
||||
# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
|
||||
# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
|
||||
CONFIG_DEBUG_UART_8250=y
|
||||
# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
|
||||
CONFIG_DEBUG_UART_8250_SHIFT=2
|
||||
# CONFIG_DEBUG_UART_8250_WORD is not set
|
||||
CONFIG_DEBUG_UART_PHYS=0xd0012000
|
||||
CONFIG_DEBUG_UART_VIRT=0xfec12000
|
||||
CONFIG_DEBUG_UNCOMPRESS=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_ENGINE_RAID=y
|
||||
# CONFIG_DMA_NOOP_OPS is not set
|
||||
CONFIG_DMA_OF=y
|
||||
# CONFIG_DMA_VIRT_OPS is not set
|
||||
# CONFIG_DRM_LIB_RANDOM is not set
|
||||
CONFIG_DTC=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_EDAC_ATOMIC_SCRUB=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EXPORTFS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXTCON=y
|
||||
# CONFIG_F2FS_CHECK_FS is not set
|
||||
CONFIG_F2FS_FS=y
|
||||
# CONFIG_F2FS_FS_SECURITY is not set
|
||||
CONFIG_F2FS_FS_XATTR=y
|
||||
CONFIG_F2FS_STAT_FS=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_FUTEX_PI=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IO=y
|
||||
CONFIG_GENERIC_IRQ_CHIP=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_MVEBU=y
|
||||
CONFIG_GPIO_PCA953X=y
|
||||
# CONFIG_GPIO_PCA953X_IRQ is not set
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_GRO_CELLS is not set
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
|
||||
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
|
||||
CONFIG_HAVE_ARCH_BITREVERSE=y
|
||||
CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
||||
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
||||
CONFIG_HAVE_ARM_SCU=y
|
||||
CONFIG_HAVE_ARM_SMCCC=y
|
||||
CONFIG_HAVE_ARM_TWD=y
|
||||
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
|
||||
CONFIG_HAVE_CC_STACKPROTECTOR=y
|
||||
CONFIG_HAVE_CLK=y
|
||||
CONFIG_HAVE_CLK_PREPARE=y
|
||||
CONFIG_HAVE_CONTEXT_TRACKING=y
|
||||
CONFIG_HAVE_C_RECORDMCOUNT=y
|
||||
CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
||||
CONFIG_HAVE_DMA_API_DEBUG=y
|
||||
CONFIG_HAVE_DMA_CONTIGUOUS=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
|
||||
CONFIG_HAVE_EBPF_JIT=y
|
||||
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
|
||||
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_HAVE_IDE=y
|
||||
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_HAVE_MEMBLOCK=y
|
||||
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
CONFIG_HAVE_OPTPROBES=y
|
||||
CONFIG_HAVE_PERF_EVENTS=y
|
||||
CONFIG_HAVE_PERF_REGS=y
|
||||
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
|
||||
CONFIG_HAVE_PROC_CPU=y
|
||||
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
|
||||
CONFIG_HAVE_SMP=y
|
||||
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
||||
CONFIG_HAVE_UID16=y
|
||||
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
||||
CONFIG_HIGHMEM=y
|
||||
# CONFIG_HIGHPTE is not set
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
CONFIG_HWBM=y
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_HZ_FIXED=0
|
||||
CONFIG_HZ_PERIODIC=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MV64XXX=y
|
||||
# CONFIG_I2C_PXA is not set
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_IOMMU_HELPER=y
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_DEBUG=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
# CONFIG_IWMMXT is not set
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PCA963X=y
|
||||
CONFIG_LEDS_TLC591XX=y
|
||||
CONFIG_LEDS_TRIGGER_DISK=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MACH_ARMADA_370=y
|
||||
# CONFIG_MACH_ARMADA_375 is not set
|
||||
CONFIG_MACH_ARMADA_38X=y
|
||||
# CONFIG_MACH_ARMADA_39X is not set
|
||||
CONFIG_MACH_ARMADA_XP=y
|
||||
# CONFIG_MACH_DOVE is not set
|
||||
CONFIG_MACH_MVEBU_ANY=y
|
||||
CONFIG_MACH_MVEBU_V7=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MANGLE_BOOTARGS=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_I2C=y
|
||||
CONFIG_MEMORY=y
|
||||
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
|
||||
CONFIG_MIGHT_HAVE_PCI=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_MVSDIO=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_PXAV3=y
|
||||
# CONFIG_MMC_TIFM_SD is not set
|
||||
CONFIG_MODULES_USE_ELF_REL=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND_PXA3xx=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
# CONFIG_MTD_UBI_FASTMAP is not set
|
||||
# CONFIG_MTD_UBI_GLUEBI is not set
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MULTI_IRQ_HANDLER=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_MVEBU_CLK_COMMON=y
|
||||
CONFIG_MVEBU_CLK_COREDIV=y
|
||||
CONFIG_MVEBU_CLK_CPU=y
|
||||
CONFIG_MVEBU_DEVBUS=y
|
||||
CONFIG_MVEBU_MBUS=y
|
||||
CONFIG_MVMDIO=y
|
||||
CONFIG_MVNETA=y
|
||||
CONFIG_MVNETA_BM=y
|
||||
CONFIG_MVNETA_BM_ENABLE=y
|
||||
CONFIG_MVPP2=y
|
||||
CONFIG_MVSW61XX_PHY=y
|
||||
CONFIG_MV_XOR=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NO_BOOTMEM=y
|
||||
CONFIG_NR_CPUS=4
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_ADDRESS_PCI=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_PCI=y
|
||||
CONFIG_OF_PCI_IRQ=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
CONFIG_OLD_SIGACTION=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
CONFIG_ORION_WATCHDOG=y
|
||||
CONFIG_OUTER_CACHE=y
|
||||
CONFIG_OUTER_CACHE_SYNC=y
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_OFFSET=0xC0000000
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCI_MVEBU=y
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PGTABLE_LEVELS=2
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_ARMADA_370=y
|
||||
CONFIG_PINCTRL_ARMADA_38X=y
|
||||
CONFIG_PINCTRL_ARMADA_XP=y
|
||||
CONFIG_PINCTRL_MVEBU=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PJ4B_ERRATA_4742=y
|
||||
# CONFIG_PL310_ERRATA_588369 is not set
|
||||
# CONFIG_PL310_ERRATA_727915 is not set
|
||||
# CONFIG_PL310_ERRATA_753970 is not set
|
||||
# CONFIG_PL310_ERRATA_769419 is not set
|
||||
CONFIG_PLAT_ORION=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=11
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_RCU_NEED_SEGCBLIST=y
|
||||
CONFIG_RCU_STALL_COMMON=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGMAP_SPI=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_ARMADA38X=y
|
||||
CONFIG_RTC_DRV_MV=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_MC146818_LIB=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
CONFIG_SATA_AHCI_PLATFORM=y
|
||||
CONFIG_SATA_MV=y
|
||||
# CONFIG_SCHED_INFO is not set
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SENSORS_PWM_FAN=y
|
||||
CONFIG_SENSORS_TMP421=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_MVEBU_CONSOLE=y
|
||||
CONFIG_SERIAL_MVEBU_UART=y
|
||||
CONFIG_SFP=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_ON_UP=y
|
||||
CONFIG_SOC_BUS=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
# CONFIG_SPI_ARMADA_3700 is not set
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_ORION=y
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRAM_EXEC=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_SWCONFIG=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SWP_EMULATE=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THIN_ARCHIVES=y
|
||||
# CONFIG_THUMB2_KERNEL is not set
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_ORION=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_MVEBU=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_VECTORS_BASE=0xffff0000
|
||||
CONFIG_VFP=y
|
||||
CONFIG_VFPv3=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
770
target/linux/mvebu/patches-4.14/002-add_powertables.patch
Normal file
770
target/linux/mvebu/patches-4.14/002-add_powertables.patch
Normal file
|
@ -0,0 +1,770 @@
|
|||
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
|
||||
@@ -237,11 +237,19 @@
|
||||
&pcie1 {
|
||||
/* Marvell 88W8864, 5GHz-only */
|
||||
status = "okay";
|
||||
+
|
||||
+ mwlwifi {
|
||||
+ marvell,2ghz = <0>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
/* Marvell 88W8864, 2GHz-only */
|
||||
status = "okay";
|
||||
+
|
||||
+ mwlwifi {
|
||||
+ marvell,5ghz = <0>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
|
||||
@@ -169,3 +169,205 @@
|
||||
reg = <0x280000 0x680000>; /* 6.5MiB */
|
||||
};
|
||||
};
|
||||
+
|
||||
+&pcie1 {
|
||||
+ mwlwifi {
|
||||
+ marvell,chainmask = <2 2>;
|
||||
+ marvell,powertable {
|
||||
+ AU =
|
||||
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
||||
+ <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
|
||||
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
|
||||
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
|
||||
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
|
||||
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
|
||||
+ CA =
|
||||
+ <36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
||||
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
||||
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
||||
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
||||
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
|
||||
+ CN =
|
||||
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
|
||||
+ ETSI =
|
||||
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
||||
+ <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
|
||||
+ FCC =
|
||||
+ <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
||||
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
||||
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
||||
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
||||
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2 {
|
||||
+ mwlwifi {
|
||||
+ marvell,chainmask = <2 2>;
|
||||
+ marvell,powertable {
|
||||
+ AU =
|
||||
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ CA =
|
||||
+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
|
||||
+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
||||
+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
||||
+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
||||
+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
||||
+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
||||
+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
||||
+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
||||
+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
||||
+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
||||
+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
|
||||
+ CN =
|
||||
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ ETSI =
|
||||
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ FCC =
|
||||
+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
|
||||
@@ -169,3 +169,205 @@
|
||||
reg = <0x280000 0x680000>; /* 6.5MiB */
|
||||
};
|
||||
};
|
||||
+
|
||||
+&pcie1 {
|
||||
+ mwlwifi {
|
||||
+ marvell,chainmask = <4 4>;
|
||||
+ marvell,powertable {
|
||||
+ AU =
|
||||
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
||||
+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
||||
+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
||||
+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
||||
+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
|
||||
+ CA =
|
||||
+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
|
||||
+ CN =
|
||||
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
|
||||
+ ETSI =
|
||||
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
|
||||
+ FCC =
|
||||
+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2 {
|
||||
+ mwlwifi {
|
||||
+ marvell,chainmask = <4 4>;
|
||||
+ marvell,powertable {
|
||||
+ AU =
|
||||
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ CA =
|
||||
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ CN =
|
||||
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ ETSI =
|
||||
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ FCC =
|
||||
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
|
||||
@@ -169,3 +169,205 @@
|
||||
reg = <0x280000 0x680000>; /* 6.5MiB */
|
||||
};
|
||||
};
|
||||
+
|
||||
+&pcie1 {
|
||||
+ mwlwifi {
|
||||
+ marvell,chainmask = <4 4>;
|
||||
+ marvell,powertable {
|
||||
+ AU =
|
||||
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
||||
+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
||||
+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
||||
+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
||||
+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
|
||||
+ CA =
|
||||
+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
|
||||
+ CN =
|
||||
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
|
||||
+ ETSI =
|
||||
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
||||
+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
|
||||
+ FCC =
|
||||
+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
||||
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
||||
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
||||
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2 {
|
||||
+ mwlwifi {
|
||||
+ marvell,chainmask = <4 4>;
|
||||
+ marvell,powertable {
|
||||
+ AU =
|
||||
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ CA =
|
||||
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ CN =
|
||||
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ ETSI =
|
||||
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ FCC =
|
||||
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
|
||||
@@ -184,6 +184,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&pcie1 {
|
||||
+ mwlwifi {
|
||||
+ marvell,chainmask = <4 4>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2 {
|
||||
+ mwlwifi {
|
||||
+ marvell,chainmask = <4 4>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&sdhci {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhci_pins>;
|
||||
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
@@ -376,12 +376,100 @@
|
||||
pcie@2,0 {
|
||||
/* Port 0, Lane 1 */
|
||||
status = "okay";
|
||||
+
|
||||
+ mwlwifi {
|
||||
+ marvell,5ghz = <0>;
|
||||
+ marvell,chainmask = <4 4>;
|
||||
+ marvell,powertable {
|
||||
+ FCC =
|
||||
+ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+
|
||||
+ ETSI =
|
||||
+ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
||||
+ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
/* Second mini-PCIe port */
|
||||
pcie@3,0 {
|
||||
/* Port 0, Lane 3 */
|
||||
status = "okay";
|
||||
+
|
||||
+ mwlwifi {
|
||||
+ marvell,2ghz = <0>;
|
||||
+ marvell,chainmask = <4 4>;
|
||||
+ marvell,powertable {
|
||||
+ FCC =
|
||||
+ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
||||
+ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
|
||||
+ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
|
||||
+ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
|
||||
+ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
|
||||
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
|
||||
+ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
|
||||
+
|
||||
+ ETSI =
|
||||
+ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
||||
+ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
40
target/linux/mvebu/patches-4.14/003-add_switch_nodes.patch
Normal file
40
target/linux/mvebu/patches-4.14/003-add_switch_nodes.patch
Normal file
|
@ -0,0 +1,40 @@
|
|||
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
@@ -361,6 +361,16 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ mvsw61xx {
|
||||
+ compatible = "marvell,88e6172";
|
||||
+ status = "okay";
|
||||
+ reg = <0x10>;
|
||||
+
|
||||
+ mii-bus = <&mdio>;
|
||||
+ cpu-port-0 = <5>;
|
||||
+ cpu-port-1 = <6>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&pciec {
|
||||
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
|
||||
@@ -113,6 +113,18 @@
|
||||
linux,default-trigger = "disk-activity";
|
||||
};
|
||||
};
|
||||
+
|
||||
+ mvsw61xx {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ compatible = "marvell,88e6176";
|
||||
+ status = "okay";
|
||||
+ reg = <0x10>;
|
||||
+
|
||||
+ mii-bus = <&mdio>;
|
||||
+ cpu-port-0 = <5>;
|
||||
+ cpu-port-1 = <6>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&ahci0 {
|
|
@ -0,0 +1,39 @@
|
|||
From 172230195068703b78ad5733a09492f5d6814c09 Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Tue, 28 Feb 2017 14:15:50 +0100
|
||||
Subject: [PATCH] ARM: dts: armada: Add default trigger for sata led
|
||||
|
||||
In others board we have the sata led set to function
|
||||
with the sata led trigger by default.
|
||||
This patch makes the same for these board that have sata
|
||||
led but get disabled by not associating it to any trigger.
|
||||
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Acked-by: Jason Cooper <jason@lakedaemon.net>
|
||||
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-385-linksys-caiman.dts | 1 +
|
||||
arch/arm/boot/dts/armada-385-linksys-cobra.dts | 1 +
|
||||
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 1 +
|
||||
3 files changed, 3 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
|
||||
@@ -100,6 +100,7 @@
|
||||
|
||||
sata {
|
||||
label = "caiman:white:sata";
|
||||
+ linux,default-trigger = "disk-activity";
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
|
||||
@@ -100,6 +100,7 @@
|
||||
|
||||
sata {
|
||||
label = "cobra:white:sata";
|
||||
+ linux,default-trigger = "disk-activity";
|
||||
};
|
||||
};
|
||||
|
60
target/linux/mvebu/patches-4.14/100-find_active_root.patch
Normal file
60
target/linux/mvebu/patches-4.14/100-find_active_root.patch
Normal file
|
@ -0,0 +1,60 @@
|
|||
The WRT1900AC among other Linksys routers uses a dual-firmware layout.
|
||||
Dynamically rename the active partition to "ubi".
|
||||
|
||||
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
|
||||
|
||||
--- a/drivers/mtd/ofpart.c
|
||||
+++ b/drivers/mtd/ofpart.c
|
||||
@@ -25,6 +25,8 @@ static bool node_has_compatible(struct d
|
||||
return of_get_property(pp, "compatible", NULL);
|
||||
}
|
||||
|
||||
+static int mangled_rootblock;
|
||||
+
|
||||
static int parse_ofpart_partitions(struct mtd_info *master,
|
||||
const struct mtd_partition **pparts,
|
||||
struct mtd_part_parser_data *data)
|
||||
@@ -33,6 +35,7 @@ static int parse_ofpart_partitions(struc
|
||||
struct device_node *mtd_node;
|
||||
struct device_node *ofpart_node;
|
||||
const char *partname;
|
||||
+ const char *owrtpart = "ubi";
|
||||
struct device_node *pp;
|
||||
int nr_parts, i, ret = 0;
|
||||
bool dedicated = true;
|
||||
@@ -110,9 +113,13 @@ static int parse_ofpart_partitions(struc
|
||||
parts[i].size = of_read_number(reg + a_cells, s_cells);
|
||||
parts[i].of_node = pp;
|
||||
|
||||
- partname = of_get_property(pp, "label", &len);
|
||||
- if (!partname)
|
||||
- partname = of_get_property(pp, "name", &len);
|
||||
+ if (mangled_rootblock && (i == mangled_rootblock)) {
|
||||
+ partname = owrtpart;
|
||||
+ } else {
|
||||
+ partname = of_get_property(pp, "label", &len);
|
||||
+ if (!partname)
|
||||
+ partname = of_get_property(pp, "name", &len);
|
||||
+ }
|
||||
parts[i].name = partname;
|
||||
|
||||
if (of_get_property(pp, "read-only", &len))
|
||||
@@ -219,6 +226,18 @@ static int __init ofpart_parser_init(voi
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int __init active_root(char *str)
|
||||
+{
|
||||
+ get_option(&str, &mangled_rootblock);
|
||||
+
|
||||
+ if (!mangled_rootblock)
|
||||
+ return 1;
|
||||
+
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
+__setup("mangled_rootblock=", active_root);
|
||||
+
|
||||
static void __exit ofpart_parser_exit(void)
|
||||
{
|
||||
deregister_mtd_parser(&ofpart_parser);
|
15
target/linux/mvebu/patches-4.14/102-revert_i2c_delay.patch
Normal file
15
target/linux/mvebu/patches-4.14/102-revert_i2c_delay.patch
Normal file
|
@ -0,0 +1,15 @@
|
|||
--- a/arch/arm/boot/dts/armada-xp.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-xp.dtsi
|
||||
@@ -274,12 +274,10 @@
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x100>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x100>;
|
||||
};
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
Remove a BUG() call that would crash on a race condition that should
|
||||
otherwise be harmless.
|
||||
|
||||
--- a/drivers/mtd/nand/pxa3xx_nand.c
|
||||
+++ b/drivers/mtd/nand/pxa3xx_nand.c
|
||||
@@ -727,7 +727,6 @@ static void handle_data_pio(struct pxa3x
|
||||
default:
|
||||
dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
|
||||
info->state);
|
||||
- BUG();
|
||||
}
|
||||
|
||||
/* Update buffer pointers for multi-page read/write */
|
|
@ -0,0 +1,10 @@
|
|||
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
@@ -200,7 +200,6 @@
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
- marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
nand-ecc-strength = <4>;
|
|
@ -0,0 +1,69 @@
|
|||
Revert "mtd: pxa3xx-nand: handle PIO in threaded interrupt"
|
||||
|
||||
This reverts commit 24542257a3b987025d4b998ec2d15e556c98ad3f
|
||||
This upstream change has been causing spurious timeouts on accesses
|
||||
to the NAND flash if something else on the system is causing
|
||||
significant latency.
|
||||
|
||||
Nothing guarantees that the thread will run in time, so the
|
||||
usual timeout is unreliable.
|
||||
|
||||
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
||||
|
||||
--- a/drivers/mtd/nand/pxa3xx_nand.c
|
||||
+++ b/drivers/mtd/nand/pxa3xx_nand.c
|
||||
@@ -791,24 +791,11 @@ static void start_data_dma(struct pxa3xx
|
||||
__func__, direction, info->dma_cookie, info->sg.length);
|
||||
}
|
||||
|
||||
-static irqreturn_t pxa3xx_nand_irq_thread(int irq, void *data)
|
||||
-{
|
||||
- struct pxa3xx_nand_info *info = data;
|
||||
-
|
||||
- handle_data_pio(info);
|
||||
-
|
||||
- info->state = STATE_CMD_DONE;
|
||||
- nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
|
||||
-
|
||||
- return IRQ_HANDLED;
|
||||
-}
|
||||
-
|
||||
static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
|
||||
{
|
||||
struct pxa3xx_nand_info *info = devid;
|
||||
unsigned int status, is_completed = 0, is_ready = 0;
|
||||
unsigned int ready, cmd_done;
|
||||
- irqreturn_t ret = IRQ_HANDLED;
|
||||
|
||||
if (info->cs == 0) {
|
||||
ready = NDSR_FLASH_RDY;
|
||||
@@ -850,8 +837,7 @@ static irqreturn_t pxa3xx_nand_irq(int i
|
||||
} else {
|
||||
info->state = (status & NDSR_RDDREQ) ?
|
||||
STATE_PIO_READING : STATE_PIO_WRITING;
|
||||
- ret = IRQ_WAKE_THREAD;
|
||||
- goto NORMAL_IRQ_EXIT;
|
||||
+ handle_data_pio(info);
|
||||
}
|
||||
}
|
||||
if (status & cmd_done) {
|
||||
@@ -896,7 +882,7 @@ static irqreturn_t pxa3xx_nand_irq(int i
|
||||
if (is_ready)
|
||||
complete(&info->dev_ready);
|
||||
NORMAL_IRQ_EXIT:
|
||||
- return ret;
|
||||
+ return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static inline int is_buf_blank(uint8_t *buf, size_t len)
|
||||
@@ -1865,9 +1851,7 @@ static int alloc_nand_resource(struct pl
|
||||
/* initialize all interrupts to be disabled */
|
||||
disable_int(info, NDSR_MASK);
|
||||
|
||||
- ret = request_threaded_irq(irq, pxa3xx_nand_irq,
|
||||
- pxa3xx_nand_irq_thread, IRQF_ONESHOT,
|
||||
- pdev->name, info);
|
||||
+ ret = request_irq(irq, pxa3xx_nand_irq, 0, pdev->name, info);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
|
||||
goto fail_free_buf;
|
|
@ -0,0 +1,19 @@
|
|||
--- a/arch/arm/boot/dts/armada-388-rd.dts
|
||||
+++ b/arch/arm/boot/dts/armada-388-rd.dts
|
||||
@@ -140,6 +140,16 @@
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "uboot";
|
||||
+ reg = <0 0x400000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@1 {
|
||||
+ label = "firmware";
|
||||
+ reg = <0x400000 0xc00000>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
Date: Tue, 13 Jan 2015 11:14:09 +0100
|
||||
Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
|
||||
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++
|
||||
1 file changed, 15 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||
@@ -181,19 +181,19 @@
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
- label = "U-Boot";
|
||||
+ label = "u-boot";
|
||||
reg = <0x00000000 0x00800000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
- label = "uImage";
|
||||
+ label = "kernel";
|
||||
reg = <0x00800000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@c00000 {
|
||||
- label = "Root";
|
||||
+ label = "ubi";
|
||||
reg = <0x00c00000 0x3f400000>;
|
||||
};
|
||||
};
|
|
@ -0,0 +1,21 @@
|
|||
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||
@@ -129,6 +129,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ mvsw61xx {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ compatible = "marvell,88e6176";
|
||||
+ status = "okay";
|
||||
+ reg = <0x4>;
|
||||
+ is-indirect;
|
||||
+
|
||||
+ mii-bus = <&mdio>;
|
||||
+ cpu-port-0 = <5>;
|
||||
+ };
|
||||
+
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&rear_button_pins>;
|
|
@ -0,0 +1,35 @@
|
|||
The hardware queue scheduling is apparently configured with fixed
|
||||
priorities, which creates a nasty fairness issue where traffic from one
|
||||
CPU can starve traffic from all other CPUs.
|
||||
|
||||
Work around this issue by forcing all tx packets to go through one CPU,
|
||||
until this issue is fixed properly.
|
||||
|
||||
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
||||
---
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -3961,6 +3961,15 @@ static int mvneta_ethtool_set_wol(struct
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
|
||||
+ void *accel_priv,
|
||||
+ select_queue_fallback_t fallback)
|
||||
+{
|
||||
+ /* XXX: hardware queue scheduling is broken,
|
||||
+ * use only one queue until it is fixed */
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static const struct net_device_ops mvneta_netdev_ops = {
|
||||
.ndo_open = mvneta_open,
|
||||
.ndo_stop = mvneta_stop,
|
||||
@@ -3971,6 +3980,7 @@ static const struct net_device_ops mvnet
|
||||
.ndo_fix_features = mvneta_fix_features,
|
||||
.ndo_get_stats64 = mvneta_get_stats64,
|
||||
.ndo_do_ioctl = mvneta_ioctl,
|
||||
+ .ndo_select_queue = mvneta_select_queue,
|
||||
};
|
||||
|
||||
static const struct ethtool_ops mvneta_eth_tool_ops = {
|
|
@ -0,0 +1,40 @@
|
|||
From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Sat, 3 Oct 2015 09:13:05 +0100
|
||||
Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states
|
||||
|
||||
The cpuidle ->enter method expects the return value to be the sleep
|
||||
state we entered. Returning negative numbers or other codes is not
|
||||
permissible since coupled CPU idle was merged.
|
||||
|
||||
At least some of the mvebu_v7_cpu_suspend() implementations return the
|
||||
value from cpu_suspend(), which returns zero if the CPU vectors back
|
||||
into the kernel via cpu_resume() (the success case), or the non-zero
|
||||
return value of the suspend actor, or one (failure cases).
|
||||
|
||||
We do not want to be returning the failure case value back to CPU idle
|
||||
as that indicates that we successfully entered one of the deeper idle
|
||||
states. Always return zero instead, indicating that we slept for the
|
||||
shortest amount of time.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
---
|
||||
drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
|
||||
1 file changed, 5 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
|
||||
+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
|
||||
@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
|
||||
ret = mvebu_v7_cpu_suspend(deepidle);
|
||||
cpu_pm_exit();
|
||||
|
||||
+ /*
|
||||
+ * If we failed to enter the desired state, indicate that we
|
||||
+ * slept lightly.
|
||||
+ */
|
||||
if (ret)
|
||||
- return ret;
|
||||
+ return 0;
|
||||
|
||||
return index;
|
||||
}
|
|
@ -0,0 +1,60 @@
|
|||
From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Sat, 9 Jul 2016 10:58:16 +0100
|
||||
Subject: pci: mvebu: time out reset on link up
|
||||
|
||||
If the port reports that the link is up while we are resetting, there's
|
||||
little point in waiting for the full duration.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
drivers/pci/host/pci-mvebu.c | 20 ++++++++++++++------
|
||||
1 file changed, 14 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/pci/host/pci-mvebu.c
|
||||
+++ b/drivers/pci/host/pci-mvebu.c
|
||||
@@ -1167,6 +1167,7 @@ static int mvebu_pcie_powerup(struct mve
|
||||
|
||||
if (port->reset_gpio) {
|
||||
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
|
||||
+ unsigned int i;
|
||||
|
||||
of_property_read_u32(port->dn, "reset-delay-us",
|
||||
&reset_udelay);
|
||||
@@ -1174,7 +1175,13 @@ static int mvebu_pcie_powerup(struct mve
|
||||
udelay(100);
|
||||
|
||||
gpiod_set_value_cansleep(port->reset_gpio, 0);
|
||||
- msleep(reset_udelay / 1000);
|
||||
+ for (i = 0; i < reset_udelay; i += 1000) {
|
||||
+ if (mvebu_pcie_link_up(port))
|
||||
+ break;
|
||||
+ msleep(1);
|
||||
+ }
|
||||
+
|
||||
+ printk("%s: reset completed in %dus\n", port->name, i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
@@ -1261,15 +1268,16 @@ static int mvebu_pcie_probe(struct platf
|
||||
if (!child)
|
||||
continue;
|
||||
|
||||
- ret = mvebu_pcie_powerup(port);
|
||||
- if (ret < 0)
|
||||
- continue;
|
||||
-
|
||||
port->base = mvebu_pcie_map_registers(pdev, child, port);
|
||||
if (IS_ERR(port->base)) {
|
||||
dev_err(dev, "%s: cannot map registers\n", port->name);
|
||||
port->base = NULL;
|
||||
- mvebu_pcie_powerdown(port);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ ret = mvebu_pcie_powerup(port);
|
||||
+ if (ret < 0) {
|
||||
+ port->base = NULL;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -0,0 +1,290 @@
|
|||
From e76632d118659347d9261a4470d9f60bfbe0044c Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Sun, 13 Sep 2015 01:06:31 +0100
|
||||
Subject: sfp: display SFP module information
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
---
|
||||
drivers/net/phy/sfp.c | 254 +++++++++++++++++++++++++++++++++++++++++++++++++-
|
||||
1 file changed, 253 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/net/phy/sfp.c
|
||||
+++ b/drivers/net/phy/sfp.c
|
||||
@@ -247,6 +247,184 @@ static unsigned int sfp_check(void *buf,
|
||||
return check;
|
||||
}
|
||||
|
||||
+static const char *sfp_link_len(char *buf, size_t size, unsigned int length,
|
||||
+ unsigned int multiplier)
|
||||
+{
|
||||
+ if (length == 0)
|
||||
+ return "unsupported/unspecified";
|
||||
+
|
||||
+ if (length == 255) {
|
||||
+ *buf++ = '>';
|
||||
+ size -= 1;
|
||||
+ length -= 1;
|
||||
+ }
|
||||
+
|
||||
+ length *= multiplier;
|
||||
+
|
||||
+ if (length >= 1000)
|
||||
+ snprintf(buf, size, "%u.%0*ukm",
|
||||
+ length / 1000,
|
||||
+ multiplier > 100 ? 1 :
|
||||
+ multiplier > 10 ? 2 : 3,
|
||||
+ length % 1000);
|
||||
+ else
|
||||
+ snprintf(buf, size, "%um", length);
|
||||
+
|
||||
+ return buf;
|
||||
+}
|
||||
+
|
||||
+struct bitfield {
|
||||
+ unsigned int mask;
|
||||
+ unsigned int val;
|
||||
+ const char *str;
|
||||
+};
|
||||
+
|
||||
+static const struct bitfield sfp_options[] = {
|
||||
+ {
|
||||
+ .mask = SFP_OPTIONS_HIGH_POWER_LEVEL,
|
||||
+ .val = SFP_OPTIONS_HIGH_POWER_LEVEL,
|
||||
+ .str = "hpl",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_PAGING_A2,
|
||||
+ .val = SFP_OPTIONS_PAGING_A2,
|
||||
+ .str = "paginga2",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_RETIMER,
|
||||
+ .val = SFP_OPTIONS_RETIMER,
|
||||
+ .str = "retimer",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_COOLED_XCVR,
|
||||
+ .val = SFP_OPTIONS_COOLED_XCVR,
|
||||
+ .str = "cooled",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_POWER_DECL,
|
||||
+ .val = SFP_OPTIONS_POWER_DECL,
|
||||
+ .str = "powerdecl",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_RX_LINEAR_OUT,
|
||||
+ .val = SFP_OPTIONS_RX_LINEAR_OUT,
|
||||
+ .str = "rxlinear",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_RX_DECISION_THRESH,
|
||||
+ .val = SFP_OPTIONS_RX_DECISION_THRESH,
|
||||
+ .str = "rxthresh",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_TUNABLE_TX,
|
||||
+ .val = SFP_OPTIONS_TUNABLE_TX,
|
||||
+ .str = "tunabletx",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_RATE_SELECT,
|
||||
+ .val = SFP_OPTIONS_RATE_SELECT,
|
||||
+ .str = "ratesel",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_TX_DISABLE,
|
||||
+ .val = SFP_OPTIONS_TX_DISABLE,
|
||||
+ .str = "txdisable",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_TX_FAULT,
|
||||
+ .val = SFP_OPTIONS_TX_FAULT,
|
||||
+ .str = "txfault",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_LOS_INVERTED,
|
||||
+ .val = SFP_OPTIONS_LOS_INVERTED,
|
||||
+ .str = "los-",
|
||||
+ }, {
|
||||
+ .mask = SFP_OPTIONS_LOS_NORMAL,
|
||||
+ .val = SFP_OPTIONS_LOS_NORMAL,
|
||||
+ .str = "los+",
|
||||
+ }, { }
|
||||
+};
|
||||
+
|
||||
+static const struct bitfield diagmon[] = {
|
||||
+ {
|
||||
+ .mask = SFP_DIAGMON_DDM,
|
||||
+ .val = SFP_DIAGMON_DDM,
|
||||
+ .str = "ddm",
|
||||
+ }, {
|
||||
+ .mask = SFP_DIAGMON_INT_CAL,
|
||||
+ .val = SFP_DIAGMON_INT_CAL,
|
||||
+ .str = "intcal",
|
||||
+ }, {
|
||||
+ .mask = SFP_DIAGMON_EXT_CAL,
|
||||
+ .val = SFP_DIAGMON_EXT_CAL,
|
||||
+ .str = "extcal",
|
||||
+ }, {
|
||||
+ .mask = SFP_DIAGMON_RXPWR_AVG,
|
||||
+ .val = SFP_DIAGMON_RXPWR_AVG,
|
||||
+ .str = "rxpwravg",
|
||||
+ }, { }
|
||||
+};
|
||||
+
|
||||
+static const char *sfp_bitfield(char *out, size_t outsz, const struct bitfield *bits, unsigned int val)
|
||||
+{
|
||||
+ char *p = out;
|
||||
+ int n;
|
||||
+
|
||||
+ *p = '\0';
|
||||
+ while (bits->mask) {
|
||||
+ if ((val & bits->mask) == bits->val) {
|
||||
+ n = snprintf(p, outsz, "%s%s",
|
||||
+ out != p ? ", " : "",
|
||||
+ bits->str);
|
||||
+ if (n == outsz)
|
||||
+ break;
|
||||
+ p += n;
|
||||
+ outsz -= n;
|
||||
+ }
|
||||
+ bits++;
|
||||
+ }
|
||||
+
|
||||
+ return out;
|
||||
+}
|
||||
+
|
||||
+static const char *sfp_connector(unsigned int connector)
|
||||
+{
|
||||
+ switch (connector) {
|
||||
+ case SFP_CONNECTOR_UNSPEC:
|
||||
+ return "unknown/unspecified";
|
||||
+ case SFP_CONNECTOR_SC:
|
||||
+ return "SC";
|
||||
+ case SFP_CONNECTOR_FIBERJACK:
|
||||
+ return "Fiberjack";
|
||||
+ case SFP_CONNECTOR_LC:
|
||||
+ return "LC";
|
||||
+ case SFP_CONNECTOR_MT_RJ:
|
||||
+ return "MT-RJ";
|
||||
+ case SFP_CONNECTOR_MU:
|
||||
+ return "MU";
|
||||
+ case SFP_CONNECTOR_SG:
|
||||
+ return "SG";
|
||||
+ case SFP_CONNECTOR_OPTICAL_PIGTAIL:
|
||||
+ return "Optical pigtail";
|
||||
+ case SFP_CONNECTOR_HSSDC_II:
|
||||
+ return "HSSDC II";
|
||||
+ case SFP_CONNECTOR_COPPER_PIGTAIL:
|
||||
+ return "Copper pigtail";
|
||||
+ default:
|
||||
+ return "unknown";
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static const char *sfp_encoding(unsigned int encoding)
|
||||
+{
|
||||
+ switch (encoding) {
|
||||
+ case SFP_ENCODING_UNSPEC:
|
||||
+ return "unspecified";
|
||||
+ case SFP_ENCODING_8472_64B66B:
|
||||
+ return "64b66b";
|
||||
+ case SFP_ENCODING_8B10B:
|
||||
+ return "8b10b";
|
||||
+ case SFP_ENCODING_4B5B:
|
||||
+ return "4b5b";
|
||||
+ case SFP_ENCODING_NRZ:
|
||||
+ return "NRZ";
|
||||
+ case SFP_ENCODING_8472_MANCHESTER:
|
||||
+ return "MANCHESTER";
|
||||
+ default:
|
||||
+ return "unknown";
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
/* Helpers */
|
||||
static void sfp_module_tx_disable(struct sfp *sfp)
|
||||
{
|
||||
@@ -415,6 +593,7 @@ static int sfp_sm_mod_probe(struct sfp *
|
||||
char sn[17];
|
||||
char date[9];
|
||||
char rev[5];
|
||||
+ char options[80];
|
||||
u8 check;
|
||||
int err;
|
||||
|
||||
@@ -458,10 +637,83 @@ static int sfp_sm_mod_probe(struct sfp *
|
||||
rev[4] = '\0';
|
||||
memcpy(sn, sfp->id.ext.vendor_sn, 16);
|
||||
sn[16] = '\0';
|
||||
- memcpy(date, sfp->id.ext.datecode, 8);
|
||||
+ date[0] = sfp->id.ext.datecode[4];
|
||||
+ date[1] = sfp->id.ext.datecode[5];
|
||||
+ date[2] = '-';
|
||||
+ date[3] = sfp->id.ext.datecode[2];
|
||||
+ date[4] = sfp->id.ext.datecode[3];
|
||||
+ date[5] = '-';
|
||||
+ date[6] = sfp->id.ext.datecode[0];
|
||||
+ date[7] = sfp->id.ext.datecode[1];
|
||||
date[8] = '\0';
|
||||
|
||||
dev_info(sfp->dev, "module %s %s rev %s sn %s dc %s\n", vendor, part, rev, sn, date);
|
||||
+ dev_info(sfp->dev, " %s connector, encoding %s, nominal bitrate %u.%uGbps +%u%% -%u%%\n",
|
||||
+ sfp_connector(sfp->id.base.connector),
|
||||
+ sfp_encoding(sfp->id.base.encoding),
|
||||
+ sfp->id.base.br_nominal / 10,
|
||||
+ sfp->id.base.br_nominal % 10,
|
||||
+ sfp->id.ext.br_max, sfp->id.ext.br_min);
|
||||
+ dev_info(sfp->dev, " 1000BaseSX%c 1000BaseLX%c 1000BaseCX%c 1000BaseT%c 100BaseTLX%c 1000BaseFX%c BaseBX10%c BasePX%c\n",
|
||||
+ sfp->id.base.e1000_base_sx ? '+' : '-',
|
||||
+ sfp->id.base.e1000_base_lx ? '+' : '-',
|
||||
+ sfp->id.base.e1000_base_cx ? '+' : '-',
|
||||
+ sfp->id.base.e1000_base_t ? '+' : '-',
|
||||
+ sfp->id.base.e100_base_lx ? '+' : '-',
|
||||
+ sfp->id.base.e100_base_fx ? '+' : '-',
|
||||
+ sfp->id.base.e_base_bx10 ? '+' : '-',
|
||||
+ sfp->id.base.e_base_px ? '+' : '-');
|
||||
+ dev_info(sfp->dev, " 10GBaseSR%c 10GBaseLR%c 10GBaseLRM%c 10GBaseER%c\n",
|
||||
+ sfp->id.base.e10g_base_sr ? '+' : '-',
|
||||
+ sfp->id.base.e10g_base_lr ? '+' : '-',
|
||||
+ sfp->id.base.e10g_base_lrm ? '+' : '-',
|
||||
+ sfp->id.base.e10g_base_er ? '+' : '-');
|
||||
+
|
||||
+ if (!sfp->id.base.sfp_ct_passive && !sfp->id.base.sfp_ct_active &&
|
||||
+ !sfp->id.base.e1000_base_t) {
|
||||
+ char len_9um[16], len_om[16];
|
||||
+
|
||||
+ dev_info(sfp->dev, " Wavelength %unm, fiber lengths:\n",
|
||||
+ be16_to_cpup(&sfp->id.base.optical_wavelength));
|
||||
+
|
||||
+ if (sfp->id.base.link_len[0] == 255)
|
||||
+ strcpy(len_9um, ">254km");
|
||||
+ else if (sfp->id.base.link_len[1] && sfp->id.base.link_len[1] != 255)
|
||||
+ sprintf(len_9um, "%um",
|
||||
+ sfp->id.base.link_len[1] * 100);
|
||||
+ else if (sfp->id.base.link_len[0])
|
||||
+ sprintf(len_9um, "%ukm", sfp->id.base.link_len[0]);
|
||||
+ else if (sfp->id.base.link_len[1] == 255)
|
||||
+ strcpy(len_9um, ">25.4km");
|
||||
+ else
|
||||
+ strcpy(len_9um, "unsupported");
|
||||
+
|
||||
+ dev_info(sfp->dev, " 9µm SM : %s\n", len_9um);
|
||||
+ dev_info(sfp->dev, " 62.5µm MM OM1: %s\n",
|
||||
+ sfp_link_len(len_om, sizeof(len_om),
|
||||
+ sfp->id.base.link_len[3], 10));
|
||||
+ dev_info(sfp->dev, " 50µm MM OM2: %s\n",
|
||||
+ sfp_link_len(len_om, sizeof(len_om),
|
||||
+ sfp->id.base.link_len[2], 10));
|
||||
+ dev_info(sfp->dev, " 50µm MM OM3: %s\n",
|
||||
+ sfp_link_len(len_om, sizeof(len_om),
|
||||
+ sfp->id.base.link_len[5], 10));
|
||||
+ dev_info(sfp->dev, " 50µm MM OM4: %s\n",
|
||||
+ sfp_link_len(len_om, sizeof(len_om),
|
||||
+ sfp->id.base.link_len[4], 10));
|
||||
+ } else {
|
||||
+ char len[16];
|
||||
+ dev_info(sfp->dev, " Copper length: %s\n",
|
||||
+ sfp_link_len(len, sizeof(len),
|
||||
+ sfp->id.base.link_len[4], 1));
|
||||
+ }
|
||||
+
|
||||
+ dev_info(sfp->dev, " Options: %s\n",
|
||||
+ sfp_bitfield(options, sizeof(options), sfp_options,
|
||||
+ be16_to_cpu(sfp->id.ext.options)));
|
||||
+ dev_info(sfp->dev, " Diagnostics: %s\n",
|
||||
+ sfp_bitfield(options, sizeof(options), diagmon,
|
||||
+ sfp->id.ext.diagmon));
|
||||
|
||||
/* We only support SFP modules, not the legacy GBIC modules. */
|
||||
if (sfp->id.base.phys_id != SFP_PHYS_ID_SFP ||
|
|
@ -0,0 +1,979 @@
|
|||
From 36f29e6cf8071fed3854d9825217ed2a3c83b990 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Wed, 16 Sep 2015 21:27:10 +0100
|
||||
Subject: net: mvneta: convert to phylink
|
||||
|
||||
Convert mvneta to use phylink, which models the MAC to PHY link in
|
||||
a generic, reusable form.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
|
||||
- remove unused sync status
|
||||
---
|
||||
drivers/net/ethernet/marvell/Kconfig | 2 +-
|
||||
drivers/net/ethernet/marvell/mvneta.c | 594 ++++++++++++++++++++--------------
|
||||
2 files changed, 349 insertions(+), 247 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/marvell/Kconfig
|
||||
+++ b/drivers/net/ethernet/marvell/Kconfig
|
||||
@@ -60,7 +60,7 @@ config MVNETA
|
||||
depends on ARCH_MVEBU || COMPILE_TEST
|
||||
depends on HAS_DMA
|
||||
select MVMDIO
|
||||
- select FIXED_PHY
|
||||
+ select PHYLINK
|
||||
---help---
|
||||
This driver supports the network interface units in the
|
||||
Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -28,7 +28,7 @@
|
||||
#include <linux/of_mdio.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <linux/phy.h>
|
||||
-#include <linux/phy_fixed.h>
|
||||
+#include <linux/phylink.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <net/hwbm.h>
|
||||
@@ -189,6 +189,7 @@
|
||||
#define MVNETA_GMAC_CTRL_0 0x2c00
|
||||
#define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
|
||||
#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
|
||||
+#define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
|
||||
#define MVNETA_GMAC0_PORT_ENABLE BIT(0)
|
||||
#define MVNETA_GMAC_CTRL_2 0x2c08
|
||||
#define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
|
||||
@@ -204,13 +205,19 @@
|
||||
#define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
|
||||
#define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
|
||||
#define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
|
||||
+#define MVNETA_GMAC_AN_COMPLETE BIT(11)
|
||||
+#define MVNETA_GMAC_SYNC_OK BIT(14)
|
||||
#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
|
||||
#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
|
||||
#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
|
||||
#define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
|
||||
+#define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
|
||||
+#define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
|
||||
#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
|
||||
#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
|
||||
#define MVNETA_GMAC_AN_SPEED_EN BIT(7)
|
||||
+#define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
|
||||
+#define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
|
||||
#define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
|
||||
#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
|
||||
#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
|
||||
@@ -237,6 +244,12 @@
|
||||
#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
|
||||
#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
|
||||
|
||||
+#define MVNETA_LPI_CTRL_0 0x2cc0
|
||||
+#define MVNETA_LPI_CTRL_1 0x2cc4
|
||||
+#define MVNETA_LPI_REQUEST_ENABLE BIT(0)
|
||||
+#define MVNETA_LPI_CTRL_2 0x2cc8
|
||||
+#define MVNETA_LPI_STATUS 0x2ccc
|
||||
+
|
||||
#define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
|
||||
|
||||
/* Descriptor ring Macros */
|
||||
@@ -313,6 +326,11 @@
|
||||
#define MVNETA_RX_GET_BM_POOL_ID(rxd) \
|
||||
(((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
|
||||
|
||||
+enum {
|
||||
+ ETHTOOL_STAT_EEE_WAKEUP,
|
||||
+ ETHTOOL_MAX_STATS,
|
||||
+};
|
||||
+
|
||||
struct mvneta_statistic {
|
||||
unsigned short offset;
|
||||
unsigned short type;
|
||||
@@ -321,6 +339,7 @@ struct mvneta_statistic {
|
||||
|
||||
#define T_REG_32 32
|
||||
#define T_REG_64 64
|
||||
+#define T_SW 1
|
||||
|
||||
static const struct mvneta_statistic mvneta_statistics[] = {
|
||||
{ 0x3000, T_REG_64, "good_octets_received", },
|
||||
@@ -355,6 +374,7 @@ static const struct mvneta_statistic mvn
|
||||
{ 0x304c, T_REG_32, "broadcast_frames_sent", },
|
||||
{ 0x3054, T_REG_32, "fc_sent", },
|
||||
{ 0x300c, T_REG_32, "internal_mac_transmit_err", },
|
||||
+ { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
|
||||
};
|
||||
|
||||
struct mvneta_pcpu_stats {
|
||||
@@ -407,20 +427,19 @@ struct mvneta_port {
|
||||
u16 tx_ring_size;
|
||||
u16 rx_ring_size;
|
||||
|
||||
- struct mii_bus *mii_bus;
|
||||
- phy_interface_t phy_interface;
|
||||
- struct device_node *phy_node;
|
||||
- unsigned int link;
|
||||
- unsigned int duplex;
|
||||
- unsigned int speed;
|
||||
+ struct device_node *dn;
|
||||
unsigned int tx_csum_limit;
|
||||
- unsigned int use_inband_status:1;
|
||||
+ struct phylink *phylink;
|
||||
|
||||
struct mvneta_bm *bm_priv;
|
||||
struct mvneta_bm_pool *pool_long;
|
||||
struct mvneta_bm_pool *pool_short;
|
||||
int bm_win_id;
|
||||
|
||||
+ bool eee_enabled;
|
||||
+ bool eee_active;
|
||||
+ bool tx_lpi_enabled;
|
||||
+
|
||||
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
|
||||
|
||||
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
|
||||
@@ -1214,10 +1233,6 @@ static void mvneta_port_disable(struct m
|
||||
val &= ~MVNETA_GMAC0_PORT_ENABLE;
|
||||
mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
|
||||
|
||||
- pp->link = 0;
|
||||
- pp->duplex = -1;
|
||||
- pp->speed = 0;
|
||||
-
|
||||
udelay(200);
|
||||
}
|
||||
|
||||
@@ -1277,44 +1292,6 @@ static void mvneta_set_other_mcast_table
|
||||
mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
|
||||
}
|
||||
|
||||
-static void mvneta_set_autoneg(struct mvneta_port *pp, int enable)
|
||||
-{
|
||||
- u32 val;
|
||||
-
|
||||
- if (enable) {
|
||||
- val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
|
||||
- val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
|
||||
- MVNETA_GMAC_FORCE_LINK_DOWN |
|
||||
- MVNETA_GMAC_AN_FLOW_CTRL_EN);
|
||||
- val |= MVNETA_GMAC_INBAND_AN_ENABLE |
|
||||
- MVNETA_GMAC_AN_SPEED_EN |
|
||||
- MVNETA_GMAC_AN_DUPLEX_EN;
|
||||
- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
|
||||
-
|
||||
- val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
|
||||
- val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
|
||||
- mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
|
||||
-
|
||||
- val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
|
||||
- val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
|
||||
- mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
|
||||
- } else {
|
||||
- val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
|
||||
- val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
|
||||
- MVNETA_GMAC_AN_SPEED_EN |
|
||||
- MVNETA_GMAC_AN_DUPLEX_EN);
|
||||
- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
|
||||
-
|
||||
- val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
|
||||
- val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
|
||||
- mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
|
||||
-
|
||||
- val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
|
||||
- val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
|
||||
- mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
|
||||
- }
|
||||
-}
|
||||
-
|
||||
static void mvneta_percpu_unmask_interrupt(void *arg)
|
||||
{
|
||||
struct mvneta_port *pp = arg;
|
||||
@@ -1467,7 +1444,6 @@ static void mvneta_defaults_set(struct m
|
||||
val &= ~MVNETA_PHY_POLLING_ENABLE;
|
||||
mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
|
||||
|
||||
- mvneta_set_autoneg(pp, pp->use_inband_status);
|
||||
mvneta_set_ucast_table(pp, -1);
|
||||
mvneta_set_special_mcast_table(pp, -1);
|
||||
mvneta_set_other_mcast_table(pp, -1);
|
||||
@@ -2692,26 +2668,11 @@ static irqreturn_t mvneta_percpu_isr(int
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
-static int mvneta_fixed_link_update(struct mvneta_port *pp,
|
||||
- struct phy_device *phy)
|
||||
+static void mvneta_link_change(struct mvneta_port *pp)
|
||||
{
|
||||
- struct fixed_phy_status status;
|
||||
- struct fixed_phy_status changed = {};
|
||||
u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
|
||||
|
||||
- status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
|
||||
- if (gmac_stat & MVNETA_GMAC_SPEED_1000)
|
||||
- status.speed = SPEED_1000;
|
||||
- else if (gmac_stat & MVNETA_GMAC_SPEED_100)
|
||||
- status.speed = SPEED_100;
|
||||
- else
|
||||
- status.speed = SPEED_10;
|
||||
- status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
|
||||
- changed.link = 1;
|
||||
- changed.speed = 1;
|
||||
- changed.duplex = 1;
|
||||
- fixed_phy_update_state(phy, &status, &changed);
|
||||
- return 0;
|
||||
+ phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
|
||||
}
|
||||
|
||||
/* NAPI handler
|
||||
@@ -2727,7 +2688,6 @@ static int mvneta_poll(struct napi_struc
|
||||
u32 cause_rx_tx;
|
||||
int rx_queue;
|
||||
struct mvneta_port *pp = netdev_priv(napi->dev);
|
||||
- struct net_device *ndev = pp->dev;
|
||||
struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
|
||||
|
||||
if (!netif_running(pp->dev)) {
|
||||
@@ -2741,12 +2701,11 @@ static int mvneta_poll(struct napi_struc
|
||||
u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
|
||||
|
||||
mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
|
||||
- if (pp->use_inband_status && (cause_misc &
|
||||
- (MVNETA_CAUSE_PHY_STATUS_CHANGE |
|
||||
- MVNETA_CAUSE_LINK_CHANGE |
|
||||
- MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
|
||||
- mvneta_fixed_link_update(pp, ndev->phydev);
|
||||
- }
|
||||
+
|
||||
+ if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
|
||||
+ MVNETA_CAUSE_LINK_CHANGE |
|
||||
+ MVNETA_CAUSE_PSC_SYNC_CHANGE))
|
||||
+ mvneta_link_change(pp);
|
||||
}
|
||||
|
||||
/* Release Tx descriptors */
|
||||
@@ -3060,7 +3019,6 @@ static int mvneta_setup_txqs(struct mvne
|
||||
static void mvneta_start_dev(struct mvneta_port *pp)
|
||||
{
|
||||
int cpu;
|
||||
- struct net_device *ndev = pp->dev;
|
||||
|
||||
mvneta_max_rx_size_set(pp, pp->pkt_size);
|
||||
mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
|
||||
@@ -3088,16 +3046,15 @@ static void mvneta_start_dev(struct mvne
|
||||
MVNETA_CAUSE_LINK_CHANGE |
|
||||
MVNETA_CAUSE_PSC_SYNC_CHANGE);
|
||||
|
||||
- phy_start(ndev->phydev);
|
||||
+ phylink_start(pp->phylink);
|
||||
netif_tx_start_all_queues(pp->dev);
|
||||
}
|
||||
|
||||
static void mvneta_stop_dev(struct mvneta_port *pp)
|
||||
{
|
||||
unsigned int cpu;
|
||||
- struct net_device *ndev = pp->dev;
|
||||
|
||||
- phy_stop(ndev->phydev);
|
||||
+ phylink_stop(pp->phylink);
|
||||
|
||||
if (!pp->neta_armada3700) {
|
||||
for_each_online_cpu(cpu) {
|
||||
@@ -3251,103 +3208,232 @@ static int mvneta_set_mac_addr(struct ne
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static void mvneta_adjust_link(struct net_device *ndev)
|
||||
+static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
|
||||
+ struct phylink_link_state *state)
|
||||
+{
|
||||
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
|
||||
+
|
||||
+ /* Allow all the expected bits */
|
||||
+ phylink_set(mask, Autoneg);
|
||||
+ phylink_set_port_modes(mask);
|
||||
+
|
||||
+ /* Asymmetric pause is unsupported */
|
||||
+ phylink_set(mask, Pause);
|
||||
+ /* Half-duplex at speeds higher than 100Mbit is unsupported */
|
||||
+ phylink_set(mask, 1000baseT_Full);
|
||||
+ phylink_set(mask, 1000baseX_Full);
|
||||
+
|
||||
+ if (state->interface != PHY_INTERFACE_MODE_1000BASEX) {
|
||||
+ /* 10M and 100M are only supported in non-802.3z mode */
|
||||
+ phylink_set(mask, 10baseT_Half);
|
||||
+ phylink_set(mask, 10baseT_Full);
|
||||
+ phylink_set(mask, 100baseT_Half);
|
||||
+ phylink_set(mask, 100baseT_Full);
|
||||
+ }
|
||||
+
|
||||
+ bitmap_and(supported, supported, mask,
|
||||
+ __ETHTOOL_LINK_MODE_MASK_NBITS);
|
||||
+ bitmap_and(state->advertising, state->advertising, mask,
|
||||
+ __ETHTOOL_LINK_MODE_MASK_NBITS);
|
||||
+}
|
||||
+
|
||||
+static int mvneta_mac_link_state(struct net_device *ndev,
|
||||
+ struct phylink_link_state *state)
|
||||
{
|
||||
struct mvneta_port *pp = netdev_priv(ndev);
|
||||
- struct phy_device *phydev = ndev->phydev;
|
||||
- int status_change = 0;
|
||||
+ u32 gmac_stat;
|
||||
|
||||
- if (phydev->link) {
|
||||
- if ((pp->speed != phydev->speed) ||
|
||||
- (pp->duplex != phydev->duplex)) {
|
||||
- u32 val;
|
||||
-
|
||||
- val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
|
||||
- val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
|
||||
- MVNETA_GMAC_CONFIG_GMII_SPEED |
|
||||
- MVNETA_GMAC_CONFIG_FULL_DUPLEX);
|
||||
-
|
||||
- if (phydev->duplex)
|
||||
- val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
|
||||
-
|
||||
- if (phydev->speed == SPEED_1000)
|
||||
- val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
|
||||
- else if (phydev->speed == SPEED_100)
|
||||
- val |= MVNETA_GMAC_CONFIG_MII_SPEED;
|
||||
+ gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
|
||||
|
||||
- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
|
||||
+ if (gmac_stat & MVNETA_GMAC_SPEED_1000)
|
||||
+ state->speed = SPEED_1000;
|
||||
+ else if (gmac_stat & MVNETA_GMAC_SPEED_100)
|
||||
+ state->speed = SPEED_100;
|
||||
+ else
|
||||
+ state->speed = SPEED_10;
|
||||
|
||||
- pp->duplex = phydev->duplex;
|
||||
- pp->speed = phydev->speed;
|
||||
- }
|
||||
+ state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
|
||||
+ state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
|
||||
+ state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
|
||||
+
|
||||
+ state->pause = 0;
|
||||
+ if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
|
||||
+ state->pause |= MLO_PAUSE_RX;
|
||||
+ if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
|
||||
+ state->pause |= MLO_PAUSE_TX;
|
||||
+
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
+static void mvneta_mac_an_restart(struct net_device *ndev)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(ndev);
|
||||
+ u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
|
||||
+
|
||||
+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
|
||||
+ gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
|
||||
+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
|
||||
+ gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
|
||||
+}
|
||||
+
|
||||
+static void mvneta_mac_config(struct net_device *ndev, unsigned int mode,
|
||||
+ const struct phylink_link_state *state)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(ndev);
|
||||
+ u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
|
||||
+ u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
|
||||
+ u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
|
||||
+ u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
|
||||
+
|
||||
+ new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
|
||||
+ new_ctrl2 = gmac_ctrl2 & ~MVNETA_GMAC2_INBAND_AN_ENABLE;
|
||||
+ new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
|
||||
+ new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
|
||||
+ MVNETA_GMAC_INBAND_RESTART_AN |
|
||||
+ MVNETA_GMAC_CONFIG_MII_SPEED |
|
||||
+ MVNETA_GMAC_CONFIG_GMII_SPEED |
|
||||
+ MVNETA_GMAC_AN_SPEED_EN |
|
||||
+ MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL |
|
||||
+ MVNETA_GMAC_CONFIG_FLOW_CTRL |
|
||||
+ MVNETA_GMAC_AN_FLOW_CTRL_EN |
|
||||
+ MVNETA_GMAC_CONFIG_FULL_DUPLEX |
|
||||
+ MVNETA_GMAC_AN_DUPLEX_EN);
|
||||
+
|
||||
+ if (phylink_test(state->advertising, Pause))
|
||||
+ new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
|
||||
+ if (state->pause & MLO_PAUSE_TXRX_MASK)
|
||||
+ new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
|
||||
+
|
||||
+ if (!phylink_autoneg_inband(mode)) {
|
||||
+ /* Phy or fixed speed */
|
||||
+ if (state->duplex)
|
||||
+ new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
|
||||
+
|
||||
+ if (state->speed == SPEED_1000)
|
||||
+ new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED;
|
||||
+ else if (state->speed == SPEED_100)
|
||||
+ new_an |= MVNETA_GMAC_CONFIG_MII_SPEED;
|
||||
+ } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
|
||||
+ /* SGMII mode receives the state from the PHY */
|
||||
+ new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
|
||||
+ new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
|
||||
+ new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
|
||||
+ MVNETA_GMAC_FORCE_LINK_PASS)) |
|
||||
+ MVNETA_GMAC_INBAND_AN_ENABLE |
|
||||
+ MVNETA_GMAC_AN_SPEED_EN |
|
||||
+ MVNETA_GMAC_AN_DUPLEX_EN;
|
||||
+ } else {
|
||||
+ /* 802.3z negotiation - only 1000base-X */
|
||||
+ new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
|
||||
+ new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
|
||||
+ new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
|
||||
+ MVNETA_GMAC_FORCE_LINK_PASS)) |
|
||||
+ MVNETA_GMAC_INBAND_AN_ENABLE |
|
||||
+ MVNETA_GMAC_CONFIG_GMII_SPEED |
|
||||
+ /* The MAC only supports FD mode */
|
||||
+ MVNETA_GMAC_CONFIG_FULL_DUPLEX;
|
||||
+
|
||||
+ if (state->pause & MLO_PAUSE_AN && state->an_enabled)
|
||||
+ new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
|
||||
+ }
|
||||
+
|
||||
+ /* Armada 370 documentation says we can only change the port mode
|
||||
+ * and in-band enable when the link is down, so force it down
|
||||
+ * while making these changes. We also do this for GMAC_CTRL2 */
|
||||
+ if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
|
||||
+ (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
|
||||
+ (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
|
||||
+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
|
||||
+ (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) |
|
||||
+ MVNETA_GMAC_FORCE_LINK_DOWN);
|
||||
+ }
|
||||
+
|
||||
+ if (new_ctrl0 != gmac_ctrl0)
|
||||
+ mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
|
||||
+ if (new_ctrl2 != gmac_ctrl2)
|
||||
+ mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
|
||||
+ if (new_clk != gmac_clk)
|
||||
+ mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
|
||||
+ if (new_an != gmac_an)
|
||||
+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
|
||||
+}
|
||||
+
|
||||
+static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
|
||||
+{
|
||||
+ u32 lpi_ctl1;
|
||||
+
|
||||
+ lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
|
||||
+ if (enable)
|
||||
+ lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
|
||||
+ else
|
||||
+ lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
|
||||
+ mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
|
||||
+}
|
||||
+
|
||||
+static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(ndev);
|
||||
+ u32 val;
|
||||
+
|
||||
+ mvneta_port_down(pp);
|
||||
+
|
||||
+ if (!phylink_autoneg_inband(mode)) {
|
||||
+ val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
|
||||
+ val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
|
||||
+ val |= MVNETA_GMAC_FORCE_LINK_DOWN;
|
||||
+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
|
||||
}
|
||||
|
||||
- if (phydev->link != pp->link) {
|
||||
- if (!phydev->link) {
|
||||
- pp->duplex = -1;
|
||||
- pp->speed = 0;
|
||||
- }
|
||||
+ pp->eee_active = false;
|
||||
+ mvneta_set_eee(pp, false);
|
||||
+}
|
||||
+
|
||||
+static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode,
|
||||
+ struct phy_device *phy)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(ndev);
|
||||
+ u32 val;
|
||||
|
||||
- pp->link = phydev->link;
|
||||
- status_change = 1;
|
||||
+ if (!phylink_autoneg_inband(mode)) {
|
||||
+ val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
|
||||
+ val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
|
||||
+ val |= MVNETA_GMAC_FORCE_LINK_PASS;
|
||||
+ mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
|
||||
}
|
||||
|
||||
- if (status_change) {
|
||||
- if (phydev->link) {
|
||||
- if (!pp->use_inband_status) {
|
||||
- u32 val = mvreg_read(pp,
|
||||
- MVNETA_GMAC_AUTONEG_CONFIG);
|
||||
- val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
|
||||
- val |= MVNETA_GMAC_FORCE_LINK_PASS;
|
||||
- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
|
||||
- val);
|
||||
- }
|
||||
- mvneta_port_up(pp);
|
||||
- } else {
|
||||
- if (!pp->use_inband_status) {
|
||||
- u32 val = mvreg_read(pp,
|
||||
- MVNETA_GMAC_AUTONEG_CONFIG);
|
||||
- val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
|
||||
- val |= MVNETA_GMAC_FORCE_LINK_DOWN;
|
||||
- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
|
||||
- val);
|
||||
- }
|
||||
- mvneta_port_down(pp);
|
||||
- }
|
||||
- phy_print_status(phydev);
|
||||
+ mvneta_port_up(pp);
|
||||
+
|
||||
+ if (phy && pp->eee_enabled) {
|
||||
+ pp->eee_active = phy_init_eee(phy, 0) >= 0;
|
||||
+ mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
|
||||
}
|
||||
}
|
||||
|
||||
+static const struct phylink_mac_ops mvneta_phylink_ops = {
|
||||
+ .validate = mvneta_validate,
|
||||
+ .mac_link_state = mvneta_mac_link_state,
|
||||
+ .mac_an_restart = mvneta_mac_an_restart,
|
||||
+ .mac_config = mvneta_mac_config,
|
||||
+ .mac_link_down = mvneta_mac_link_down,
|
||||
+ .mac_link_up = mvneta_mac_link_up,
|
||||
+};
|
||||
+
|
||||
static int mvneta_mdio_probe(struct mvneta_port *pp)
|
||||
{
|
||||
- struct phy_device *phy_dev;
|
||||
struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
|
||||
+ int err = phylink_of_phy_connect(pp->phylink, pp->dn);
|
||||
+ if (err)
|
||||
+ netdev_err(pp->dev, "could not attach PHY\n");
|
||||
|
||||
- phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
|
||||
- pp->phy_interface);
|
||||
- if (!phy_dev) {
|
||||
- netdev_err(pp->dev, "could not find the PHY\n");
|
||||
- return -ENODEV;
|
||||
- }
|
||||
-
|
||||
- phy_ethtool_get_wol(phy_dev, &wol);
|
||||
+ phylink_ethtool_get_wol(pp->phylink, &wol);
|
||||
device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
|
||||
|
||||
- phy_dev->supported &= PHY_GBIT_FEATURES;
|
||||
- phy_dev->advertising = phy_dev->supported;
|
||||
-
|
||||
- pp->link = 0;
|
||||
- pp->duplex = 0;
|
||||
- pp->speed = 0;
|
||||
-
|
||||
- return 0;
|
||||
+ return err;
|
||||
}
|
||||
|
||||
static void mvneta_mdio_remove(struct mvneta_port *pp)
|
||||
{
|
||||
- struct net_device *ndev = pp->dev;
|
||||
-
|
||||
- phy_disconnect(ndev->phydev);
|
||||
+ phylink_disconnect_phy(pp->phylink);
|
||||
}
|
||||
|
||||
/* Electing a CPU must be done in an atomic way: it should be done
|
||||
@@ -3626,10 +3712,9 @@ static int mvneta_stop(struct net_device
|
||||
|
||||
static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
||||
{
|
||||
- if (!dev->phydev)
|
||||
- return -ENOTSUPP;
|
||||
+ struct mvneta_port *pp = netdev_priv(dev);
|
||||
|
||||
- return phy_mii_ioctl(dev->phydev, ifr, cmd);
|
||||
+ return phylink_mii_ioctl(pp->phylink, ifr, cmd);
|
||||
}
|
||||
|
||||
/* Ethtool methods */
|
||||
@@ -3640,44 +3725,25 @@ mvneta_ethtool_set_link_ksettings(struct
|
||||
const struct ethtool_link_ksettings *cmd)
|
||||
{
|
||||
struct mvneta_port *pp = netdev_priv(ndev);
|
||||
- struct phy_device *phydev = ndev->phydev;
|
||||
|
||||
- if (!phydev)
|
||||
- return -ENODEV;
|
||||
-
|
||||
- if ((cmd->base.autoneg == AUTONEG_ENABLE) != pp->use_inband_status) {
|
||||
- u32 val;
|
||||
-
|
||||
- mvneta_set_autoneg(pp, cmd->base.autoneg == AUTONEG_ENABLE);
|
||||
-
|
||||
- if (cmd->base.autoneg == AUTONEG_DISABLE) {
|
||||
- val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
|
||||
- val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
|
||||
- MVNETA_GMAC_CONFIG_GMII_SPEED |
|
||||
- MVNETA_GMAC_CONFIG_FULL_DUPLEX);
|
||||
-
|
||||
- if (phydev->duplex)
|
||||
- val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
|
||||
+ return phylink_ethtool_ksettings_set(pp->phylink, cmd);
|
||||
+}
|
||||
|
||||
- if (phydev->speed == SPEED_1000)
|
||||
- val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
|
||||
- else if (phydev->speed == SPEED_100)
|
||||
- val |= MVNETA_GMAC_CONFIG_MII_SPEED;
|
||||
+/* Get link ksettings for ethtools */
|
||||
+static int
|
||||
+mvneta_ethtool_get_link_ksettings(struct net_device *ndev,
|
||||
+ struct ethtool_link_ksettings *cmd)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(ndev);
|
||||
|
||||
- mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
|
||||
- }
|
||||
+ return phylink_ethtool_ksettings_get(pp->phylink, cmd);
|
||||
+}
|
||||
|
||||
- pp->use_inband_status = (cmd->base.autoneg == AUTONEG_ENABLE);
|
||||
- netdev_info(pp->dev, "autoneg status set to %i\n",
|
||||
- pp->use_inband_status);
|
||||
-
|
||||
- if (netif_running(ndev)) {
|
||||
- mvneta_port_down(pp);
|
||||
- mvneta_port_up(pp);
|
||||
- }
|
||||
- }
|
||||
+static int mvneta_ethtool_nway_reset(struct net_device *dev)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(dev);
|
||||
|
||||
- return phy_ethtool_ksettings_set(ndev->phydev, cmd);
|
||||
+ return phylink_ethtool_nway_reset(pp->phylink);
|
||||
}
|
||||
|
||||
/* Set interrupt coalescing for ethtools */
|
||||
@@ -3769,6 +3835,22 @@ static int mvneta_ethtool_set_ringparam(
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void mvneta_ethtool_get_pauseparam(struct net_device *dev,
|
||||
+ struct ethtool_pauseparam *pause)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(dev);
|
||||
+
|
||||
+ phylink_ethtool_get_pauseparam(pp->phylink, pause);
|
||||
+}
|
||||
+
|
||||
+static int mvneta_ethtool_set_pauseparam(struct net_device *dev,
|
||||
+ struct ethtool_pauseparam *pause)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(dev);
|
||||
+
|
||||
+ return phylink_ethtool_set_pauseparam(pp->phylink, pause);
|
||||
+}
|
||||
+
|
||||
static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
|
||||
u8 *data)
|
||||
{
|
||||
@@ -3785,26 +3867,35 @@ static void mvneta_ethtool_update_stats(
|
||||
{
|
||||
const struct mvneta_statistic *s;
|
||||
void __iomem *base = pp->base;
|
||||
- u32 high, low, val;
|
||||
- u64 val64;
|
||||
+ u32 high, low;
|
||||
+ u64 val;
|
||||
int i;
|
||||
|
||||
for (i = 0, s = mvneta_statistics;
|
||||
s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
|
||||
s++, i++) {
|
||||
+ val = 0;
|
||||
+
|
||||
switch (s->type) {
|
||||
case T_REG_32:
|
||||
val = readl_relaxed(base + s->offset);
|
||||
- pp->ethtool_stats[i] += val;
|
||||
break;
|
||||
case T_REG_64:
|
||||
/* Docs say to read low 32-bit then high */
|
||||
low = readl_relaxed(base + s->offset);
|
||||
high = readl_relaxed(base + s->offset + 4);
|
||||
- val64 = (u64)high << 32 | low;
|
||||
- pp->ethtool_stats[i] += val64;
|
||||
+ val = (u64)high << 32 | low;
|
||||
+ break;
|
||||
+ case T_SW:
|
||||
+ switch (s->offset) {
|
||||
+ case ETHTOOL_STAT_EEE_WAKEUP:
|
||||
+ val = phylink_get_eee_err(pp->phylink);
|
||||
+ break;
|
||||
+ }
|
||||
break;
|
||||
}
|
||||
+
|
||||
+ pp->ethtool_stats[i] += val;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -3939,28 +4030,65 @@ static int mvneta_ethtool_get_rxfh(struc
|
||||
static void mvneta_ethtool_get_wol(struct net_device *dev,
|
||||
struct ethtool_wolinfo *wol)
|
||||
{
|
||||
- wol->supported = 0;
|
||||
- wol->wolopts = 0;
|
||||
+ struct mvneta_port *pp = netdev_priv(dev);
|
||||
|
||||
- if (dev->phydev)
|
||||
- phy_ethtool_get_wol(dev->phydev, wol);
|
||||
+ phylink_ethtool_get_wol(pp->phylink, wol);
|
||||
}
|
||||
|
||||
static int mvneta_ethtool_set_wol(struct net_device *dev,
|
||||
struct ethtool_wolinfo *wol)
|
||||
{
|
||||
+ struct mvneta_port *pp = netdev_priv(dev);
|
||||
int ret;
|
||||
|
||||
- if (!dev->phydev)
|
||||
- return -EOPNOTSUPP;
|
||||
-
|
||||
- ret = phy_ethtool_set_wol(dev->phydev, wol);
|
||||
+ ret = phylink_ethtool_set_wol(pp->phylink, wol);
|
||||
if (!ret)
|
||||
device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static int mvneta_ethtool_get_eee(struct net_device *dev,
|
||||
+ struct ethtool_eee *eee)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(dev);
|
||||
+ u32 lpi_ctl0;
|
||||
+
|
||||
+ lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
|
||||
+
|
||||
+ eee->eee_enabled = pp->eee_enabled;
|
||||
+ eee->eee_active = pp->eee_active;
|
||||
+ eee->tx_lpi_enabled = pp->tx_lpi_enabled;
|
||||
+ eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
|
||||
+
|
||||
+ return phylink_ethtool_get_eee(pp->phylink, eee);
|
||||
+}
|
||||
+
|
||||
+static int mvneta_ethtool_set_eee(struct net_device *dev,
|
||||
+ struct ethtool_eee *eee)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(dev);
|
||||
+ u32 lpi_ctl0;
|
||||
+
|
||||
+ /* The Armada 37x documents do not give limits for this other than
|
||||
+ * it being an 8-bit register. */
|
||||
+ if (eee->tx_lpi_enabled &&
|
||||
+ (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
|
||||
+ lpi_ctl0 &= ~(0xff << 8);
|
||||
+ lpi_ctl0 |= eee->tx_lpi_timer << 8;
|
||||
+ mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
|
||||
+
|
||||
+ pp->eee_enabled = eee->eee_enabled;
|
||||
+ pp->tx_lpi_enabled = eee->tx_lpi_enabled;
|
||||
+
|
||||
+ mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
|
||||
+
|
||||
+ return phylink_ethtool_set_eee(pp->phylink, eee);
|
||||
+}
|
||||
+
|
||||
static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
|
||||
void *accel_priv,
|
||||
select_queue_fallback_t fallback)
|
||||
@@ -3984,13 +4112,15 @@ static const struct net_device_ops mvnet
|
||||
};
|
||||
|
||||
static const struct ethtool_ops mvneta_eth_tool_ops = {
|
||||
- .nway_reset = phy_ethtool_nway_reset,
|
||||
+ .nway_reset = mvneta_ethtool_nway_reset,
|
||||
.get_link = ethtool_op_get_link,
|
||||
.set_coalesce = mvneta_ethtool_set_coalesce,
|
||||
.get_coalesce = mvneta_ethtool_get_coalesce,
|
||||
.get_drvinfo = mvneta_ethtool_get_drvinfo,
|
||||
.get_ringparam = mvneta_ethtool_get_ringparam,
|
||||
.set_ringparam = mvneta_ethtool_set_ringparam,
|
||||
+ .get_pauseparam = mvneta_ethtool_get_pauseparam,
|
||||
+ .set_pauseparam = mvneta_ethtool_set_pauseparam,
|
||||
.get_strings = mvneta_ethtool_get_strings,
|
||||
.get_ethtool_stats = mvneta_ethtool_get_stats,
|
||||
.get_sset_count = mvneta_ethtool_get_sset_count,
|
||||
@@ -3998,10 +4128,12 @@ static const struct ethtool_ops mvneta_e
|
||||
.get_rxnfc = mvneta_ethtool_get_rxnfc,
|
||||
.get_rxfh = mvneta_ethtool_get_rxfh,
|
||||
.set_rxfh = mvneta_ethtool_set_rxfh,
|
||||
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
|
||||
+ .get_link_ksettings = mvneta_ethtool_get_link_ksettings,
|
||||
.set_link_ksettings = mvneta_ethtool_set_link_ksettings,
|
||||
.get_wol = mvneta_ethtool_get_wol,
|
||||
.set_wol = mvneta_ethtool_set_wol,
|
||||
+ .get_eee = mvneta_ethtool_get_eee,
|
||||
+ .set_eee = mvneta_ethtool_set_eee,
|
||||
};
|
||||
|
||||
/* Initialize hw */
|
||||
@@ -4146,14 +4278,13 @@ static int mvneta_probe(struct platform_
|
||||
{
|
||||
struct resource *res;
|
||||
struct device_node *dn = pdev->dev.of_node;
|
||||
- struct device_node *phy_node;
|
||||
struct device_node *bm_node;
|
||||
struct mvneta_port *pp;
|
||||
struct net_device *dev;
|
||||
+ struct phylink *phylink;
|
||||
const char *dt_mac_addr;
|
||||
char hw_mac_addr[ETH_ALEN];
|
||||
const char *mac_from;
|
||||
- const char *managed;
|
||||
int tx_csum_limit;
|
||||
int phy_mode;
|
||||
int err;
|
||||
@@ -4169,31 +4300,11 @@ static int mvneta_probe(struct platform_
|
||||
goto err_free_netdev;
|
||||
}
|
||||
|
||||
- phy_node = of_parse_phandle(dn, "phy", 0);
|
||||
- if (!phy_node) {
|
||||
- if (!of_phy_is_fixed_link(dn)) {
|
||||
- dev_err(&pdev->dev, "no PHY specified\n");
|
||||
- err = -ENODEV;
|
||||
- goto err_free_irq;
|
||||
- }
|
||||
-
|
||||
- err = of_phy_register_fixed_link(dn);
|
||||
- if (err < 0) {
|
||||
- dev_err(&pdev->dev, "cannot register fixed PHY\n");
|
||||
- goto err_free_irq;
|
||||
- }
|
||||
-
|
||||
- /* In the case of a fixed PHY, the DT node associated
|
||||
- * to the PHY is the Ethernet MAC DT node.
|
||||
- */
|
||||
- phy_node = of_node_get(dn);
|
||||
- }
|
||||
-
|
||||
phy_mode = of_get_phy_mode(dn);
|
||||
if (phy_mode < 0) {
|
||||
dev_err(&pdev->dev, "incorrect phy-mode\n");
|
||||
err = -EINVAL;
|
||||
- goto err_put_phy_node;
|
||||
+ goto err_free_irq;
|
||||
}
|
||||
|
||||
dev->tx_queue_len = MVNETA_MAX_TXD;
|
||||
@@ -4204,12 +4315,7 @@ static int mvneta_probe(struct platform_
|
||||
|
||||
pp = netdev_priv(dev);
|
||||
spin_lock_init(&pp->lock);
|
||||
- pp->phy_node = phy_node;
|
||||
- pp->phy_interface = phy_mode;
|
||||
-
|
||||
- err = of_property_read_string(dn, "managed", &managed);
|
||||
- pp->use_inband_status = (err == 0 &&
|
||||
- strcmp(managed, "in-band-status") == 0);
|
||||
+ pp->dn = dn;
|
||||
|
||||
pp->rxq_def = rxq_def;
|
||||
|
||||
@@ -4231,7 +4337,7 @@ static int mvneta_probe(struct platform_
|
||||
pp->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(pp->clk)) {
|
||||
err = PTR_ERR(pp->clk);
|
||||
- goto err_put_phy_node;
|
||||
+ goto err_free_irq;
|
||||
}
|
||||
|
||||
clk_prepare_enable(pp->clk);
|
||||
@@ -4357,6 +4463,14 @@ static int mvneta_probe(struct platform_
|
||||
/* 9676 == 9700 - 20 and rounding to 8 */
|
||||
dev->max_mtu = 9676;
|
||||
|
||||
+ phylink = phylink_create(dev, dn, phy_mode, &mvneta_phylink_ops);
|
||||
+ if (IS_ERR(phylink)) {
|
||||
+ err = PTR_ERR(phylink);
|
||||
+ goto err_free_stats;
|
||||
+ }
|
||||
+
|
||||
+ pp->phylink = phylink;
|
||||
+
|
||||
err = register_netdev(dev);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to register\n");
|
||||
@@ -4368,14 +4482,6 @@ static int mvneta_probe(struct platform_
|
||||
|
||||
platform_set_drvdata(pdev, pp->dev);
|
||||
|
||||
- if (pp->use_inband_status) {
|
||||
- struct phy_device *phy = of_phy_find_device(dn);
|
||||
-
|
||||
- mvneta_fixed_link_update(pp, phy);
|
||||
-
|
||||
- put_device(&phy->mdio.dev);
|
||||
- }
|
||||
-
|
||||
return 0;
|
||||
|
||||
err_netdev:
|
||||
@@ -4386,16 +4492,14 @@ err_netdev:
|
||||
1 << pp->id);
|
||||
}
|
||||
err_free_stats:
|
||||
+ if (pp->phylink)
|
||||
+ phylink_destroy(pp->phylink);
|
||||
free_percpu(pp->stats);
|
||||
err_free_ports:
|
||||
free_percpu(pp->ports);
|
||||
err_clk:
|
||||
clk_disable_unprepare(pp->clk_bus);
|
||||
clk_disable_unprepare(pp->clk);
|
||||
-err_put_phy_node:
|
||||
- of_node_put(phy_node);
|
||||
- if (of_phy_is_fixed_link(dn))
|
||||
- of_phy_deregister_fixed_link(dn);
|
||||
err_free_irq:
|
||||
irq_dispose_mapping(dev->irq);
|
||||
err_free_netdev:
|
||||
@@ -4407,7 +4511,6 @@ err_free_netdev:
|
||||
static int mvneta_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *dev = platform_get_drvdata(pdev);
|
||||
- struct device_node *dn = pdev->dev.of_node;
|
||||
struct mvneta_port *pp = netdev_priv(dev);
|
||||
|
||||
unregister_netdev(dev);
|
||||
@@ -4415,10 +4518,8 @@ static int mvneta_remove(struct platform
|
||||
clk_disable_unprepare(pp->clk);
|
||||
free_percpu(pp->ports);
|
||||
free_percpu(pp->stats);
|
||||
- if (of_phy_is_fixed_link(dn))
|
||||
- of_phy_deregister_fixed_link(dn);
|
||||
irq_dispose_mapping(dev->irq);
|
||||
- of_node_put(pp->phy_node);
|
||||
+ phylink_destroy(pp->phylink);
|
||||
free_netdev(dev);
|
||||
|
||||
if (pp->bm_priv) {
|
||||
@@ -4470,9 +4571,6 @@ static int mvneta_resume(struct device *
|
||||
return err;
|
||||
}
|
||||
|
||||
- if (pp->use_inband_status)
|
||||
- mvneta_fixed_link_update(pp, dev->phydev);
|
||||
-
|
||||
netif_device_attach(dev);
|
||||
if (netif_running(dev)) {
|
||||
mvneta_open(dev);
|
|
@ -0,0 +1,28 @@
|
|||
From acdfcc7ef78c46baca1439a1cac5b73008abc672 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Tue, 16 May 2017 11:55:58 +0100
|
||||
Subject: net: mvneta: hack fix phy_interface
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
drivers/net/ethernet/marvell/mvneta.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -427,6 +427,7 @@ struct mvneta_port {
|
||||
u16 tx_ring_size;
|
||||
u16 rx_ring_size;
|
||||
|
||||
+ phy_interface_t phy_interface;
|
||||
struct device_node *dn;
|
||||
unsigned int tx_csum_limit;
|
||||
struct phylink *phylink;
|
||||
@@ -4315,6 +4316,7 @@ static int mvneta_probe(struct platform_
|
||||
|
||||
pp = netdev_priv(dev);
|
||||
spin_lock_init(&pp->lock);
|
||||
+ pp->phy_interface = phy_mode;
|
||||
pp->dn = dn;
|
||||
|
||||
pp->rxq_def = rxq_def;
|
|
@ -0,0 +1,56 @@
|
|||
From fde9e742a47606110232b7464608b6f9c0510938 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Sat, 24 Dec 2016 10:27:08 +0000
|
||||
Subject: net: mvneta: disable MVNETA_CAUSE_PSC_SYNC_CHANGE interrupt
|
||||
|
||||
The PSC sync change interrupt can fire multiple times while the link is
|
||||
down. As this isn't information we make use of, it's pointless having
|
||||
the interrupt enabled, so let's disable this interrupt.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
drivers/net/ethernet/marvell/mvneta.c | 12 ++++--------
|
||||
1 file changed, 4 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -2704,8 +2704,7 @@ static int mvneta_poll(struct napi_struc
|
||||
mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
|
||||
|
||||
if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
|
||||
- MVNETA_CAUSE_LINK_CHANGE |
|
||||
- MVNETA_CAUSE_PSC_SYNC_CHANGE))
|
||||
+ MVNETA_CAUSE_LINK_CHANGE))
|
||||
mvneta_link_change(pp);
|
||||
}
|
||||
|
||||
@@ -3044,8 +3043,7 @@ static void mvneta_start_dev(struct mvne
|
||||
|
||||
mvreg_write(pp, MVNETA_INTR_MISC_MASK,
|
||||
MVNETA_CAUSE_PHY_STATUS_CHANGE |
|
||||
- MVNETA_CAUSE_LINK_CHANGE |
|
||||
- MVNETA_CAUSE_PSC_SYNC_CHANGE);
|
||||
+ MVNETA_CAUSE_LINK_CHANGE);
|
||||
|
||||
phylink_start(pp->phylink);
|
||||
netif_tx_start_all_queues(pp->dev);
|
||||
@@ -3542,8 +3540,7 @@ static int mvneta_cpu_online(unsigned in
|
||||
on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
|
||||
mvreg_write(pp, MVNETA_INTR_MISC_MASK,
|
||||
MVNETA_CAUSE_PHY_STATUS_CHANGE |
|
||||
- MVNETA_CAUSE_LINK_CHANGE |
|
||||
- MVNETA_CAUSE_PSC_SYNC_CHANGE);
|
||||
+ MVNETA_CAUSE_LINK_CHANGE);
|
||||
netif_tx_start_all_queues(pp->dev);
|
||||
spin_unlock(&pp->lock);
|
||||
return 0;
|
||||
@@ -3584,8 +3581,7 @@ static int mvneta_cpu_dead(unsigned int
|
||||
on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
|
||||
mvreg_write(pp, MVNETA_INTR_MISC_MASK,
|
||||
MVNETA_CAUSE_PHY_STATUS_CHANGE |
|
||||
- MVNETA_CAUSE_LINK_CHANGE |
|
||||
- MVNETA_CAUSE_PSC_SYNC_CHANGE);
|
||||
+ MVNETA_CAUSE_LINK_CHANGE);
|
||||
netif_tx_start_all_queues(pp->dev);
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,44 @@
|
|||
From 2ff039aa4462c2104c210b7cf39691c612de8214 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Thu, 1 Oct 2015 23:32:39 +0100
|
||||
Subject: net: mvneta: add module EEPROM reading support
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
---
|
||||
drivers/net/ethernet/marvell/mvneta.c | 18 ++++++++++++++++++
|
||||
1 file changed, 18 insertions(+)
|
||||
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -4045,6 +4045,22 @@ static int mvneta_ethtool_set_wol(struct
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static int mvneta_ethtool_get_module_info(struct net_device *dev,
|
||||
+ struct ethtool_modinfo *modinfo)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(dev);
|
||||
+
|
||||
+ return phylink_ethtool_get_module_info(pp->phylink, modinfo);
|
||||
+}
|
||||
+
|
||||
+static int mvneta_ethtool_get_module_eeprom(struct net_device *dev,
|
||||
+ struct ethtool_eeprom *ee, u8 *buf)
|
||||
+{
|
||||
+ struct mvneta_port *pp = netdev_priv(dev);
|
||||
+
|
||||
+ return phylink_ethtool_get_module_eeprom(pp->phylink, ee, buf);
|
||||
+}
|
||||
+
|
||||
static int mvneta_ethtool_get_eee(struct net_device *dev,
|
||||
struct ethtool_eee *eee)
|
||||
{
|
||||
@@ -4129,6 +4145,8 @@ static const struct ethtool_ops mvneta_e
|
||||
.set_link_ksettings = mvneta_ethtool_set_link_ksettings,
|
||||
.get_wol = mvneta_ethtool_get_wol,
|
||||
.set_wol = mvneta_ethtool_set_wol,
|
||||
+ .get_module_info = mvneta_ethtool_get_module_info,
|
||||
+ .get_module_eeprom = mvneta_ethtool_get_module_eeprom,
|
||||
.get_eee = mvneta_ethtool_get_eee,
|
||||
.set_eee = mvneta_ethtool_set_eee,
|
||||
};
|
|
@ -0,0 +1,80 @@
|
|||
From 774ce2eda0a929f79ee398ba6d2d13fd406f31c4 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Fri, 2 Oct 2015 22:46:54 +0100
|
||||
Subject: phy: fixed-phy: remove fixed_phy_update_state()
|
||||
|
||||
mvneta is the only user of fixed_phy_update_state(), which has been
|
||||
converted to use phylink instead. Remove fixed_phy_update_state().
|
||||
|
||||
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
---
|
||||
drivers/net/phy/fixed_phy.c | 31 -------------------------------
|
||||
include/linux/phy_fixed.h | 9 ---------
|
||||
2 files changed, 40 deletions(-)
|
||||
|
||||
--- a/drivers/net/phy/fixed_phy.c
|
||||
+++ b/drivers/net/phy/fixed_phy.c
|
||||
@@ -115,37 +115,6 @@ int fixed_phy_set_link_update(struct phy
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(fixed_phy_set_link_update);
|
||||
|
||||
-int fixed_phy_update_state(struct phy_device *phydev,
|
||||
- const struct fixed_phy_status *status,
|
||||
- const struct fixed_phy_status *changed)
|
||||
-{
|
||||
- struct fixed_mdio_bus *fmb = &platform_fmb;
|
||||
- struct fixed_phy *fp;
|
||||
-
|
||||
- if (!phydev || phydev->mdio.bus != fmb->mii_bus)
|
||||
- return -EINVAL;
|
||||
-
|
||||
- list_for_each_entry(fp, &fmb->phys, node) {
|
||||
- if (fp->addr == phydev->mdio.addr) {
|
||||
- write_seqcount_begin(&fp->seqcount);
|
||||
-#define _UPD(x) if (changed->x) \
|
||||
- fp->status.x = status->x
|
||||
- _UPD(link);
|
||||
- _UPD(speed);
|
||||
- _UPD(duplex);
|
||||
- _UPD(pause);
|
||||
- _UPD(asym_pause);
|
||||
-#undef _UPD
|
||||
- fixed_phy_update(fp);
|
||||
- write_seqcount_end(&fp->seqcount);
|
||||
- return 0;
|
||||
- }
|
||||
- }
|
||||
-
|
||||
- return -ENOENT;
|
||||
-}
|
||||
-EXPORT_SYMBOL(fixed_phy_update_state);
|
||||
-
|
||||
int fixed_phy_add(unsigned int irq, int phy_addr,
|
||||
struct fixed_phy_status *status,
|
||||
int link_gpio)
|
||||
--- a/include/linux/phy_fixed.h
|
||||
+++ b/include/linux/phy_fixed.h
|
||||
@@ -24,9 +24,6 @@ extern void fixed_phy_unregister(struct
|
||||
extern int fixed_phy_set_link_update(struct phy_device *phydev,
|
||||
int (*link_update)(struct net_device *,
|
||||
struct fixed_phy_status *));
|
||||
-extern int fixed_phy_update_state(struct phy_device *phydev,
|
||||
- const struct fixed_phy_status *status,
|
||||
- const struct fixed_phy_status *changed);
|
||||
#else
|
||||
static inline int fixed_phy_add(unsigned int irq, int phy_id,
|
||||
struct fixed_phy_status *status,
|
||||
@@ -50,12 +47,6 @@ static inline int fixed_phy_set_link_upd
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
-static inline int fixed_phy_update_state(struct phy_device *phydev,
|
||||
- const struct fixed_phy_status *status,
|
||||
- const struct fixed_phy_status *changed)
|
||||
-{
|
||||
- return -ENODEV;
|
||||
-}
|
||||
#endif /* CONFIG_FIXED_PHY */
|
||||
|
||||
#endif /* __PHY_FIXED_H */
|
|
@ -0,0 +1,181 @@
|
|||
From c47beb7e3f8575dfd7d58240a72c4e4e66ce5449 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Fri, 14 Apr 2017 15:26:32 +0100
|
||||
Subject: sfp: move module eeprom ethtool access into netdev core ethtool
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
drivers/net/ethernet/marvell/mvneta.c | 18 ------------------
|
||||
drivers/net/phy/phylink.c | 28 ----------------------------
|
||||
drivers/net/phy/sfp-bus.c | 6 ++----
|
||||
include/linux/netdevice.h | 2 ++
|
||||
include/linux/phylink.h | 3 ---
|
||||
net/core/ethtool.c | 7 +++++++
|
||||
6 files changed, 11 insertions(+), 53 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -4045,22 +4045,6 @@ static int mvneta_ethtool_set_wol(struct
|
||||
return ret;
|
||||
}
|
||||
|
||||
-static int mvneta_ethtool_get_module_info(struct net_device *dev,
|
||||
- struct ethtool_modinfo *modinfo)
|
||||
-{
|
||||
- struct mvneta_port *pp = netdev_priv(dev);
|
||||
-
|
||||
- return phylink_ethtool_get_module_info(pp->phylink, modinfo);
|
||||
-}
|
||||
-
|
||||
-static int mvneta_ethtool_get_module_eeprom(struct net_device *dev,
|
||||
- struct ethtool_eeprom *ee, u8 *buf)
|
||||
-{
|
||||
- struct mvneta_port *pp = netdev_priv(dev);
|
||||
-
|
||||
- return phylink_ethtool_get_module_eeprom(pp->phylink, ee, buf);
|
||||
-}
|
||||
-
|
||||
static int mvneta_ethtool_get_eee(struct net_device *dev,
|
||||
struct ethtool_eee *eee)
|
||||
{
|
||||
@@ -4145,8 +4129,6 @@ static const struct ethtool_ops mvneta_e
|
||||
.set_link_ksettings = mvneta_ethtool_set_link_ksettings,
|
||||
.get_wol = mvneta_ethtool_get_wol,
|
||||
.set_wol = mvneta_ethtool_set_wol,
|
||||
- .get_module_info = mvneta_ethtool_get_module_info,
|
||||
- .get_module_eeprom = mvneta_ethtool_get_module_eeprom,
|
||||
.get_eee = mvneta_ethtool_get_eee,
|
||||
.set_eee = mvneta_ethtool_set_eee,
|
||||
};
|
||||
--- a/drivers/net/phy/phylink.c
|
||||
+++ b/drivers/net/phy/phylink.c
|
||||
@@ -1039,34 +1039,6 @@ int phylink_ethtool_set_pauseparam(struc
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(phylink_ethtool_set_pauseparam);
|
||||
|
||||
-int phylink_ethtool_get_module_info(struct phylink *pl,
|
||||
- struct ethtool_modinfo *modinfo)
|
||||
-{
|
||||
- int ret = -EOPNOTSUPP;
|
||||
-
|
||||
- WARN_ON(!lockdep_rtnl_is_held());
|
||||
-
|
||||
- if (pl->sfp_bus)
|
||||
- ret = sfp_get_module_info(pl->sfp_bus, modinfo);
|
||||
-
|
||||
- return ret;
|
||||
-}
|
||||
-EXPORT_SYMBOL_GPL(phylink_ethtool_get_module_info);
|
||||
-
|
||||
-int phylink_ethtool_get_module_eeprom(struct phylink *pl,
|
||||
- struct ethtool_eeprom *ee, u8 *buf)
|
||||
-{
|
||||
- int ret = -EOPNOTSUPP;
|
||||
-
|
||||
- WARN_ON(!lockdep_rtnl_is_held());
|
||||
-
|
||||
- if (pl->sfp_bus)
|
||||
- ret = sfp_get_module_eeprom(pl->sfp_bus, ee, buf);
|
||||
-
|
||||
- return ret;
|
||||
-}
|
||||
-EXPORT_SYMBOL_GPL(phylink_ethtool_get_module_eeprom);
|
||||
-
|
||||
int phylink_init_eee(struct phylink *pl, bool clk_stop_enable)
|
||||
{
|
||||
int ret = -EPROTONOSUPPORT;
|
||||
--- a/drivers/net/phy/sfp-bus.c
|
||||
+++ b/drivers/net/phy/sfp-bus.c
|
||||
@@ -278,6 +278,7 @@ static int sfp_register_bus(struct sfp_b
|
||||
}
|
||||
if (bus->started)
|
||||
bus->socket_ops->start(bus->sfp);
|
||||
+ bus->netdev->sfp_bus = bus;
|
||||
bus->registered = true;
|
||||
return 0;
|
||||
}
|
||||
@@ -292,14 +293,13 @@ static void sfp_unregister_bus(struct sf
|
||||
if (bus->phydev && ops && ops->disconnect_phy)
|
||||
ops->disconnect_phy(bus->upstream);
|
||||
}
|
||||
+ bus->netdev->sfp_bus = NULL;
|
||||
bus->registered = false;
|
||||
}
|
||||
|
||||
|
||||
int sfp_get_module_info(struct sfp_bus *bus, struct ethtool_modinfo *modinfo)
|
||||
{
|
||||
- if (!bus->registered)
|
||||
- return -ENOIOCTLCMD;
|
||||
return bus->socket_ops->module_info(bus->sfp, modinfo);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sfp_get_module_info);
|
||||
@@ -307,8 +307,6 @@ EXPORT_SYMBOL_GPL(sfp_get_module_info);
|
||||
int sfp_get_module_eeprom(struct sfp_bus *bus, struct ethtool_eeprom *ee,
|
||||
u8 *data)
|
||||
{
|
||||
- if (!bus->registered)
|
||||
- return -ENOIOCTLCMD;
|
||||
return bus->socket_ops->module_eeprom(bus->sfp, ee, data);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sfp_get_module_eeprom);
|
||||
--- a/include/linux/netdevice.h
|
||||
+++ b/include/linux/netdevice.h
|
||||
@@ -57,6 +57,7 @@ struct device;
|
||||
struct phy_device;
|
||||
struct dsa_switch_tree;
|
||||
|
||||
+struct sfp_bus;
|
||||
/* 802.11 specific */
|
||||
struct wireless_dev;
|
||||
/* 802.15.4 specific */
|
||||
@@ -1908,6 +1909,7 @@ struct net_device {
|
||||
struct netprio_map __rcu *priomap;
|
||||
#endif
|
||||
struct phy_device *phydev;
|
||||
+ struct sfp_bus *sfp_bus;
|
||||
struct lock_class_key *qdisc_tx_busylock;
|
||||
struct lock_class_key *qdisc_running_key;
|
||||
bool proto_down;
|
||||
--- a/include/linux/phylink.h
|
||||
+++ b/include/linux/phylink.h
|
||||
@@ -125,9 +125,6 @@ void phylink_ethtool_get_pauseparam(stru
|
||||
struct ethtool_pauseparam *);
|
||||
int phylink_ethtool_set_pauseparam(struct phylink *,
|
||||
struct ethtool_pauseparam *);
|
||||
-int phylink_ethtool_get_module_info(struct phylink *, struct ethtool_modinfo *);
|
||||
-int phylink_ethtool_get_module_eeprom(struct phylink *,
|
||||
- struct ethtool_eeprom *, u8 *);
|
||||
int phylink_init_eee(struct phylink *, bool);
|
||||
int phylink_get_eee_err(struct phylink *);
|
||||
int phylink_ethtool_get_eee(struct phylink *, struct ethtool_eee *);
|
||||
--- a/net/core/ethtool.c
|
||||
+++ b/net/core/ethtool.c
|
||||
@@ -22,6 +22,7 @@
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/vmalloc.h>
|
||||
+#include <linux/sfp.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/rtnetlink.h>
|
||||
#include <linux/sched/signal.h>
|
||||
@@ -2190,6 +2191,9 @@ static int __ethtool_get_module_info(str
|
||||
const struct ethtool_ops *ops = dev->ethtool_ops;
|
||||
struct phy_device *phydev = dev->phydev;
|
||||
|
||||
+ if (dev->sfp_bus)
|
||||
+ return sfp_get_module_info(dev->sfp_bus, modinfo);
|
||||
+
|
||||
if (phydev && phydev->drv && phydev->drv->module_info)
|
||||
return phydev->drv->module_info(phydev, modinfo);
|
||||
|
||||
@@ -2224,6 +2228,9 @@ static int __ethtool_get_module_eeprom(s
|
||||
const struct ethtool_ops *ops = dev->ethtool_ops;
|
||||
struct phy_device *phydev = dev->phydev;
|
||||
|
||||
+ if (dev->sfp_bus)
|
||||
+ return sfp_get_module_eeprom(dev->sfp_bus, ee, data);
|
||||
+
|
||||
if (phydev && phydev->drv && phydev->drv->module_eeprom)
|
||||
return phydev->drv->module_eeprom(phydev, ee, data);
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
From 883dc66755313e133a787eba4dfde313fe33525b Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Fri, 14 Apr 2017 16:41:55 +0100
|
||||
Subject: sfp: use netdev sfp_bus for start/stop
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
drivers/net/phy/phylink.c | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/net/phy/phylink.c
|
||||
+++ b/drivers/net/phy/phylink.c
|
||||
@@ -755,8 +755,8 @@ void phylink_start(struct phylink *pl)
|
||||
clear_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
|
||||
phylink_run_resolve(pl);
|
||||
|
||||
- if (pl->sfp_bus)
|
||||
- sfp_upstream_start(pl->sfp_bus);
|
||||
+ if (pl->netdev->sfp_bus)
|
||||
+ sfp_upstream_start(pl->netdev->sfp_bus);
|
||||
if (pl->phydev)
|
||||
phy_start(pl->phydev);
|
||||
}
|
||||
@@ -768,8 +768,8 @@ void phylink_stop(struct phylink *pl)
|
||||
|
||||
if (pl->phydev)
|
||||
phy_stop(pl->phydev);
|
||||
- if (pl->sfp_bus)
|
||||
- sfp_upstream_stop(pl->sfp_bus);
|
||||
+ if (pl->netdev->sfp_bus)
|
||||
+ sfp_upstream_stop(pl->netdev->sfp_bus);
|
||||
|
||||
set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
|
||||
flush_work(&pl->resolve);
|
|
@ -0,0 +1,131 @@
|
|||
From 4a4aca08b11501cb1b2c509113bbb65eb66a1f45 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Fri, 14 Apr 2017 14:21:25 +0100
|
||||
Subject: sfp: hack: allow marvell 10G phy support to use SFP
|
||||
|
||||
Allow the Marvell 10G PHY to register with the SFP bus, so that SFP+
|
||||
cages can work. This bypasses phylink, meaning that socket status
|
||||
is not taken into account for the link state. Also, the tx-disable
|
||||
signal must be commented out in DT for this to work...
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
drivers/net/phy/marvell10g.c | 54 +++++++++++++++++++++++++++++++++++++++++++-
|
||||
1 file changed, 53 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/net/phy/marvell10g.c
|
||||
+++ b/drivers/net/phy/marvell10g.c
|
||||
@@ -15,8 +15,10 @@
|
||||
* If both the fiber and copper ports are connected, the first to gain
|
||||
* link takes priority and the other port is completely locked out.
|
||||
*/
|
||||
+#include <linux/of.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/marvell_phy.h>
|
||||
+#include <linux/sfp.h>
|
||||
|
||||
enum {
|
||||
MV_PCS_BASE_T = 0x0000,
|
||||
@@ -38,6 +40,11 @@ enum {
|
||||
MV_AN_RESULT_SPD_10000 = BIT(15),
|
||||
};
|
||||
|
||||
+struct mv3310_priv {
|
||||
+ struct device_node *sfp_node;
|
||||
+ struct sfp_bus *sfp_bus;
|
||||
+};
|
||||
+
|
||||
static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
|
||||
u16 mask, u16 bits)
|
||||
{
|
||||
@@ -56,17 +63,52 @@ static int mv3310_modify(struct phy_devi
|
||||
return ret < 0 ? ret : 1;
|
||||
}
|
||||
|
||||
+static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
|
||||
+{
|
||||
+ struct phy_device *phydev = upstream;
|
||||
+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
|
||||
+
|
||||
+ if (sfp_parse_interface(priv->sfp_bus, id) != PHY_INTERFACE_MODE_10GKR) {
|
||||
+ dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct sfp_upstream_ops mv3310_sfp_ops = {
|
||||
+ .module_insert = mv3310_sfp_insert,
|
||||
+};
|
||||
+
|
||||
static int mv3310_probe(struct phy_device *phydev)
|
||||
{
|
||||
+ struct mv3310_priv *priv;
|
||||
u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
|
||||
|
||||
if (!phydev->is_c45 ||
|
||||
(phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
|
||||
return -ENODEV;
|
||||
|
||||
+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ dev_set_drvdata(&phydev->mdio.dev, priv);
|
||||
+
|
||||
+ if (phydev->mdio.dev.of_node)
|
||||
+ priv->sfp_node = of_parse_phandle(phydev->mdio.dev.of_node,
|
||||
+ "sfp", 0);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void mv3310_remove(struct phy_device *phydev)
|
||||
+{
|
||||
+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
|
||||
+
|
||||
+ if (priv->sfp_bus)
|
||||
+ sfp_unregister_upstream(priv->sfp_bus);
|
||||
+}
|
||||
+
|
||||
/*
|
||||
* Resetting the MV88X3310 causes it to become non-responsive. Avoid
|
||||
* setting the reset bit(s).
|
||||
@@ -78,6 +120,7 @@ static int mv3310_soft_reset(struct phy_
|
||||
|
||||
static int mv3310_config_init(struct phy_device *phydev)
|
||||
{
|
||||
+ struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
|
||||
__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
|
||||
u32 mask;
|
||||
int val;
|
||||
@@ -166,6 +209,14 @@ static int mv3310_config_init(struct phy
|
||||
phydev->supported &= mask;
|
||||
phydev->advertising &= phydev->supported;
|
||||
|
||||
+ /* Would be nice to do this in the probe function, but unfortunately,
|
||||
+ * phylib doesn't have phydev->attached_dev set there.
|
||||
+ */
|
||||
+ if (priv->sfp_node && !priv->sfp_bus)
|
||||
+ priv->sfp_bus = sfp_register_upstream(priv->sfp_node,
|
||||
+ phydev->attached_dev,
|
||||
+ phydev, &mv3310_sfp_ops);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -349,12 +400,13 @@ static struct phy_driver mv3310_drivers[
|
||||
SUPPORTED_FIBRE |
|
||||
SUPPORTED_10000baseT_Full |
|
||||
SUPPORTED_Backplane,
|
||||
- .probe = mv3310_probe,
|
||||
.soft_reset = mv3310_soft_reset,
|
||||
.config_init = mv3310_config_init,
|
||||
+ .probe = mv3310_probe,
|
||||
.config_aneg = mv3310_config_aneg,
|
||||
.aneg_done = mv3310_aneg_done,
|
||||
.read_status = mv3310_read_status,
|
||||
+ .remove = mv3310_remove,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
From 3344f73509a34d2124b716efc79cd9787773018b Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Fri, 14 Apr 2017 20:17:13 +0100
|
||||
Subject: sfp: add sfp+ compatible
|
||||
|
||||
Add a compatible for SFP+ cages. SFP+ cages are backwards compatible,
|
||||
but the ethernet device behind them may not support the slower speeds
|
||||
of SFP modules.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
drivers/net/phy/sfp.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/net/phy/sfp.c
|
||||
+++ b/drivers/net/phy/sfp.c
|
||||
@@ -1135,6 +1135,7 @@ static int sfp_remove(struct platform_de
|
||||
|
||||
static const struct of_device_id sfp_of_match[] = {
|
||||
{ .compatible = "sff,sfp", },
|
||||
+ { .compatible = "sff,sfp+", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sfp_of_match);
|
|
@ -0,0 +1,87 @@
|
|||
From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Tue, 29 Nov 2016 10:15:45 +0000
|
||||
Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 +
|
||||
.../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++
|
||||
2 files changed, 63 insertions(+)
|
||||
create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
||||
+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
||||
@@ -48,6 +48,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-388-clearfog.dtsi"
|
||||
+#include "armada-38x-solidrun-microsom-emmc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SolidRun Clearfog Base A1";
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
|
||||
@@ -0,0 +1,62 @@
|
||||
+/*
|
||||
+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
|
||||
+ *
|
||||
+ * Copyright (C) 2015 Russell King
|
||||
+ *
|
||||
+ * This board is in development; the contents of this file work with
|
||||
+ * the A1 rev 2.0 of the board, which does not represent final
|
||||
+ * production board. Things will change, don't expect this file to
|
||||
+ * remain compatible info the future.
|
||||
+ *
|
||||
+ * This file is dual-licensed: you can use it either under the terms
|
||||
+ * of the GPL or the X11 license, at your option. Note that this dual
|
||||
+ * licensing only applies to this file, and not this project as a
|
||||
+ * whole.
|
||||
+ *
|
||||
+ * a) This file is free software; you can redistribute it and/or
|
||||
+ * modify it under the terms of the GNU General Public License
|
||||
+ * version 2 as published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This file is distributed in the hope that it will be useful
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ *
|
||||
+ * Or, alternatively
|
||||
+ *
|
||||
+ * b) Permission is hereby granted, free of charge, to any person
|
||||
+ * obtaining a copy of this software and associated documentation
|
||||
+ * files (the "Software"), to deal in the Software without
|
||||
+ * restriction, including without limitation the rights to use
|
||||
+ * copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
+ * sell copies of the Software, and to permit persons to whom the
|
||||
+ * Software is furnished to do so, subject to the following
|
||||
+ * conditions:
|
||||
+ *
|
||||
+ * The above copyright notice and this permission notice shall be
|
||||
+ * included in all copies or substantial portions of the Software.
|
||||
+ *
|
||||
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
+ * OTHER DEALINGS IN THE SOFTWARE.
|
||||
+ */
|
||||
+/ {
|
||||
+ soc {
|
||||
+ internal-regs {
|
||||
+ sdhci@d8000 {
|
||||
+ bus-width = <4>;
|
||||
+ no-1-8-v;
|
||||
+ non-removable;
|
||||
+ pinctrl-0 = <µsom_sdhci_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "okay";
|
||||
+ wp-inverted;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
|
@ -0,0 +1,42 @@
|
|||
From 6e127081e669cf163a818dc04d590790e4ed9527 Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
Date: Tue, 29 Nov 2016 20:06:44 +0000
|
||||
Subject: ARM: dts: armada388-clearfog: increase speed of i2c0 to 400kHz
|
||||
|
||||
All the devices on I2C0 support fast mode, so increase the bus speed
|
||||
to match. The Armada 388 is known to have a timing issue when in
|
||||
standard mode, which we believe causes the ficticious device at 0x64
|
||||
to appear.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
arch/arm/boot/dts/armada-388-clearfog.dtsi | 7 ++-----
|
||||
1 file changed, 2 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
|
||||
@@ -143,8 +143,7 @@
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
- /* Is there anything on this? */
|
||||
- clock-frequency = <100000>;
|
||||
+ clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
@@ -239,13 +238,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
- /* The MCP3021 is 100kHz clock only */
|
||||
+ /* The MCP3021 supports standard and fast modes */
|
||||
mikrobus_adc: mcp3021@4c {
|
||||
compatible = "microchip,mcp3021";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
-
|
||||
- /* Also something at 0x64 */
|
||||
};
|
||||
|
||||
&i2c1 {
|
|
@ -0,0 +1,81 @@
|
|||
From 74fa68669c88f73bceff523cb764297b7d1e132b Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Tue, 29 Nov 2016 10:13:44 +0000
|
||||
Subject: ARM: dts: armada388-clearfog: add SFP module support
|
||||
|
||||
Add SFP module support for Clearfog using the SFP phylink support.
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
---
|
||||
arch/arm/boot/dts/armada-388-clearfog.dtsi | 44 ++++++++----------------------
|
||||
1 file changed, 11 insertions(+), 33 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
|
||||
@@ -117,6 +117,15 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ sfp: sfp {
|
||||
+ compatible = "sff,sfp";
|
||||
+ i2c-bus = <&i2c1>;
|
||||
+ los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
|
||||
+ moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
|
||||
+ tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
|
||||
+ tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
};
|
||||
|
||||
ð1 {
|
||||
@@ -133,13 +142,10 @@
|
||||
bm,pool-long = <3>;
|
||||
bm,pool-short = <1>;
|
||||
buffer-manager = <&bm>;
|
||||
+ managed = "in-band-status";
|
||||
phy-mode = "sgmii";
|
||||
+ sfp = <&sfp>;
|
||||
status = "okay";
|
||||
-
|
||||
- fixed-link {
|
||||
- speed = <1000>;
|
||||
- full-duplex;
|
||||
- };
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
@@ -208,34 +214,6 @@
|
||||
output-low;
|
||||
line-name = "m.2 devslp";
|
||||
};
|
||||
- sfp_los {
|
||||
- /* SFP loss of signal */
|
||||
- gpio-hog;
|
||||
- gpios = <12 GPIO_ACTIVE_HIGH>;
|
||||
- input;
|
||||
- line-name = "sfp-los";
|
||||
- };
|
||||
- sfp_tx_fault {
|
||||
- /* SFP laser fault */
|
||||
- gpio-hog;
|
||||
- gpios = <13 GPIO_ACTIVE_HIGH>;
|
||||
- input;
|
||||
- line-name = "sfp-tx-fault";
|
||||
- };
|
||||
- sfp_tx_disable {
|
||||
- /* SFP transmit disable */
|
||||
- gpio-hog;
|
||||
- gpios = <14 GPIO_ACTIVE_HIGH>;
|
||||
- output-low;
|
||||
- line-name = "sfp-tx-disable";
|
||||
- };
|
||||
- sfp_mod_def0 {
|
||||
- /* SFP module present */
|
||||
- gpio-hog;
|
||||
- gpios = <15 GPIO_ACTIVE_LOW>;
|
||||
- input;
|
||||
- line-name = "sfp-mod-def0";
|
||||
- };
|
||||
};
|
||||
|
||||
/* The MCP3021 supports standard and fast modes */
|
|
@ -0,0 +1,124 @@
|
|||
From 09a0122c74ec076e08512f1b00b7ccb8a450282f Mon Sep 17 00:00:00 2001
|
||||
From: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
Date: Tue, 29 Nov 2016 10:15:43 +0000
|
||||
Subject: ARM: dts: armada388-clearfog: document MPP usage
|
||||
|
||||
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||||
---
|
||||
arch/arm/boot/dts/armada-388-clearfog-base.dts | 51 ++++++++++++++++++++++++++
|
||||
arch/arm/boot/dts/armada-388-clearfog.dts | 50 +++++++++++++++++++++++++
|
||||
2 files changed, 101 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
||||
+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
||||
@@ -108,3 +108,54 @@
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
+
|
||||
+/*
|
||||
+MPP
|
||||
+18: pu gpio pca9655 int
|
||||
+19: gpio phy reset
|
||||
+20: pu gpio sd0 detect
|
||||
+21: sd0:cmd
|
||||
+22: pd gpio mikro int
|
||||
+23:
|
||||
+
|
||||
+24: ua1:rxd mikro rx
|
||||
+25: ua1:txd mikro tx
|
||||
+26: pu i2c1:sck
|
||||
+27: pu i2c1:sda
|
||||
+28: sd0:clk
|
||||
+29: pd gpio mikro rst
|
||||
+30:
|
||||
+31:
|
||||
+
|
||||
+32:
|
||||
+33:
|
||||
+34:
|
||||
+35:
|
||||
+36:
|
||||
+37: sd0:d3
|
||||
+38: sd0:d0
|
||||
+39: sd0:d1
|
||||
+
|
||||
+40: sd0:d2
|
||||
+41:
|
||||
+42:
|
||||
+43: spi1:cs2 mikro cs
|
||||
+44: gpio rear button sw3
|
||||
+45: ref:clk_out0 phy#0 clock
|
||||
+46: ref:clk_out1 phy#1 clock
|
||||
+47:
|
||||
+
|
||||
+48: gpio J18 spare gpio
|
||||
+49: gpio U10 I2C_IRQ(GNSS)
|
||||
+50: gpio board id?
|
||||
+51:
|
||||
+52:
|
||||
+53:
|
||||
+54: gpio mikro pwm
|
||||
+55:
|
||||
+
|
||||
+56: pu spi1:mosi mikro mosi
|
||||
+57: pd spi1:sck mikro sck
|
||||
+58: spi1:miso mikro miso
|
||||
+59:
|
||||
+*/
|
||||
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
||||
@@ -289,3 +289,53 @@
|
||||
*/
|
||||
pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
|
||||
};
|
||||
+/*
|
||||
++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
|
||||
+MPP18: gpio ? (pca9655 int?)
|
||||
+MPP19: gpio ? (clkreq?)
|
||||
+MPP20: gpio ? (sd0 detect)
|
||||
+MPP21: sd0:cmd x sd0
|
||||
+MPP22: gpio x mikro int
|
||||
+MPP23: gpio x switch irq
|
||||
++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
|
||||
+MPP24: ua1:rxd x mikro rx
|
||||
+MPP25: ua1:txd x mikro tx
|
||||
+MPP26: i2c1:sck x mikro sck
|
||||
+MPP27: i2c1:sda x mikro sda
|
||||
+MPP28: sd0:clk x sd0
|
||||
+MPP29: gpio x mikro rst
|
||||
+MPP30: ge1:txd2 ? (config)
|
||||
+MPP31: ge1:txd3 ? (config)
|
||||
++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
|
||||
+MPP32: ge1:txctl ? (unused)
|
||||
+MPP33: gpio ? (pic_com0)
|
||||
+MPP34: gpio x rear button (pic_com1)
|
||||
+MPP35: gpio ? (pic_com2)
|
||||
+MPP36: gpio ? (unused)
|
||||
+MPP37: sd0:d3 x sd0
|
||||
+MPP38: sd0:d0 x sd0
|
||||
+MPP39: sd0:d1 x sd0
|
||||
++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
|
||||
+MPP40: sd0:d2 x sd0
|
||||
+MPP41: gpio x switch reset
|
||||
+MPP42: gpio ? sw1-1
|
||||
+MPP43: spi1:cs2 x mikro cs
|
||||
+MPP44: sata3:prsnt ? (unused)
|
||||
+MPP45: ref:clk_out0 ?
|
||||
+MPP46: ref:clk_out1 x switch clk
|
||||
+MPP47: 4 ? (unused)
|
||||
++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
|
||||
+MPP48: tdm:pclk
|
||||
+MPP49: tdm:fsync
|
||||
+MPP50: tdm:drx
|
||||
+MPP51: tdm:dtx
|
||||
+MPP52: tdm:int
|
||||
+MPP53: tdm:rst
|
||||
+MPP54: gpio ? (pwm)
|
||||
+MPP55: spi1:cs1 x slic
|
||||
++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
|
||||
+MPP56: spi1:mosi x mikro mosi
|
||||
+MPP57: spi1:sck x mikro sck
|
||||
+MPP58: spi1:miso x mikro miso
|
||||
+MPP59: spi1:cs0 x w25q32
|
||||
+*/
|
Loading…
Reference in a new issue