ath79: fix QCA9557 eth PLL settings
The QCA9557 dtsi is currently missing pll-handle and pll-regs for both eth0 and eth1, therefore PLL settings won't be applied. This commit fixes this behavior. Signed-off-by: David Bauer <mail@david-bauer.net>
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parent
5107ba2374
commit
4b9680f138
1 changed files with 7 additions and 1 deletions
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@ -109,7 +109,7 @@
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pll: pll-controller@18050000 {
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pll: pll-controller@18050000 {
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compatible = "qca,ar9557-pll",
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compatible = "qca,ar9557-pll",
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"qca,qca9550-pll";
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"qca,qca9550-pll", "syscon";
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reg = <0x18050000 0x50>;
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reg = <0x18050000 0x50>;
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#clock-cells = <1>;
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#clock-cells = <1>;
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@ -295,6 +295,9 @@
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ð0 {
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ð0 {
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compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
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compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
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pll-reg = <0 0x28 0>;
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pll-handle = <&pll>;
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pll-data = <0x82000101 0x80000101 0x80001313>;
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pll-data = <0x82000101 0x80000101 0x80001313>;
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phy-mode = "rgmii";
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phy-mode = "rgmii";
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@ -310,6 +313,9 @@
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ð1 {
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ð1 {
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compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
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compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
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pll-reg = <0 0x48 0>;
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pll-handle = <&pll>;
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pll-data = <0x82000101 0x80000101 0x80001313>;
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pll-data = <0x82000101 0x80000101 0x80001313>;
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phy-mode = "sgmii";
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phy-mode = "sgmii";
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