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kernel: fix BCM54612E PHY support

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This backports upstream commit 62e13097c46c ("net: phy: broadcom: rehook
BCM54612E specific init")

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
This commit is contained in:
Rafał Miłecki 2017-02-01 20:53:15 +01:00
parent 06bb0a89b7
commit 49f9c06fde
1 changed files with 81 additions and 14 deletions
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95
target/linux/generic/patches-4.4/078-0004-net-phy-pick-Broadcom-drivers-updates-from-net-next-.patch
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@ -82,7 +82,7 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
{ PHY_ID_BCM7346, 0xfffffff0, }, { PHY_ID_BCM7346, 0xfffffff0, },
--- a/drivers/net/phy/broadcom.c --- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c
@@ -30,6 +30,22 @@ MODULE_DESCRIPTION("Broadcom PHY driver" @@ -30,6 +30,50 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
MODULE_AUTHOR("Maciej W. Rozycki"); MODULE_AUTHOR("Maciej W. Rozycki");
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
@ -101,11 +101,39 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+ +
+ return 0; + return 0;
+} +}
+
+static int bcm54612e_config_init(struct phy_device *phydev)
+{
+ /* Clear TX internal delay unless requested. */
+ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
+ (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
+ /* Disable TXD to GTXCLK clock delay (default set) */
+ /* Bit 9 is the only field in shadow register 00011 */
+ bcm_phy_write_shadow(phydev, 0x03, 0);
+ }
+
+ /* Clear RX internal delay unless requested. */
+ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
+ (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
+ u16 reg;
+
+ reg = bcm54xx_auxctl_read(phydev,
+ MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
+ /* Disable RXD to RXC delay (default set) */
+ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
+ /* Clear shadow selector field */
+ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
+ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
+ MII_BCM54XX_AUXCTL_MISC_WREN | reg);
+ }
+
+ return 0;
+}
+ +
static int bcm54810_config(struct phy_device *phydev) static int bcm54810_config(struct phy_device *phydev)
{ {
int rc, val; int rc, val;
@@ -230,7 +246,11 @@ static int bcm54xx_config_init(struct ph @@ -230,7 +274,15 @@ static int bcm54xx_config_init(struct ph
(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
bcm54xx_adjust_rxrefclk(phydev); bcm54xx_adjust_rxrefclk(phydev);
@ -114,27 +142,57 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+ err = bcm54210e_config_init(phydev); + err = bcm54210e_config_init(phydev);
+ if (err) + if (err)
+ return err; + return err;
+ } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
+ err = bcm54612e_config_init(phydev);
+ if (err)
+ return err;
+ } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) { + } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
err = bcm54810_config(phydev); err = bcm54810_config(phydev);
if (err) if (err)
return err; return err;
@@ -395,12 +415,10 @@ static int bcm54612e_config_aneg(struct @@ -375,41 +427,6 @@ static int bcm5481_config_aneg(struct ph
(phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) { return ret;
u16 reg; }
-static int bcm54612e_config_aneg(struct phy_device *phydev)
-{
- int ret;
-
- /* First, auto-negotiate. */
- ret = genphy_config_aneg(phydev);
-
- /* Clear TX internal delay unless requested. */
- if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
- (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
- /* Disable TXD to GTXCLK clock delay (default set) */
- /* Bit 9 is the only field in shadow register 00011 */
- bcm_phy_write_shadow(phydev, 0x03, 0);
- }
-
- /* Clear RX internal delay unless requested. */
- if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
- (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
- u16 reg;
-
- /* Errata: reads require filling in the write selector field */ - /* Errata: reads require filling in the write selector field */
- bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, - bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
- MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC); - MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
- reg = phy_read(phydev, MII_BCM54XX_AUX_CTL); - reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
+ reg = bcm54xx_auxctl_read(phydev, - /* Disable RXD to RXC delay (default set) */
+ MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
/* Disable RXD to RXC delay (default set) */
- reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW; - reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
+ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; - /* Clear shadow selector field */
/* Clear shadow selector field */ - reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK; - bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, - MII_BCM54XX_AUXCTL_MISC_WREN | reg);
@@ -548,6 +566,19 @@ static struct phy_driver broadcom_driver - }
-
- return ret;
-}
-
static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
{
int val;
@@ -548,6 +565,19 @@ static struct phy_driver broadcom_driver
.config_intr = bcm_phy_config_intr, .config_intr = bcm_phy_config_intr,
.driver = { .owner = THIS_MODULE }, .driver = { .owner = THIS_MODULE },
}, { }, {
@ -154,7 +212,16 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
.phy_id = PHY_ID_BCM5461, .phy_id = PHY_ID_BCM5461,
.phy_id_mask = 0xfffffff0, .phy_id_mask = 0xfffffff0,
.name = "Broadcom BCM5461", .name = "Broadcom BCM5461",
@@ -708,6 +739,7 @@ module_phy_driver(broadcom_drivers); @@ -568,7 +598,7 @@ static struct phy_driver broadcom_driver
SUPPORTED_Pause | SUPPORTED_Asym_Pause,
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
.config_init = bcm54xx_config_init,
- .config_aneg = bcm54612e_config_aneg,
+ .config_aneg = genphy_config_aneg,
.read_status = genphy_read_status,
.ack_interrupt = bcm_phy_ack_intr,
.config_intr = bcm_phy_config_intr,
@@ -708,6 +738,7 @@ module_phy_driver(broadcom_drivers);
static struct mdio_device_id __maybe_unused broadcom_tbl[] = { static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
{ PHY_ID_BCM5411, 0xfffffff0 }, { PHY_ID_BCM5411, 0xfffffff0 },
{ PHY_ID_BCM5421, 0xfffffff0 }, { PHY_ID_BCM5421, 0xfffffff0 },