ipq806x: fix pcie reset gpio definions and move them to the common .dtsi file
Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 47544
This commit is contained in:
Felix Fietkau
parent
575413a779
commit
49d4a980d7
22 changed files with 170 additions and 266 deletions
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@ -15,59 +15,59 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -35,6 +35,24 @@
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bias-disable;
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};
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+ pcie0_pins: pcie0_pinmux {
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+ mux {
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+ pins = "gpio3";
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+ function = "pcie1_rst";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
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+ };
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+
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+ pcie1_pins: pcie1_pinmux {
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+ mux {
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+ pins = "gpio48";
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+ function = "pcie2_rst";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
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+ };
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+
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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@@ -115,5 +133,21 @@
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@@ -115,5 +115,15 @@
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usb30@1 {
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status = "ok";
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};
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+
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 3 0>;
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+ phy-tx0-term-offset = <7>;
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 48 0>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+ phy-tx0-term-offset = <7>;
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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@@ -30,6 +30,33 @@
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bias-disable;
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};
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@@ -128,5 +128,17 @@
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usb30@1 {
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status = "ok";
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};
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+
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ };
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+
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+ pcie2: pci@1b900000 {
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+ status = "ok";
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -3,6 +3,9 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm IPQ8064";
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@@ -83,6 +86,33 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 32 0x4>;
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+
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+ pcie0_pins: pcie0_pinmux {
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+ mux {
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+ pins = "gpio3";
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@ -94,49 +94,10 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ bias-disable;
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+ };
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+ };
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+
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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@@ -128,5 +155,26 @@
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usb30@1 {
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status = "ok";
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};
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+
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 3 0>;
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 48 0>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie2: pci@1b900000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 63 0>;
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-names = "default";
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -3,6 +3,8 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm IPQ8064";
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@@ -311,6 +313,129 @@
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intc: interrupt-controller@2000000 {
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@@ -311,6 +341,144 @@
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reg = <0x01200600 0x100>;
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};
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@ -178,6 +139,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ <&gcc PCIE_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+
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+ perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
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+
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+ status = "disabled";
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+ };
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+
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@ -219,6 +185,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ <&gcc PCIE_1_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+
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+ perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
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+
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+ status = "disabled";
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+ };
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+
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@ -260,6 +231,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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+ <&gcc PCIE_2_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-names = "default";
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+
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+ perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
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+
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+ status = "disabled";
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+ };
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+
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@ -1,6 +1,6 @@
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -341,15 +341,21 @@
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@@ -369,15 +369,21 @@
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clocks = <&gcc PCIE_A_CLK>,
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<&gcc PCIE_H_CLK>,
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@ -24,9 +24,9 @@
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+ <&gcc PCIE_EXT_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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status = "disabled";
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};
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@@ -382,15 +388,21 @@
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pinctrl-0 = <&pcie0_pins>;
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pinctrl-names = "default";
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@@ -415,15 +421,21 @@
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clocks = <&gcc PCIE_1_A_CLK>,
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<&gcc PCIE_1_H_CLK>,
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@ -50,9 +50,9 @@
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+ <&gcc PCIE_1_EXT_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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status = "disabled";
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};
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@@ -423,15 +435,21 @@
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pinctrl-0 = <&pcie1_pins>;
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pinctrl-names = "default";
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@@ -461,15 +473,21 @@
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clocks = <&gcc PCIE_2_A_CLK>,
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<&gcc PCIE_2_H_CLK>,
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@ -76,5 +76,5 @@
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+ <&gcc PCIE_2_EXT_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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status = "disabled";
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};
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-names = "default";
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@ -8,7 +8,7 @@
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#include <dt-bindings/soc/qcom,gsbi.h>
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#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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@@ -76,6 +77,63 @@
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@@ -77,6 +78,63 @@
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ranges;
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compatible = "simple-bus";
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@ -72,7 +72,7 @@
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qcom_pinmux: pinmux@800000 {
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compatible = "qcom,ipq8064-pinctrl";
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reg = <0x800000 0x4000>;
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@@ -120,6 +178,12 @@
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@@ -148,6 +206,12 @@
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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};
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@ -1,6 +1,6 @@
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -24,6 +24,11 @@
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@@ -25,6 +25,11 @@
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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@ -12,7 +12,7 @@
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};
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cpu@1 {
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@@ -34,11 +39,24 @@
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@@ -35,11 +40,24 @@
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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@ -37,7 +37,7 @@
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};
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};
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@@ -71,6 +89,46 @@
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@@ -72,6 +90,46 @@
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};
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};
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@ -84,7 +84,7 @@
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@@ -171,11 +229,13 @@
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@@ -199,11 +257,13 @@
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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@ -13,7 +13,7 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -662,6 +662,26 @@
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@@ -705,6 +705,26 @@
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};
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};
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@ -26,7 +26,7 @@ arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -682,6 +682,22 @@
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@@ -725,6 +725,22 @@
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status = "disabled";
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};
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@ -25,7 +25,7 @@ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -61,6 +61,31 @@
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@@ -43,6 +43,31 @@
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bias-none;
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};
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};
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@ -57,8 +57,8 @@ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
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};
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gsbi@16300000 {
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@@ -149,5 +174,19 @@
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pinctrl-names = "default";
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@@ -125,5 +150,19 @@
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status = "ok";
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phy-tx0-term-offset = <7>;
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};
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+
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@ -1,6 +1,6 @@
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -183,6 +183,8 @@
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@@ -159,6 +159,8 @@
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nand-ecc-strength = <4>;
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nand-bus-width = <8>;
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@ -22,7 +22,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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qcom-msm8974-sony-xperia-honami.dtb
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
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@@ -0,0 +1,362 @@
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@@ -0,0 +1,338 @@
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+#include "qcom-ipq8064-v1.0.dtsi"
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+
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+#include <dt-bindings/input/input.h>
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@ -64,24 +64,6 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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+ bias-disable;
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+ };
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+
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+ pcie0_pins: pcie0_pinmux {
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+ mux {
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+ pins = "gpio3";
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+ function = "pcie1_rst";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
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+ };
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+
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+ pcie1_pins: pcie1_pinmux {
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+ mux {
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+ pins = "gpio48";
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+ function = "pcie2_rst";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
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+ };
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+
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+ nand_pins: nand_pins {
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+ mux {
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+ pins = "gpio34", "gpio35", "gpio36",
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@ -173,16 +155,10 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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+
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 3 0>;
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 48 0>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ nand@1ac00000 {
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@ -22,7 +22,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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chosen {
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@@ -86,6 +87,15 @@
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@@ -68,6 +69,15 @@
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bias-bus-hold;
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};
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};
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@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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gsbi@16300000 {
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@@ -186,6 +196,34 @@
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@@ -162,6 +172,34 @@
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linux,part-probe = "qcom-smem";
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};
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@ -83,7 +83,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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chosen {
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@@ -65,6 +66,15 @@
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@@ -38,6 +39,15 @@
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bias-none;
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};
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};
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@ -99,9 +99,9 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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};
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gsbi2: gsbi@12480000 {
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@@ -176,5 +186,44 @@
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-names = "default";
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@@ -140,5 +150,44 @@
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pcie2: pci@1b900000 {
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status = "ok";
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};
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+
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+ mdio0: mdio {
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@ -12,7 +12,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -96,6 +96,16 @@
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@@ -78,6 +78,16 @@
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bias-disable;
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};
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};
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|
|
@ -29,7 +29,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
@@ -224,6 +234,27 @@
|
||||
@@ -200,6 +210,27 @@
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
|
@ -59,7 +59,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
|
||||
@@ -75,6 +75,14 @@
|
||||
@@ -48,6 +48,14 @@
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
|
@ -74,7 +74,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
};
|
||||
|
||||
gsbi2: gsbi@12480000 {
|
||||
@@ -225,5 +233,40 @@
|
||||
@@ -189,5 +197,40 @@
|
||||
reg = <7>;
|
||||
};
|
||||
};
|
||||
|
|
@ -117,7 +117,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -698,6 +698,92 @@
|
||||
@@ -741,6 +741,92 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -15,59 +15,59 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
||||
@@ -35,6 +35,24 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
+ pcie0_pins: pcie0_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio3";
|
||||
+ function = "pcie1_rst";
|
||||
+ drive-strength = <12>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie1_pins: pcie1_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio48";
|
||||
+ function = "pcie2_rst";
|
||||
+ drive-strength = <12>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
@@ -91,5 +109,21 @@
|
||||
@@ -91,5 +91,15 @@
|
||||
sata@29000000 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ pcie0: pci@1b500000 {
|
||||
+ status = "ok";
|
||||
+ reset-gpio = <&qcom_pinmux 3 0>;
|
||||
+ pinctrl-0 = <&pcie0_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ phy-tx0-term-offset = <7>;
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pci@1b700000 {
|
||||
+ status = "ok";
|
||||
+ reset-gpio = <&qcom_pinmux 48 0>;
|
||||
+ pinctrl-0 = <&pcie1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ phy-tx0-term-offset = <7>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
|
||||
@@ -30,6 +30,33 @@
|
||||
bias-disable;
|
||||
};
|
||||
@@ -128,5 +128,17 @@
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ pcie0: pci@1b500000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pci@1b700000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
+
|
||||
+ pcie2: pci@1b900000 {
|
||||
+ status = "ok";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -4,6 +4,9 @@
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
|
||||
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm IPQ8064";
|
||||
@@ -99,6 +102,33 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 16 0x4>;
|
||||
+
|
||||
+ pcie0_pins: pcie0_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio3";
|
||||
|
|
@ -94,49 +94,10 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
@@ -128,5 +155,26 @@
|
||||
usb30@1 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ pcie0: pci@1b500000 {
|
||||
+ status = "ok";
|
||||
+ reset-gpio = <&qcom_pinmux 3 0>;
|
||||
+ pinctrl-0 = <&pcie0_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pci@1b700000 {
|
||||
+ status = "ok";
|
||||
+ reset-gpio = <&qcom_pinmux 48 0>;
|
||||
+ pinctrl-0 = <&pcie1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
+
|
||||
+ pcie2: pci@1b900000 {
|
||||
+ status = "ok";
|
||||
+ reset-gpio = <&qcom_pinmux 63 0>;
|
||||
+ pinctrl-0 = <&pcie2_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -4,6 +4,8 @@
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
|
||||
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm IPQ8064";
|
||||
@@ -333,6 +335,129 @@
|
||||
intc: interrupt-controller@2000000 {
|
||||
@@ -333,6 +363,144 @@
|
||||
compatible = "syscon";
|
||||
reg = <0x01200600 0x100>;
|
||||
};
|
||||
|
|
@ -179,6 +140,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
+ <&gcc PCIE_PHY_RESET>;
|
||||
+ reset-names = "axi", "ahb", "por", "pci", "phy";
|
||||
+
|
||||
+ pinctrl-0 = <&pcie0_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
|
|
@ -220,6 +186,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
+ <&gcc PCIE_1_PHY_RESET>;
|
||||
+ reset-names = "axi", "ahb", "por", "pci", "phy";
|
||||
+
|
||||
+ pinctrl-0 = <&pcie1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
|
|
@ -261,6 +232,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
+ <&gcc PCIE_2_PHY_RESET>;
|
||||
+ reset-names = "axi", "ahb", "por", "pci", "phy";
|
||||
+
|
||||
+ pinctrl-0 = <&pcie2_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -364,15 +364,21 @@
|
||||
@@ -392,15 +392,21 @@
|
||||
|
||||
clocks = <&gcc PCIE_A_CLK>,
|
||||
<&gcc PCIE_H_CLK>,
|
||||
|
|
@ -24,9 +24,9 @@
|
|||
+ <&gcc PCIE_EXT_RESET>;
|
||||
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -405,15 +411,21 @@
|
||||
pinctrl-0 = <&pcie0_pins>;
|
||||
pinctrl-names = "default";
|
||||
@@ -438,15 +444,21 @@
|
||||
|
||||
clocks = <&gcc PCIE_1_A_CLK>,
|
||||
<&gcc PCIE_1_H_CLK>,
|
||||
|
|
@ -50,9 +50,9 @@
|
|||
+ <&gcc PCIE_1_EXT_RESET>;
|
||||
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -446,15 +458,21 @@
|
||||
pinctrl-0 = <&pcie1_pins>;
|
||||
pinctrl-names = "default";
|
||||
@@ -484,15 +496,21 @@
|
||||
|
||||
clocks = <&gcc PCIE_2_A_CLK>,
|
||||
<&gcc PCIE_2_H_CLK>,
|
||||
|
|
@ -76,5 +76,5 @@
|
|||
+ <&gcc PCIE_2_EXT_RESET>;
|
||||
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
pinctrl-0 = <&pcie2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
|
||||
@@ -92,6 +93,63 @@
|
||||
@@ -93,6 +94,63 @@
|
||||
reg-names = "lpass-lpaif";
|
||||
};
|
||||
|
||||
|
|
@ -72,7 +72,7 @@
|
|||
qcom_pinmux: pinmux@800000 {
|
||||
compatible = "qcom,ipq8064-pinctrl";
|
||||
reg = <0x800000 0x4000>;
|
||||
@@ -136,6 +194,12 @@
|
||||
@@ -164,6 +222,12 @@
|
||||
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -25,6 +25,11 @@
|
||||
@@ -26,6 +26,11 @@
|
||||
next-level-cache = <&L2>;
|
||||
qcom,acc = <&acc0>;
|
||||
qcom,saw = <&saw0>;
|
||||
|
|
@ -12,7 +12,7 @@
|
|||
};
|
||||
|
||||
cpu@1 {
|
||||
@@ -35,11 +40,24 @@
|
||||
@@ -36,11 +41,24 @@
|
||||
next-level-cache = <&L2>;
|
||||
qcom,acc = <&acc1>;
|
||||
qcom,saw = <&saw1>;
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
@@ -72,6 +90,46 @@
|
||||
@@ -73,6 +91,46 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -84,7 +84,7 @@
|
|||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@@ -187,11 +245,13 @@
|
||||
@@ -215,11 +273,13 @@
|
||||
acc0: clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ Signed-off-by: Andy Gross <agross@codeaurora.org>
|
|||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -600,6 +600,26 @@
|
||||
@@ -643,6 +643,26 @@
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
|
|||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -620,6 +620,22 @@
|
||||
@@ -663,6 +663,22 @@
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
|
|||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
||||
@@ -61,6 +61,28 @@
|
||||
@@ -43,6 +43,28 @@
|
||||
bias-none;
|
||||
};
|
||||
};
|
||||
|
|
@ -54,8 +54,8 @@ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
|
|||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
@@ -125,5 +147,19 @@
|
||||
pinctrl-names = "default";
|
||||
@@ -101,5 +123,19 @@
|
||||
status = "ok";
|
||||
phy-tx0-term-offset = <7>;
|
||||
};
|
||||
+
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
||||
@@ -156,6 +156,8 @@
|
||||
@@ -132,6 +132,8 @@
|
||||
|
||||
nand-ecc-strength = <4>;
|
||||
nand-bus-width = <8>;
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
qcom-msm8974-sony-xperia-honami.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
|
||||
@@ -0,0 +1,362 @@
|
||||
@@ -0,0 +1,338 @@
|
||||
+#include "qcom-ipq8064-v1.0.dtsi"
|
||||
+
|
||||
+#include <dt-bindings/input/input.h>
|
||||
|
|
@ -64,24 +64,6 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ pcie0_pins: pcie0_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio3";
|
||||
+ function = "pcie1_rst";
|
||||
+ drive-strength = <12>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie1_pins: pcie1_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio48";
|
||||
+ function = "pcie2_rst";
|
||||
+ drive-strength = <12>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ nand_pins: nand_pins {
|
||||
+ mux {
|
||||
+ pins = "gpio34", "gpio35", "gpio36",
|
||||
|
|
@ -173,16 +155,10 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
|
|||
+
|
||||
+ pcie0: pci@1b500000 {
|
||||
+ status = "ok";
|
||||
+ reset-gpio = <&qcom_pinmux 3 0>;
|
||||
+ pinctrl-0 = <&pcie0_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pci@1b700000 {
|
||||
+ status = "ok";
|
||||
+ reset-gpio = <&qcom_pinmux 48 0>;
|
||||
+ pinctrl-0 = <&pcie1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
+
|
||||
+ nand@1ac00000 {
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
};
|
||||
|
||||
chosen {
|
||||
@@ -83,6 +84,15 @@
|
||||
@@ -65,6 +66,15 @@
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
|
@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
@@ -159,6 +169,34 @@
|
||||
@@ -135,6 +145,34 @@
|
||||
|
||||
linux,part-probe = "qcom-smem";
|
||||
};
|
||||
|
|
@ -83,7 +83,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
};
|
||||
|
||||
chosen {
|
||||
@@ -65,6 +66,15 @@
|
||||
@@ -38,6 +39,15 @@
|
||||
bias-none;
|
||||
};
|
||||
};
|
||||
|
|
@ -99,9 +99,9 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
};
|
||||
|
||||
gsbi2: gsbi@12480000 {
|
||||
@@ -176,5 +186,44 @@
|
||||
pinctrl-0 = <&pcie2_pins>;
|
||||
pinctrl-names = "default";
|
||||
@@ -140,5 +150,44 @@
|
||||
pcie2: pci@1b900000 {
|
||||
status = "ok";
|
||||
};
|
||||
+
|
||||
+ mdio0: mdio {
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
||||
@@ -93,6 +93,16 @@
|
||||
@@ -75,6 +75,16 @@
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
|
@ -29,7 +29,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
};
|
||||
|
||||
gsbi@16300000 {
|
||||
@@ -197,6 +207,27 @@
|
||||
@@ -173,6 +183,27 @@
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
|
@ -59,7 +59,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
|
||||
@@ -75,6 +75,14 @@
|
||||
@@ -48,6 +48,14 @@
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
|
@ -74,7 +74,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
};
|
||||
|
||||
gsbi2: gsbi@12480000 {
|
||||
@@ -225,5 +233,40 @@
|
||||
@@ -189,5 +197,40 @@
|
||||
reg = <7>;
|
||||
};
|
||||
};
|
||||
|
|
@ -117,7 +117,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
|
|||
};
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -636,6 +636,92 @@
|
||||
@@ -679,6 +679,92 @@
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue