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fixes several compile errors, reserves memory for second core, adds u-boot env parsing for ifxmips

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SVN-Revision: 11558
This commit is contained in:
John Crispin 2008-06-22 19:01:14 +00:00
parent 1af378601e
commit 496bdd9eb7
6 changed files with 157 additions and 40 deletions
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71
target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
View file

@ -29,25 +29,28 @@
#include <asm/bootinfo.h>
#include <asm/ifxmips/ifxmips.h>
static char buf[1024];
u32 *prom_cp1_base = NULL;
u32 prom_cp1_size = 0;
void
prom_free_prom_memory (void)
prom_free_prom_memory(void)
{
}
void
prom_putchar (char c)
prom_putchar(char c)
{
while ((ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
while((ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
if (c == '\n')
if(c == '\n')
ifxmips_w32('\r', IFXMIPS_ASC1_TBUF);
ifxmips_w32(c, IFXMIPS_ASC1_TBUF);
}
void
prom_printf (const char * fmt, ...)
prom_printf(const char * fmt, ...)
{
va_list args;
int l;
@ -58,17 +61,69 @@ prom_printf (const char * fmt, ...)
va_end(args);
buf_end = buf + l;
for (p = buf; p < buf_end; p++)
for(p = buf; p < buf_end; p++)
{
prom_putchar(*p);
}
}
u32 *prom_get_cp1_base(void)
{
return prom_cp1_base;
}
u32 prom_get_cp1_size(void)
{
return prom_cp1_size;
}
void __init
prom_init(void)
{
int argc = fw_arg0;
char **argv = (char **) fw_arg1;
char **envp = (char **) fw_arg2;
int memsize = 16;
int i;
mips_machtype = MACH_INFINEON_IFXMIPS;
strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
add_memory_region (0x00000000, 0x2000000, BOOT_MEM_RAM);
argv = (char**)KSEG1ADDR((unsigned long)argv);
arcs_cmdline[0] = '\0';
for(i = 1; i < argc; i++)
{
char *a = (char*)KSEG1ADDR(argv[i]);
if(!a)
continue;
if(strlen(arcs_cmdline) + strlen(a + 1) >= sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, a);
strcat(arcs_cmdline, " ");
}
envp = (char**)KSEG1ADDR((unsigned long)envp);
while(*envp)
{
char *e = (char*)KSEG1ADDR(*envp);
if(!strncmp(e, "memsize=", 8))
{
e += 8;
memsize = simple_strtoul(e, NULL, 10);
}
envp++;
}
prom_cp1_size = 2;
memsize -= prom_cp1_size;
prom_cp1_base = (u32*)(0xA0000000 + (memsize * 1024 * 1024));
prom_printf(KERN_INFO "Using %dMB Ram and reserving %dMB for cp1\n", memsize, prom_cp1_size);
memsize *= 1024 * 1024;
if(!*arcs_cmdline)
strcpy(&(arcs_cmdline[0]), "console=ttyS0,115200 rootfstype=squashfs,jffs2 init=/etc/preinit");
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
}

26
target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c
View file

@ -129,7 +129,7 @@ detect_squashfs_partition (unsigned long start_offset){
}
static int
ifxmips_mtd_probe (void)
ifxmips_mtd_probe (struct platform_device *dev)
{
struct mtd_info *ifxmips_mtd = NULL;
struct mtd_partition *parts = NULL;
@ -179,23 +179,23 @@ ifxmips_mtd_probe (void)
return 0;
}
static struct
platform_driver ifxmips_mtd_driver = {
.probe = ifxmips_mtd_probe,
.driver = {
.name = DRVNAME,
.owner = THIS_MODULE,
},
};
static struct
platform_driver ifxmips_mtd_driver = {
.probe = ifxmips_mtd_probe,
.driver = {
.name = DRVNAME,
.owner = THIS_MODULE,
},
};
int __init
init_ifxmips_mtd (void)
{
int ret = platform_driver_register(&ifxmips_mtd_driver);
if (ret)
printk(KERN_INFO DRVNAME ": error registering platfom driver!");
int ret = platform_driver_register(&ifxmips_mtd_driver);
if (ret)
printk(KERN_INFO DRVNAME ": error registering platfom driver!");
return ret;
return ret;
}
static void

48
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
View file

@ -88,7 +88,7 @@
#define IFXMIPS_ASC1_RXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
/* control */
#define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
#define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
/* timer reload */
#define IFXMIPS_ASC1_BG ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
@ -103,12 +103,12 @@
/*------------ RCU */
#define IFXMIPS_RCU_BASE_ADDR 0xBF203000
/* reset request */
#define IFXMIPS_RCU_REQ ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
#define IFXMIPS_RST_ALL 0x40000000
#define IFXMIPS_RCU_RST ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
#define IFXMIPS_RCU_RST_CPU1 (1 << 3)
#define IFXMIPS_RCU_RST_ALL 0x40000000
#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7)
#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11)
@ -440,6 +440,45 @@
#define MEI_XMEM_BAR16 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0094))
/*------------ DEU */
#define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100)
#define IFXMIPS_DEU_CLK ((u32 *)(IFXMIPS_DEU_BASE + 0x0000))
#define IFXMIPS_DEU_ID ((u32 *)(IFXMIPS_DEU_BASE + 0x0008))
#define IFXMIPS_DES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0010))
#define IFXMIPS_DES_IHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0014))
#define IFXMIPS_DES_ILR ((u32 *)(IFXMIPS_DEU_BASE + 0x0018))
#define IFXMIPS_DES_K1HR ((u32 *)(IFXMIPS_DEU_BASE + 0x001C))
#define IFXMIPS_DES_K1LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0020))
#define IFXMIPS_DES_K3HR ((u32 *)(IFXMIPS_DEU_BASE + 0x0024))
#define IFXMIPS_DES_K3LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0028))
#define IFXMIPS_DES_IVHR ((u32 *)(IFXMIPS_DEU_BASE + 0x002C))
#define IFXMIPS_DES_IVLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0030))
#define IFXMIPS_DES_OHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0040))
#define IFXMIPS_DES_OLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
#define IFXMIPS_AES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
#define IFXMIPS_AES_ID3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0054))
#define IFXMIPS_AES_ID2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0058))
#define IFXMIPS_AES_ID1R ((u32 *)(IFXMIPS_DEU_BASE + 0x005C))
#define IFXMIPS_AES_ID0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0060))
#define IFXMIPS_AES_K7R ((u32 *)(IFXMIPS_DEU_BASE + 0x0064))
#define IFXMIPS_AES_K6R ((u32 *)(IFXMIPS_DEU_BASE + 0x0068))
#define IFXMIPS_AES_K5R ((u32 *)(IFXMIPS_DEU_BASE + 0x006C))
#define IFXMIPS_AES_K4R ((u32 *)(IFXMIPS_DEU_BASE + 0x0070))
#define IFXMIPS_AES_K3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0074))
#define IFXMIPS_AES_K2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0078))
#define IFXMIPS_AES_K1R ((u32 *)(IFXMIPS_DEU_BASE + 0x007C))
#define IFXMIPS_AES_K0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0080))
#define IFXMIPS_AES_IV3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0084))
#define IFXMIPS_AES_IV2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0088))
#define IFXMIPS_AES_IV1R ((u32 *)(IFXMIPS_DEU_BASE + 0x008C))
#define IFXMIPS_AES_IV0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0090))
#define IFXMIPS_AES_0D3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0094))
#define IFXMIPS_AES_0D2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0098))
#define IFXMIPS_AES_OD1R ((u32 *)(IFXMIPS_DEU_BASE + 0x009C))
#define IFXMIPS_AES_OD0R ((u32 *)(IFXMIPS_DEU_BASE + 0x00A0))
/*------------ FUSE */
#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354)
@ -448,6 +487,7 @@
/*------------ MPS */
#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
#define IFXMIPS_MPS_SRAM ((u32*)(KSEG1 + 0x1F200000))
#define IFXMIPS_MPS_CHIPID ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
#define IFXMIPS_MPS_VC0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0000))

22
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gptu.h
View file

@ -139,24 +139,16 @@ struct gptu_ioctl_param {
* Data Type
* ####################################
*/
#if defined(__KERNEL__)
typedef void (*timer_callback)(unsigned long arg);
#endif // defined(__KERNEL__)
typedef void (*timer_callback)(unsigned long arg);
/*
* ####################################
* Declaration
* ####################################
*/
#if defined(__KERNEL__)
extern int request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
extern int free_timer(unsigned int);
extern int start_timer(unsigned int, int);
extern int stop_timer(unsigned int);
extern int reset_counter_flags(u32 timer, u32 flags);
extern int get_count_value(unsigned int, unsigned long *);
extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
extern int ifxmips_free_timer(unsigned int);
extern int ifxmips_start_timer(unsigned int, int);
extern int ifxmips_stop_timer(unsigned int);
extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
extern int ifxmips_get_count_value(unsigned int, unsigned long *);
extern u32 cal_divider(unsigned long);

27
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h Normal file
View file

@ -0,0 +1,27 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2008 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXPROM_H__
#define _IFXPROM_H__
void prom_printf(const char * fmt, ...);
u32 *prom_get_cp1_base(void);
u32 prom_get_cp1_size(void);
#endif

3
target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h
View file

@ -28,14 +28,17 @@
static inline int gpio_direction_input(unsigned gpio) {
ifxmips_port_set_dir_in(0, gpio);
return 0;
}
static inline int gpio_direction_output(unsigned gpio, int value) {
ifxmips_port_set_dir_out(0, gpio);
return 0;
}
static inline int gpio_get_value(unsigned gpio) {
ifxmips_port_get_input(0, gpio);
return 0;
}
static inline void gpio_set_value(unsigned gpio, int value) {