add experimental support for bcm6338
SVN-Revision: 13691
This commit is contained in:
Florian Fainelli
parent
fa5a568380
commit
3dd67d64f4
5 changed files with 136 additions and 2 deletions
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@ -14,6 +14,7 @@ CONFIG_AUDIT_GENERIC=y
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CONFIG_BASE_SMALL=0
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# CONFIG_BCM47XX is not set
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CONFIG_BCM63XX=y
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CONFIG_BCM63XX_CPU_6338=y
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CONFIG_BCM63XX_CPU_6348=y
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CONFIG_BCM63XX_CPU_6358=y
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CONFIG_BCM63XX_ENET=y
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@ -1,6 +1,13 @@
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menu "CPU support"
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depends on BCM63XX
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config BCM63XX_CPU_6338
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bool "support 6338 CPU"
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select HW_HAS_PCI
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select USB_ARCH_HAS_OHCI
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select USB_OHCI_BIG_ENDIAN_DESC
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select USB_OHCI_BIG_ENDIAN_MMIO
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config BCM63XX_CPU_6348
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bool "support 6348 CPU"
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select HW_HAS_PCI
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@ -25,6 +25,29 @@ static u16 bcm63xx_cpu_rev;
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static unsigned int bcm63xx_cpu_freq;
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static unsigned int bcm63xx_memory_size;
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/*
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* 6338 register sets and irqs
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*/
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static const unsigned long bcm96338_regs_base[] = {
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[RSET_PERF] = BCM_6338_PERF_BASE,
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[RSET_TIMER] = BCM_6338_TIMER_BASE,
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[RSET_WDT] = BCM_6338_WDT_BASE,
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[RSET_UART0] = BCM_6338_UART0_BASE,
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[RSET_GPIO] = BCM_6338_GPIO_BASE,
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[RSET_SPI] = BCM_6338_SPI_BASE,
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};
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static const int bcm96338_irqs[] = {
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[IRQ_TIMER] = BCM_6338_TIMER_IRQ,
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[IRQ_UART0] = BCM_6338_UART0_IRQ,
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[IRQ_DSL] = BCM_6338_DSL_IRQ,
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[IRQ_ENET0] = BCM_6338_ENET0_IRQ,
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[IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
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[IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
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[IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
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};
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/*
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* 6348 register sets and irqs
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*/
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@ -137,6 +160,10 @@ static unsigned int detect_cpu_clock(void)
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{
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unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
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if (BCMCPU_IS_6338()) {
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return 240000000;
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}
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/*
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* frequency depends on PLL configuration:
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*/
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@ -170,7 +197,7 @@ static unsigned int detect_memory_size(void)
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unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
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u32 val;
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if (BCMCPU_IS_6348()) {
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if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
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val = bcm_sdram_readl(SDRAM_CFG_REG);
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rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
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cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
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@ -204,6 +231,11 @@ void __init bcm63xx_cpu_init(void)
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expected_cpu_id = 0;
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switch (c->cputype) {
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case CPU_BCM6338:
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expected_cpu_id = BCM6338_CPU_ID;
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bcm63xx_regs_base = bcm96338_regs_base;
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bcm63xx_irqs = bcm96338_irqs;
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break;
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case CPU_BCM6348:
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expected_cpu_id = BCM6348_CPU_ID;
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bcm63xx_regs_base = bcm96348_regs_base;
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@ -9,6 +9,7 @@
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* compile time if only one CPU support is enabled (idea stolen from
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* arm mach-types)
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*/
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#define BCM6338_CPU_ID 0x6338
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#define BCM6348_CPU_ID 0x6348
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#define BCM6358_CPU_ID 0x6358
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@ -17,6 +18,19 @@ u16 __bcm63xx_get_cpu_id(void);
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u16 bcm63xx_get_cpu_rev(void);
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unsigned int bcm63xx_get_cpu_freq(void);
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#ifdef CONFIG_BCM63XX_CPU_6338
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
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# endif
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# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
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#else
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# define BCMCPU_IS_6338() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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@ -87,6 +101,19 @@ enum bcm63xx_regs_set {
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#define RSET_EHCI_SIZE 256
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#define RSET_PCMCIA_SIZE 12
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/*
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* 6338 register sets base address
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*/
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#define BCM_6338_PERF_BASE (0xfffe0000)
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#define BCM_6338_TIMER_BASE (0xfffe0000)
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#define BCM_6338_WDT_BASE (0xfffe001c)
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#define BCM_6338_UART0_BASE (0xfffe0300)
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#define BCM_6338_GPIO_BASE (0xfffe0400)
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#define BCM_6338_SPI_BASE (0xfffe0c00)
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#define BCM_6338_SAR_BASE (0xfffe2000)
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#define BCM_6338_MEMC_BASE (0xfffe3100)
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/*
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* 6348 register sets base address
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*/
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@ -147,6 +174,24 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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#ifdef BCMCPU_RUNTIME_DETECT
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return bcm63xx_regs_base[set];
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#else
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#ifdef CONFIG_BCM63XX_CPU_6338
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switch (set) {
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case RSET_PERF:
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return BCM_6338_PERF_BASE;
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case RSET_TIMER:
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return BCM_6338_TIMER_BASE;
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case RSET_WDT:
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return BCM_6338_WDT_BASE;
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case RSET_UART0:
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return BCM_6338_UART0_BASE;
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case RSET_GPIO:
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return BCM_6338_GPIO_BASE;
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case RSET_SPI:
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return BCM_6338_SPI_BASE;
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case RSET_MEMC:
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return BCM_6338_MEMC_BASE;
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}
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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switch (set) {
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case RSET_DSL_LMEM:
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@ -266,6 +311,27 @@ enum bcm63xx_irq {
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IRQ_PCMCIA,
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};
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/*
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* 6338 irqs
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*/
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#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
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#define BCM_6338_SPI_IR (IRQ_INTERNAL_BASE + 1)
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#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
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#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
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#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
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#define BCM_6338_USBS_IRQ (IRQ_INTERNAL_BASE + 7)
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#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
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#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
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#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
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#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
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#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
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#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
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#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
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/*
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* 6348 irqs
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*/
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@ -15,6 +15,15 @@
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/* Clock Control register */
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#define PERF_CKCTL_REG 0x4
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#define CKCTL_6338_ENET_EN (1 << 4)
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#define CKCTL_6338_USBS_EN (1 << 4)
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#define CKCTL_6338_SAR_EN (1 << 5)
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#define CKCTL_6338_SPI_EN (1 << 9)
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#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ENET_EN | \
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CKCTL_6338_SAR_EN | \
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CKCTL_6338_SPI_EN)
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#define CKCTL_6348_ADSLPHY_EN (1 << 0)
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#define CKCTL_6348_MPI_EN (1 << 1)
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#define CKCTL_6348_SDRAM_EN (1 << 2)
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@ -83,6 +92,25 @@
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/* Soft Reset register */
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#define PERF_SOFTRESET_REG 0x28
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#define SOFTRESET_6338_SPI_MASK (1 << 0)
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#define SOFTRESET_6338_ENET_MASK (1 << 2)
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#define SOFTRESET_6338_USBH_MASK (1 << 3)
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#define SOFTRESET_6338_USBS_MASK (1 << 4)
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#define SOFTRESET_6338_ADSL_MASK (1 << 5)
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#define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
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#define SOFTRESET_6338_SAR_MASK (1 << 7)
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#define SOFTRESET_6338_ACLC_MASK (1 << 8)
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#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
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#define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
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SOFTRESET_6338_ENET_MASK | \
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SOFTRESET_6338_USBH_MASK | \
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SOFTRESET_6338_USBS_MASK | \
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SOFTRESET_6338_ADSL_MASK | \
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SOFTRESET_6338_DMAMEM_MASK | \
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SOFTRESET_6338_SAR_MASK | \
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SOFTRESET_6338_ACLC_MASK | \
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SOFTRESET_6338_ADSLMIPSPLL_MASK)
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#define SOFTRESET_6348_SPI_MASK (1 << 0)
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#define SOFTRESET_6348_ENET_MASK (1 << 2)
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#define SOFTRESET_6348_USBH_MASK (1 << 3)
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@ -763,7 +791,7 @@
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#define SPI_INT_MASK 0x704
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#define SPI_INTR_CMD_DONE 0x01
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#define SPI_INTR_RX_OVERFLOW 0x02
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#define SPI_INTR_INTR_TX_UNDERFLOW 0x04
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#define SPI_INTR_TX_UNDERFLOW 0x04
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#define SPI_INTR_TX_OVERFLOW 0x08
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#define SPI_INTR_RX_UNDERFLOW 0x10
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#define SPI_INTR_CLEAR_ALL 0x1f
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