apm821xx: remove kernel 4.9 support
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This commit is contained in:
Christian Lamparter
Mathias Kresin
parent
e97f92bbf9
commit
3c94691620
14 changed files with 0 additions and 2682 deletions
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@ -1,326 +0,0 @@
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# CONFIG_40x is not set
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CONFIG_44x=y
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CONFIG_460EX=y
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CONFIG_4xx=y
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CONFIG_4xx_SOC=y
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# CONFIG_ADVANCED_OPTIONS is not set
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CONFIG_APM821xx=y
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CONFIG_APOLLO3G=y
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# CONFIG_ARCHES is not set
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
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CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
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CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK=y
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CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
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CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
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CONFIG_ARCH_HAS_ILOG2_U32=y
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CONFIG_ARCH_HAS_SG_CHAIN=y
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CONFIG_ARCH_HAS_WALK_MEMORY=y
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CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_MAY_HAVE_PC_FDC=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
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CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
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# CONFIG_ARCH_RANDOM is not set
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CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
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CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
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CONFIG_ARCH_SUPPORTS_DEFERRED_STRUCT_PAGE_INIT=y
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CONFIG_ARCH_SUPPORTS_UPROBES=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_AUDIT_ARCH=y
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# CONFIG_BAMBOO is not set
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CONFIG_BCH=y
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CONFIG_BLK_MQ_PCI=y
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# CONFIG_BLUESTONE is not set
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CONFIG_BOOKE=y
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CONFIG_BOOKE_WDT=y
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# CONFIG_BOUNCE is not set
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CONFIG_BUCKMINSTER=y
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# CONFIG_CANYONLANDS is not set
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CONSISTENT_SIZE=0x00200000
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_CRC16=y
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CONFIG_CRYPTO_DEFLATE=y
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CONFIG_CRYPTO_DEV_PPC4XX=y
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CONFIG_CRYPTO_HASH=y
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CONFIG_CRYPTO_HASH2=y
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CONFIG_CRYPTO_HW=y
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CONFIG_CRYPTO_LZO=y
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CONFIG_CRYPTO_MD5_PPC=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_SHA1_PPC=y
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CONFIG_CRYPTO_WORKQUEUE=y
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CONFIG_DECOMPRESS_GZIP=y
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# CONFIG_DEFAULT_UIMAGE is not set
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CONFIG_DTC=y
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# CONFIG_E200 is not set
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CONFIG_EARLY_PRINTK=y
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# CONFIG_EBONY is not set
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CONFIG_EDAC_ATOMIC_SCRUB=y
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CONFIG_EDAC_SUPPORT=y
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# CONFIG_EIGER is not set
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# CONFIG_EPAPR_BOOT is not set
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CONFIG_EXTRA_TARGETS="uImage"
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CONFIG_FIXED_PHY=y
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CONFIG_FREEZER=y
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# CONFIG_FSL_LBC is not set
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# CONFIG_FSL_ULI1575 is not set
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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# CONFIG_GENERIC_CSUM is not set
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_ISA_DMA=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_NVRAM=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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# CONFIG_GENERIC_TBSYNC is not set
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CONFIG_GENERIC_TIME_VSYSCALL_OLD=y
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# CONFIG_GEN_RTC is not set
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# CONFIG_GE_FPGA is not set
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# CONFIG_GLACIER is not set
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_GENERIC_PLATFORM=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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# CONFIG_HAS_RAPIDIO is not set
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
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CONFIG_HAVE_ARCH_AUDITSYSCALL=y
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# CONFIG_HAVE_ARCH_BITREVERSE is not set
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
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CONFIG_HAVE_CBPF_JIT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
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CONFIG_HAVE_DMA_API_DEBUG=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
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CONFIG_HAVE_GENERIC_RCU_GUP=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IOREMAP_PROT=y
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CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_PERF_REGS=y
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CONFIG_HAVE_PERF_USER_STACK_DUMP=y
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CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
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# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
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CONFIG_HAVE_VIRT_CPU_ACCOUNTING=y
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CONFIG_HW_RANDOM=y
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CONFIG_HW_RANDOM_PPC4XX=y
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CONFIG_HZ=1000
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# CONFIG_HZ_100 is not set
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CONFIG_HZ_1000=y
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CONFIG_HZ_PERIODIC=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_IBM_IIC=y
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CONFIG_IBM_EMAC=y
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CONFIG_IBM_EMAC_EMAC4=y
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CONFIG_IBM_EMAC_POLL_WEIGHT=32
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CONFIG_IBM_EMAC_RGMII=y
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CONFIG_IBM_EMAC_RXB=128
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CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256
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CONFIG_IBM_EMAC_RX_SKB_HEADROOM=0
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CONFIG_IBM_EMAC_TAH=y
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CONFIG_IBM_EMAC_TXB=128
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# CONFIG_ICON is not set
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CONFIG_IKAREM=y
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CONFIG_INITRAMFS_SOURCE=""
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# CONFIG_IOMMU_HELPER is not set
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# CONFIG_IPIC is not set
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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CONFIG_ISA_DMA_API=y
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# CONFIG_JFFS2_FS is not set
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# CONFIG_KATMAI is not set
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CONFIG_KERNEL_GZIP=y
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CONFIG_KERNEL_START=0xc0000000
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CONFIG_LEDS_TRIGGER_MTD=y
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CONFIG_LIBFDT=y
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CONFIG_LOWMEM_SIZE=0x30000000
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CONFIG_LZO_COMPRESS=y
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CONFIG_LZO_DECOMPRESS=y
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# CONFIG_MATH_EMULATION is not set
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CONFIG_MDIO_BOARDINFO=y
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# CONFIG_MDIO_HISI_FEMAC is not set
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# CONFIG_MFD_ACT8945A is not set
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# CONFIG_MFD_MAX77620 is not set
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# CONFIG_MMIO_NVRAM is not set
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CONFIG_MODULES_USE_ELF_RELA=y
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# CONFIG_MPIC is not set
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# CONFIG_MPIC_U3_HT_IRQS is not set
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# CONFIG_MPIC_WEIRD is not set
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CONFIG_MTD_CFI_ADV_OPTIONS=y
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# CONFIG_MTD_CFI_GEOMETRY is not set
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_BCH=y
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CONFIG_MTD_NAND_ECC=y
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CONFIG_MTD_NAND_ECC_BCH=y
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CONFIG_MTD_NAND_ECC_SMC=y
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CONFIG_MTD_NAND_NDFC=y
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# CONFIG_MTD_SPLIT is not set
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# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
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CONFIG_NEED_DMA_MAP_STATE=y
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# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
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CONFIG_NEED_PER_CPU_KM=y
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CONFIG_NEED_SG_DMA_LENGTH=y
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# CONFIG_NONSTATIC_KERNEL is not set
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CONFIG_NOT_COHERENT_CACHE=y
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CONFIG_NO_BOOTMEM=y
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CONFIG_NR_IRQS=512
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_ADDRESS_PCI=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_MDIO=y
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CONFIG_OF_NET=y
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CONFIG_OF_PCI=y
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CONFIG_OF_PCI_IRQ=y
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CONFIG_OF_RESERVED_MEM=y
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CONFIG_OLD_SIGACTION=y
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CONFIG_OLD_SIGSUSPEND=y
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CONFIG_PAGE_OFFSET=0xc0000000
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CONFIG_PCI=y
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CONFIG_PCIEAER=y
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CONFIG_PCIEPORTBUS=y
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CONFIG_PCIE_PME=y
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CONFIG_PCI_BUS_ADDR_T_64BIT=y
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CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PCI_MSI=y
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# CONFIG_PCI_MSI_IRQ_DOMAIN is not set
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CONFIG_PGTABLE_LEVELS=2
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CONFIG_PHYLIB=y
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CONFIG_PHYSICAL_START=0x00000000
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CONFIG_PHYS_64BIT=y
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CONFIG_PHYS_ADDR_T_64BIT=y
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CONFIG_PM=y
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CONFIG_PM_AUTOSLEEP=y
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# CONFIG_PM_DEBUG is not set
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CONFIG_PM_SLEEP=y
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CONFIG_PM_WAKELOCKS=y
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CONFIG_PM_WAKELOCKS_GC=y
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CONFIG_PM_WAKELOCKS_LIMIT=100
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CONFIG_PPC=y
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CONFIG_PPC32=y
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CONFIG_PPC44x_SIMPLE=y
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CONFIG_PPC4xx_CPM=y
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CONFIG_PPC4xx_GPIO=y
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# CONFIG_PPC4xx_HSTA_MSI is not set
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CONFIG_PPC4xx_MSI=y
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CONFIG_PPC4xx_OCM=y
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CONFIG_PPC4xx_PCI_EXPRESS=y
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# CONFIG_PPC64 is not set
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# CONFIG_PPC_47x is not set
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# CONFIG_PPC_85xx is not set
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# CONFIG_PPC_8xx is not set
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# CONFIG_PPC_970_NAP is not set
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CONFIG_PPC_ADV_DEBUG_DACS=2
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CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y
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CONFIG_PPC_ADV_DEBUG_DVCS=2
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CONFIG_PPC_ADV_DEBUG_IACS=4
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CONFIG_PPC_ADV_DEBUG_REGS=y
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# CONFIG_PPC_BOOK3S_32 is not set
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# CONFIG_PPC_CELL is not set
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# CONFIG_PPC_CELL_NATIVE is not set
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# CONFIG_PPC_COPRO_BASE is not set
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CONFIG_PPC_DCR=y
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# CONFIG_PPC_DCR_MMIO is not set
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CONFIG_PPC_DCR_NATIVE=y
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# CONFIG_PPC_DOORBELL is not set
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# CONFIG_PPC_EARLY_DEBUG is not set
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# CONFIG_PPC_EPAPR_HV_PIC is not set
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CONFIG_PPC_FPU=y
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# CONFIG_PPC_I8259 is not set
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# CONFIG_PPC_ICP_HV is not set
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# CONFIG_PPC_ICP_NATIVE is not set
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# CONFIG_PPC_ICS_RTAS is not set
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CONFIG_PPC_INDIRECT_PCI=y
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CONFIG_PPC_LIB_RHEAP=y
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CONFIG_PPC_MMU_NOHASH=y
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# CONFIG_PPC_MM_SLICES is not set
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# CONFIG_PPC_MPC106 is not set
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CONFIG_PPC_MSI_BITMAP=y
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# CONFIG_PPC_P7_NAP is not set
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CONFIG_PPC_PCI_CHOICE=y
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# CONFIG_PPC_RTAS is not set
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CONFIG_PPC_UDBG_16550=y
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CONFIG_PPC_WERROR=y
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# CONFIG_PPC_XICS is not set
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# CONFIG_PQ2ADS is not set
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CONFIG_PTE_64BIT=y
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# CONFIG_QORIQ_THERMAL is not set
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# CONFIG_RAINIER is not set
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CONFIG_RAS=y
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# CONFIG_RCU_STALL_COMMON is not set
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CONFIG_RD_GZIP=y
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# CONFIG_RELOCATABLE is not set
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CONFIG_RWSEM_XCHGADD_ALGORITHM=y
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# CONFIG_SAM440EP is not set
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# CONFIG_SCHED_INFO is not set
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# CONFIG_SCSI_DMA is not set
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# CONFIG_SENSORS_TC654 is not set
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# CONFIG_SEQUOIA is not set
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CONFIG_SERIAL_8250_EXTENDED=y
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CONFIG_SERIAL_8250_FSL=y
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CONFIG_SERIAL_8250_SHARE_IRQ=y
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CONFIG_SERIAL_OF_PLATFORM=y
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CONFIG_SIMPLE_GPIO=y
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CONFIG_SPARSE_IRQ=y
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CONFIG_SRCU=y
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CONFIG_SUSPEND=y
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CONFIG_SUSPEND_FREEZER=y
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# CONFIG_SWIOTLB is not set
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CONFIG_SWPHY=y
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CONFIG_SYSCTL_EXCEPTION_TRACE=y
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# CONFIG_TAISHAN is not set
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CONFIG_TASK_SIZE=0xc0000000
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_USB_SUPPORT=y
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CONFIG_VDSO32=y
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# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
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# CONFIG_WARP is not set
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CONFIG_WATCHDOG_CORE=y
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CONFIG_WNDR4700=y
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# CONFIG_XILINX_SYSACE is not set
|
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# CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set
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CONFIG_XZ_DEC_BCJ=y
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CONFIG_XZ_DEC_POWERPC=y
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# CONFIG_YOSEMITE is not set
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CONFIG_ZLIB_DEFLATE=y
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CONFIG_ZLIB_INFLATE=y
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|
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@ -1,32 +0,0 @@
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--- a/arch/powerpc/platforms/44x/Kconfig
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+++ b/arch/powerpc/platforms/44x/Kconfig
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@@ -40,6 +40,19 @@ config EBONY
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help
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This option enables support for the IBM PPC440GP evaluation board.
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+config IKAREM
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+ bool "Ikarem"
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+ depends on 44x
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+ default n
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+ select PPC44x_SIMPLE
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+ select APM821xx
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+ select PCI_MSI
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+ select PPC4xx_MSI
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+ select PPC4xx_PCI_EXPRESS
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+ select IBM_EMAC_RGMII
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+ help
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+ This option enables support for the Cisco Meraki MR24 (Ikarem) Access Point.
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+
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config SAM440EP
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bool "Sam440ep"
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depends on 44x
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--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
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+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
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@@ -62,6 +62,7 @@ static char *board[] __initdata = {
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"amcc,sequoia",
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"amcc,taishan",
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"amcc,yosemite",
|
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+ "meraki,ikarem",
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"mosaixtech,icon"
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};
|
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|
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|
|
@ -1,30 +0,0 @@
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--- a/arch/powerpc/platforms/44x/Kconfig
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+++ b/arch/powerpc/platforms/44x/Kconfig
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@@ -143,6 +143,17 @@ config CANYONLANDS
|
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help
|
||||
This option enables support for the AMCC PPC460EX evaluation board.
|
||||
|
||||
+config APOLLO3G
|
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+ bool "Apollo3G"
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+ depends on 44x
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+ default n
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+ select PPC44x_SIMPLE
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+ select APM821xx
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+ select IBM_EMAC_RGMII
|
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+ select 460EX
|
||||
+ help
|
||||
+ This option enables support for the AMCC Apollo 3G board.
|
||||
+
|
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config GLACIER
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bool "Glacier"
|
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depends on 44x
|
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--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
|
||||
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
|
||||
@@ -50,6 +50,7 @@ machine_device_initcall(ppc44x_simple, p
|
||||
* board.c file for it rather than adding it to this list.
|
||||
*/
|
||||
static char *board[] __initdata = {
|
||||
+ "amcc,apollo3g",
|
||||
"amcc,arches",
|
||||
"amcc,bamboo",
|
||||
"apm,bluestone",
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
--- a/arch/powerpc/platforms/44x/Makefile
|
||||
+++ b/arch/powerpc/platforms/44x/Makefile
|
||||
@@ -3,6 +3,7 @@ ifneq ($(CONFIG_PPC4xx_CPM),y)
|
||||
obj-$(CONFIG_44x) += idle.o
|
||||
endif
|
||||
obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
|
||||
+obj-$(CONFIG_WNDR4700) += wndr4700.o
|
||||
obj-$(CONFIG_EBONY) += ebony.o
|
||||
obj-$(CONFIG_SAM440EP) += sam440ep.o
|
||||
obj-$(CONFIG_WARP) += warp.o
|
||||
--- a/arch/powerpc/platforms/44x/Kconfig
|
||||
+++ b/arch/powerpc/platforms/44x/Kconfig
|
||||
@@ -260,6 +260,19 @@ config ICON
|
||||
help
|
||||
This option enables support for the AMCC PPC440SPe evaluation board.
|
||||
|
||||
+config WNDR4700
|
||||
+ bool "WNDR4700"
|
||||
+ depends on 44x
|
||||
+ default n
|
||||
+ select APM821xx
|
||||
+ select PCI_MSI
|
||||
+ select PPC4xx_MSI
|
||||
+ select PPC4xx_PCI_EXPRESS
|
||||
+ select IBM_EMAC_RGMII
|
||||
+ select 460EX
|
||||
+ help
|
||||
+ This option enables support for the Netgear WNDR4700/WNDR4720 board.
|
||||
+
|
||||
config XILINX_VIRTEX440_GENERIC_BOARD
|
||||
bool "Generic Xilinx Virtex 5 FXT board support"
|
||||
depends on 44x
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
--- a/arch/powerpc/platforms/44x/Kconfig
|
||||
+++ b/arch/powerpc/platforms/44x/Kconfig
|
||||
@@ -30,6 +30,19 @@ config BLUESTONE
|
||||
help
|
||||
This option enables support for the APM APM821xx Evaluation board.
|
||||
|
||||
+config BUCKMINSTER
|
||||
+ bool "Buckminster"
|
||||
+ depends on 44x
|
||||
+ default n
|
||||
+ select APM821xx
|
||||
+ select PCI_MSI
|
||||
+ select PPC4xx_MSI
|
||||
+ select PPC4xx_PCI_EXPRESS
|
||||
+ select IBM_EMAC_RGMII
|
||||
+ select 460EX
|
||||
+ help
|
||||
+ This option enables support for the Cisco Meraki MX60/MX60W (Buckminster) Security Appliance
|
||||
+
|
||||
config EBONY
|
||||
bool "Ebony"
|
||||
depends on 44x
|
||||
--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
|
||||
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
|
||||
@@ -63,6 +63,7 @@ static char *board[] __initdata = {
|
||||
"amcc,sequoia",
|
||||
"amcc,taishan",
|
||||
"amcc,yosemite",
|
||||
+ "meraki,buckminster",
|
||||
"meraki,ikarem",
|
||||
"mosaixtech,icon"
|
||||
};
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
|
||||
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
|
||||
@@ -1066,15 +1066,24 @@ static int __init apm821xx_pciex_init_po
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
- * Do a software reset on PCIe ports.
|
||||
- * This code is to fix the issue that pci drivers doesn't re-assign
|
||||
- * bus number for PCIE devices after Uboot
|
||||
- * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
|
||||
- * PT quad port, SAS LSI 1064E)
|
||||
+ * Only reset the PHY when no link is currently established.
|
||||
+ * This is for the Atheros PCIe board which has problems to establish
|
||||
+ * the link (again) after this PHY reset. All other currently tested
|
||||
+ * PCIe boards don't show this problem.
|
||||
*/
|
||||
-
|
||||
- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
|
||||
- mdelay(10);
|
||||
+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
|
||||
+ if (!(val & 0x00001000)) {
|
||||
+ /*
|
||||
+ * Do a software reset on PCIe ports.
|
||||
+ * This code is to fix the issue that pci drivers doesn't re-assign
|
||||
+ * bus number for PCIE devices after Uboot
|
||||
+ * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
|
||||
+ * PT quad port, SAS LSI 1064E)
|
||||
+ */
|
||||
+
|
||||
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
|
||||
+ mdelay(10);
|
||||
+ }
|
||||
|
||||
if (port->endpoint)
|
||||
val = PTYPE_LEGACY_ENDPOINT << 20;
|
||||
@@ -1091,9 +1100,12 @@ static int __init apm821xx_pciex_init_po
|
||||
mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
|
||||
mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
|
||||
|
||||
- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
|
||||
- mdelay(50);
|
||||
- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
|
||||
+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
|
||||
+ if (!(val & 0x00001000)) {
|
||||
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
|
||||
+ mdelay(50);
|
||||
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
|
||||
+ }
|
||||
|
||||
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
|
||||
mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
|
||||
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
|
||||
@@ -1913,9 +1913,9 @@ static void __init ppc4xx_configure_pcie
|
||||
* if it works
|
||||
*/
|
||||
out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
|
||||
- out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
|
||||
+ out_le32(mbase + PECFG_PIM0LAH, 0x00000008);
|
||||
out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
|
||||
- out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
|
||||
+ out_le32(mbase + PECFG_PIM1LAH, 0x0000000c);
|
||||
out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
|
||||
out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
|
||||
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
--- a/drivers/net/ethernet/ibm/emac/core.c
|
||||
+++ b/drivers/net/ethernet/ibm/emac/core.c
|
||||
@@ -129,6 +129,7 @@ static inline void emac_report_timeout_e
|
||||
{
|
||||
if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
|
||||
EMAC_FTR_460EX_PHY_CLK_FIX |
|
||||
+ EMAC_FTR_APM821XX_PHY_CLK_FIX |
|
||||
EMAC_FTR_440EP_PHY_CLK_FIX))
|
||||
DBG(dev, "%s" NL, error);
|
||||
else if (net_ratelimit())
|
||||
@@ -146,6 +147,10 @@ static inline void emac_rx_clk_tx(struct
|
||||
if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
|
||||
dcri_clrset(SDR0, SDR0_MFR,
|
||||
0, SDR0_MFR_ECS >> dev->cell_index);
|
||||
+
|
||||
+ if (emac_has_feature(dev, EMAC_FTR_APM821XX_PHY_CLK_FIX))
|
||||
+ dcri_clrset(SDR0, SDR0_ETH_CFG,
|
||||
+ 0, 0x00000100 >> dev->cell_index);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -155,6 +160,10 @@ static inline void emac_rx_clk_default(s
|
||||
if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
|
||||
dcri_clrset(SDR0, SDR0_MFR,
|
||||
SDR0_MFR_ECS >> dev->cell_index, 0);
|
||||
+
|
||||
+ if (emac_has_feature(dev, EMAC_FTR_APM821XX_PHY_CLK_FIX))
|
||||
+ dcri_clrset(SDR0, SDR0_ETH_CFG,
|
||||
+ 0x00000100 >> dev->cell_index, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -2617,6 +2626,7 @@ static int emac_init_config(struct emac_
|
||||
if (of_device_is_compatible(np, "ibm,emac-apm821xx")) {
|
||||
dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
|
||||
EMAC_FTR_APM821XX_NO_HALF_DUPLEX |
|
||||
+ EMAC_FTR_APM821XX_PHY_CLK_FIX |
|
||||
EMAC_FTR_460EX_PHY_CLK_FIX);
|
||||
}
|
||||
} else if (of_device_is_compatible(np, "ibm,emac4")) {
|
||||
--- a/drivers/net/ethernet/ibm/emac/core.h
|
||||
+++ b/drivers/net/ethernet/ibm/emac/core.h
|
||||
@@ -333,6 +333,8 @@ struct emac_instance {
|
||||
*/
|
||||
#define EMAC_FTR_APM821XX_NO_HALF_DUPLEX 0x00001000
|
||||
|
||||
+#define EMAC_FTR_APM821XX_PHY_CLK_FIX 0x000002000
|
||||
+
|
||||
/* Right now, we don't quite handle the always/possible masks on the
|
||||
* most optimal way as we don't have a way to say something like
|
||||
* always EMAC4. Patches welcome.
|
||||
|
|
@ -1,328 +0,0 @@
|
|||
From b1c54da602ae9215cfbde1c3ed3b6296b76f07fc Mon Sep 17 00:00:00 2001
|
||||
Message-Id: <b1c54da602ae9215cfbde1c3ed3b6296b76f07fc.1486337989.git.chunkeey@googlemail.com>
|
||||
In-Reply-To: <246bd6614529d28dc48b11981ab5dae7a7364fc2.1486337989.git.chunkeey@googlemail.com>
|
||||
References: <246bd6614529d28dc48b11981ab5dae7a7364fc2.1486337989.git.chunkeey@googlemail.com>
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Mon, 13 Jun 2016 15:42:21 +0200
|
||||
Subject: [RFC 2/2] net: emac: add support for device-tree based PHY discovery
|
||||
and setup
|
||||
To: netdev@vger.kernel.org,
|
||||
devicetree@vger.kernel.org
|
||||
Cc: David S. Miller <davem@davemloft.net>,
|
||||
Ivan Mikhaylov <ivan@de.ibm.com>,
|
||||
Mark Rutland <mark.rutland@arm.com>,
|
||||
Rob Herring <robh+dt@kernel.org>
|
||||
|
||||
This patch adds glue-code that allows the EMAC driver to interface
|
||||
with the existing dt-supported PHYs in drivers/net/phy.
|
||||
|
||||
Because currently, the emac driver maintains a small library of
|
||||
supported phys for in a private phy.c file located in the drivers
|
||||
directory.
|
||||
|
||||
The support is limited to mostly single ethernet transceiver like the:
|
||||
CIS8201, BCM5248, ET1011C, Marvell 88E1111 and 88E1112, AR8035.
|
||||
However, routers like the Netgear WNDR4700 and Cisco Meraki MX60(W)
|
||||
have a 5-port switch (QCA8327N) attached to the MDIO of the EMAC.
|
||||
The switch chip has already a proper phy-driver (ar8216) that uses
|
||||
the generic phy library.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
|
||||
---
|
||||
--- a/drivers/net/ethernet/ibm/emac/core.c
|
||||
+++ b/drivers/net/ethernet/ibm/emac/core.c
|
||||
@@ -42,6 +42,7 @@
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_net.h>
|
||||
+#include <linux/of_mdio.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
@@ -2422,6 +2423,229 @@ static int emac_read_uint_prop(struct de
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void emac_adjust_link(struct net_device *ndev)
|
||||
+{
|
||||
+ struct emac_instance *dev = netdev_priv(ndev);
|
||||
+ struct phy_device *phy = dev->phy_dev;
|
||||
+
|
||||
+ dev->phy.autoneg = phy->autoneg;
|
||||
+ dev->phy.speed = phy->speed;
|
||||
+ dev->phy.duplex = phy->duplex;
|
||||
+ dev->phy.pause = phy->pause;
|
||||
+ dev->phy.asym_pause = phy->asym_pause;
|
||||
+ dev->phy.advertising = phy->advertising;
|
||||
+}
|
||||
+
|
||||
+static int emac_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
|
||||
+{
|
||||
+ return emac_mdio_read(bus->priv, addr, regnum);
|
||||
+}
|
||||
+
|
||||
+static int emac_mii_bus_write(struct mii_bus *bus, int addr, int regnum, u16 val)
|
||||
+{
|
||||
+ emac_mdio_write(bus->priv, addr, regnum, val);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int emac_mii_bus_reset(struct mii_bus *bus)
|
||||
+{
|
||||
+ struct emac_instance *dev = netdev_priv(bus->priv);
|
||||
+ int err;
|
||||
+
|
||||
+ err = emac_reset(dev);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+ /* Meraki MX60(W)'s uboot will disable the switch and
|
||||
+ * a bus reset won't do anything. */
|
||||
+ emac_mii_reset_phy(&dev->phy);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise)
|
||||
+{
|
||||
+ struct net_device *ndev = phy->dev;
|
||||
+ struct emac_instance *dev = netdev_priv(ndev);
|
||||
+
|
||||
+ dev->phy.autoneg = AUTONEG_ENABLE;
|
||||
+ dev->phy.speed = SPEED_1000;
|
||||
+ dev->phy.duplex = DUPLEX_FULL;
|
||||
+ dev->phy.advertising = advertise;
|
||||
+ phy->autoneg = AUTONEG_ENABLE;
|
||||
+ phy->speed = dev->phy.speed;
|
||||
+ phy->duplex = dev->phy.duplex;
|
||||
+ phy->advertising = advertise;
|
||||
+ return phy_start_aneg(dev->phy_dev);
|
||||
+}
|
||||
+
|
||||
+static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd)
|
||||
+{
|
||||
+ struct net_device *ndev = phy->dev;
|
||||
+ struct emac_instance *dev = netdev_priv(ndev);
|
||||
+
|
||||
+ dev->phy.autoneg = AUTONEG_DISABLE;
|
||||
+ dev->phy.speed = speed;
|
||||
+ dev->phy.duplex = fd;
|
||||
+ phy->autoneg = AUTONEG_DISABLE;
|
||||
+ phy->speed = speed;
|
||||
+ phy->duplex = fd;
|
||||
+ return phy_start_aneg(dev->phy_dev);
|
||||
+}
|
||||
+
|
||||
+static int emac_mdio_poll_link(struct mii_phy *phy)
|
||||
+{
|
||||
+ struct net_device *ndev = phy->dev;
|
||||
+ struct emac_instance *dev = netdev_priv(ndev);
|
||||
+ int res;
|
||||
+
|
||||
+ res = phy_read_status(dev->phy_dev);
|
||||
+ if (res) {
|
||||
+ dev_err(&dev->ofdev->dev, "link update failed (%d).", res);
|
||||
+ return ethtool_op_get_link(ndev);
|
||||
+ }
|
||||
+
|
||||
+ return dev->phy_dev->link;
|
||||
+}
|
||||
+
|
||||
+static int emac_mdio_read_link(struct mii_phy *phy)
|
||||
+{
|
||||
+ struct net_device *ndev = phy->dev;
|
||||
+ struct emac_instance *dev = netdev_priv(ndev);
|
||||
+ int res;
|
||||
+
|
||||
+ res = phy_read_status(dev->phy_dev);
|
||||
+ if (res)
|
||||
+ return res;
|
||||
+
|
||||
+ dev->phy.speed = phy->speed;
|
||||
+ dev->phy.duplex = phy->duplex;
|
||||
+ dev->phy.pause = phy->pause;
|
||||
+ dev->phy.asym_pause = phy->asym_pause;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int emac_mdio_init_phy(struct mii_phy *phy)
|
||||
+{
|
||||
+ struct net_device *ndev = phy->dev;
|
||||
+ struct emac_instance *dev = netdev_priv(ndev);
|
||||
+
|
||||
+ phy_start(dev->phy_dev);
|
||||
+ dev->phy.autoneg = phy->autoneg;
|
||||
+ dev->phy.speed = phy->speed;
|
||||
+ dev->phy.duplex = phy->duplex;
|
||||
+ dev->phy.advertising = phy->advertising;
|
||||
+ dev->phy.pause = phy->pause;
|
||||
+ dev->phy.asym_pause = phy->asym_pause;
|
||||
+
|
||||
+ return phy_init_hw(dev->phy_dev);
|
||||
+}
|
||||
+
|
||||
+static const struct mii_phy_ops emac_dt_mdio_phy_ops = {
|
||||
+ .init = emac_mdio_init_phy,
|
||||
+ .setup_aneg = emac_mdio_setup_aneg,
|
||||
+ .setup_forced = emac_mdio_setup_forced,
|
||||
+ .poll_link = emac_mdio_poll_link,
|
||||
+ .read_link = emac_mdio_read_link,
|
||||
+};
|
||||
+
|
||||
+static int emac_dt_mdio_probe(struct emac_instance *dev)
|
||||
+{
|
||||
+ struct device_node *mii_np;
|
||||
+ int res;
|
||||
+
|
||||
+ mii_np = of_get_child_by_name(dev->ofdev->dev.of_node, "mdio");
|
||||
+ if (!mii_np) {
|
||||
+ dev_err(&dev->ofdev->dev, "no mdio definition found.");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ if (!of_device_is_available(mii_np)) {
|
||||
+ res = 1;
|
||||
+ goto put_node;
|
||||
+ }
|
||||
+
|
||||
+ dev->mii_bus = devm_mdiobus_alloc(&dev->ofdev->dev);
|
||||
+ if (!dev->mii_bus) {
|
||||
+ res = -ENOMEM;
|
||||
+ goto put_node;
|
||||
+ }
|
||||
+
|
||||
+ dev->mii_bus->priv = dev->ndev;
|
||||
+ dev->mii_bus->parent = dev->ndev->dev.parent;
|
||||
+ dev->mii_bus->name = "emac_mdio";
|
||||
+ dev->mii_bus->read = &emac_mii_bus_read;
|
||||
+ dev->mii_bus->write = &emac_mii_bus_write;
|
||||
+ dev->mii_bus->reset = &emac_mii_bus_reset;
|
||||
+ snprintf(dev->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name);
|
||||
+ res = of_mdiobus_register(dev->mii_bus, mii_np);
|
||||
+ if (res) {
|
||||
+ dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)",
|
||||
+ dev->mii_bus->name, res);
|
||||
+ }
|
||||
+
|
||||
+ put_node:
|
||||
+ of_node_put(mii_np);
|
||||
+ return res;
|
||||
+}
|
||||
+
|
||||
+static int emac_dt_phy_probe(struct emac_instance *dev,
|
||||
+ struct device_node *phy_handle)
|
||||
+{
|
||||
+ u32 phy_flags = 0;
|
||||
+ int res;
|
||||
+
|
||||
+ res = of_property_read_u32(phy_handle, "phy-flags", &phy_flags);
|
||||
+ if (res < 0 && res != -EINVAL)
|
||||
+ return res;
|
||||
+
|
||||
+ dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!dev->phy.def)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ dev->phy_dev = of_phy_connect(dev->ndev, phy_handle,
|
||||
+ &emac_adjust_link, phy_flags,
|
||||
+ PHY_INTERFACE_MODE_RGMII);
|
||||
+ if (!dev->phy_dev) {
|
||||
+ dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ dev->phy.def->phy_id = dev->phy_dev->drv->phy_id;
|
||||
+ dev->phy.def->phy_id_mask = dev->phy_dev->drv->phy_id_mask;
|
||||
+ dev->phy.def->name = dev->phy_dev->drv->name;
|
||||
+ dev->phy.def->ops = &emac_dt_mdio_phy_ops;
|
||||
+ dev->phy.features = dev->phy_dev->supported;
|
||||
+ dev->phy.address = dev->phy_dev->mdio.addr;
|
||||
+ dev->phy.mode = dev->phy_dev->interface;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int emac_probe_dt_phy(struct emac_instance *dev)
|
||||
+{
|
||||
+ struct device_node *np = dev->ofdev->dev.of_node;
|
||||
+ struct device_node *phy_handle;
|
||||
+ int res = 0;
|
||||
+
|
||||
+ phy_handle = of_parse_phandle(np, "phy-handle", 0);
|
||||
+
|
||||
+ if (phy_handle) {
|
||||
+ res = emac_dt_mdio_probe(dev);
|
||||
+ if (!res) {
|
||||
+ res = emac_dt_phy_probe(dev, phy_handle);
|
||||
+ if (!res)
|
||||
+ res = 1;
|
||||
+ else
|
||||
+ mdiobus_unregister(dev->mii_bus);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ of_node_put(phy_handle);
|
||||
+ /* if no phy device was specified in the device tree, then we fallback
|
||||
+ * to the old emac_phy.c probe code for compatibility reasons.
|
||||
+ */
|
||||
+ return res;
|
||||
+}
|
||||
+
|
||||
static int emac_init_phy(struct emac_instance *dev)
|
||||
{
|
||||
struct device_node *np = dev->ofdev->dev.of_node;
|
||||
@@ -2492,6 +2716,22 @@ static int emac_init_phy(struct emac_ins
|
||||
|
||||
emac_configure(dev);
|
||||
|
||||
+ if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
|
||||
+ int res = emac_probe_dt_phy(dev);
|
||||
+
|
||||
+ if (res == 1) {
|
||||
+ mutex_unlock(&emac_phy_map_lock);
|
||||
+ goto init_phy;
|
||||
+ } else if (res < 0) {
|
||||
+ mutex_unlock(&emac_phy_map_lock);
|
||||
+ dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n",
|
||||
+ res);
|
||||
+ return res;
|
||||
+ }
|
||||
+
|
||||
+ /* continue with old code */
|
||||
+ }
|
||||
+
|
||||
if (dev->phy_address != 0xffffffff)
|
||||
phy_map = ~(1 << dev->phy_address);
|
||||
|
||||
@@ -2519,6 +2759,7 @@ static int emac_init_phy(struct emac_ins
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
+ init_phy:
|
||||
/* Init PHY */
|
||||
if (dev->phy.def->ops->init)
|
||||
dev->phy.def->ops->init(&dev->phy);
|
||||
@@ -2988,6 +3229,12 @@ static int emac_remove(struct platform_d
|
||||
if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
|
||||
zmii_detach(dev->zmii_dev, dev->zmii_port);
|
||||
|
||||
+ if (dev->phy_dev)
|
||||
+ phy_disconnect(dev->phy_dev);
|
||||
+
|
||||
+ if (dev->mii_bus)
|
||||
+ mdiobus_unregister(dev->mii_bus);
|
||||
+
|
||||
busy_phy_map &= ~(1 << dev->phy.address);
|
||||
DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map);
|
||||
|
||||
--- a/drivers/net/ethernet/ibm/emac/core.h
|
||||
+++ b/drivers/net/ethernet/ibm/emac/core.h
|
||||
@@ -199,6 +199,10 @@ struct emac_instance {
|
||||
struct emac_instance *mdio_instance;
|
||||
struct mutex mdio_lock;
|
||||
|
||||
+ /* Device-tree based phy configuration */
|
||||
+ struct mii_bus *mii_bus;
|
||||
+ struct phy_device *phy_dev;
|
||||
+
|
||||
/* ZMII infos if any */
|
||||
u32 zmii_ph;
|
||||
u32 zmii_port;
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
From b2e79053e7456a961249c8865214a1e95b49c863 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Date: Sat, 3 Jun 2017 18:16:19 +0200
|
||||
Subject: [PATCH] net: emac: fix reset timeout with AR8035 phy
|
||||
|
||||
This patch fixes a problem where the AR8035 PHY can't be
|
||||
detected on an Cisco Meraki MR24, if the ethernet cable is
|
||||
not connected on boot.
|
||||
|
||||
Russell Senior provided steps to reproduce the issue:
|
||||
|Disconnect ethernet cable, apply power, wait until device has booted,
|
||||
|plug in ethernet, check for interfaces, no eth0 is listed.
|
||||
|
|
||||
|This appears to be a problem during probing of the AR8035 Phy chip.
|
||||
|When ethernet has no link, the phy detection fails, and eth0 is not
|
||||
|created. Plugging ethernet later has no effect, because there is no
|
||||
|interface as far as the kernel is concerned. The relevant part of
|
||||
|the boot log looks like this:
|
||||
|this is the failing case:
|
||||
|
|
||||
|[ 0.876611] /plb/opb/emac-rgmii@ef601500: input 0 in RGMII mode
|
||||
|[ 0.882532] /plb/opb/ethernet@ef600c00: reset timeout
|
||||
|[ 0.888546] /plb/opb/ethernet@ef600c00: can't find PHY!
|
||||
|and the succeeding case:
|
||||
|
|
||||
|[ 0.876672] /plb/opb/emac-rgmii@ef601500: input 0 in RGMII mode
|
||||
|[ 0.883952] eth0: EMAC-0 /plb/opb/ethernet@ef600c00, MAC 00:01:..
|
||||
|[ 0.890822] eth0: found Atheros 8035 Gigabit Ethernet PHY (0x01)
|
||||
|
||||
Based on the comment and the commit message of
|
||||
commit 23fbb5a87c56 ("emac: Fix EMAC soft reset on 460EX/GT").
|
||||
This is because the AR8035 PHY doesn't provide the TX Clock,
|
||||
if the ethernet cable is not attached. This causes the reset
|
||||
to timeout and the PHY detection code in emac_init_phy() is
|
||||
unable to detect the AR8035 PHY. As a result, the emac driver
|
||||
bails out early and the user left with no ethernet.
|
||||
|
||||
In order to stay compatible with existing configurations, the driver
|
||||
tries the current reset approach at first. Only if the first attempt
|
||||
timed out, it does perform one more retry with the clock input
|
||||
temporarily switched to the internal clock source for just the
|
||||
duration of the reset.
|
||||
|
||||
LEDE-Bug: #687 <https://bugs.lede-project.org/index.php?do=details&task_id=687>
|
||||
|
||||
Cc: Chris Blake <chrisrblake93@gmail.com>
|
||||
Reported-by: Russell Senior <russell@personaltelco.net>
|
||||
Fixes: 23fbb5a87c56e98 ("emac: Fix EMAC soft reset on 460EX/GT")
|
||||
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
|
||||
---
|
||||
drivers/net/ethernet/ibm/emac/core.c | 26 ++++++++++++++++++++++----
|
||||
1 file changed, 22 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/ibm/emac/core.c
|
||||
+++ b/drivers/net/ethernet/ibm/emac/core.c
|
||||
@@ -352,6 +352,7 @@ static int emac_reset(struct emac_instan
|
||||
{
|
||||
struct emac_regs __iomem *p = dev->emacp;
|
||||
int n = 20;
|
||||
+ bool __maybe_unused try_internal_clock = false;
|
||||
|
||||
DBG(dev, "reset" NL);
|
||||
|
||||
@@ -364,6 +365,7 @@ static int emac_reset(struct emac_instan
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC_DCR_NATIVE
|
||||
+do_retry:
|
||||
/*
|
||||
* PPC460EX/GT Embedded Processor Advanced User's Manual
|
||||
* section 28.10.1 Mode Register 0 (EMACx_MR0) states:
|
||||
@@ -371,10 +373,19 @@ static int emac_reset(struct emac_instan
|
||||
* of the EMAC. If none is present, select the internal clock
|
||||
* (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
|
||||
* After a soft reset, select the external clock.
|
||||
+ *
|
||||
+ * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the
|
||||
+ * ethernet cable is not attached. This causes the reset to timeout
|
||||
+ * and the PHY detection code in emac_init_phy() is unable to
|
||||
+ * communicate and detect the AR8035-A PHY. As a result, the emac
|
||||
+ * driver bails out early and the user has no ethernet.
|
||||
+ * In order to stay compatible with existing configurations, the
|
||||
+ * driver will temporarily switch to the internal clock, after
|
||||
+ * the first reset fails.
|
||||
*/
|
||||
if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
|
||||
- if (dev->phy_address == 0xffffffff &&
|
||||
- dev->phy_map == 0xffffffff) {
|
||||
+ if (try_internal_clock || (dev->phy_address == 0xffffffff &&
|
||||
+ dev->phy_map == 0xffffffff)) {
|
||||
/* No PHY: select internal loop clock before reset */
|
||||
dcri_clrset(SDR0, SDR0_ETH_CFG,
|
||||
0, SDR0_ETH_CFG_ECS << dev->cell_index);
|
||||
@@ -392,8 +403,15 @@ static int emac_reset(struct emac_instan
|
||||
|
||||
#ifdef CONFIG_PPC_DCR_NATIVE
|
||||
if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
|
||||
- if (dev->phy_address == 0xffffffff &&
|
||||
- dev->phy_map == 0xffffffff) {
|
||||
+ if (!n && !try_internal_clock) {
|
||||
+ /* first attempt has timed out. */
|
||||
+ n = 20;
|
||||
+ try_internal_clock = true;
|
||||
+ goto do_retry;
|
||||
+ }
|
||||
+
|
||||
+ if (try_internal_clock || (dev->phy_address == 0xffffffff &&
|
||||
+ dev->phy_map == 0xffffffff)) {
|
||||
/* No PHY: restore external clock source after reset */
|
||||
dcri_clrset(SDR0, SDR0_ETH_CFG,
|
||||
SDR0_ETH_CFG_ECS << dev->cell_index, 0);
|
||||
|
|
@ -1,545 +0,0 @@
|
|||
From 419992bae5aaa4e06402e0b7c79fcf7bcb6b4764 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@googlemail.com>
|
||||
Date: Thu, 2 Jun 2016 00:48:46 +0200
|
||||
Subject: [PATCH] usb: xhci: add firmware loader for uPD720201 and uPD720202
|
||||
w/o ROM
|
||||
|
||||
This patch adds a firmware loader for the uPD720201K8-711-BAC-A
|
||||
and uPD720202K8-711-BAA-A variant. Both of these chips are listed
|
||||
in Renesas' R19UH0078EJ0500 Rev.5.00 "User's Manual: Hardware" as
|
||||
devices which need the firmware loader on page 2 in order to
|
||||
work as they "do not support the External ROM".
|
||||
|
||||
The "Firmware Download Sequence" is describe in chapter
|
||||
"7.1 FW Download Interface" R19UH0078EJ0500 Rev.5.00 page 131.
|
||||
|
||||
The firmware "K2013080.mem" is available from a USB3.0 Host to
|
||||
PCIe Adapter (PP2U-E card) "Firmware download" archive. An
|
||||
alternative version can be sourced from Netgear's WNDR4700 GPL
|
||||
archives.
|
||||
|
||||
The release notes of the PP2U-E's "Firmware Download" ver 2.0.1.3
|
||||
(2012-06-15) state that the firmware is for the following devices:
|
||||
- uPD720201 ES 2.0 sample whose revision ID is 2.
|
||||
- uPD720201 ES 2.1 sample & CS sample & Mass product, ID is 3.
|
||||
- uPD720202 ES 2.0 sample & CS sample & Mass product, ID is 2.
|
||||
|
||||
If someone from Renesas is listening: It would be great, if these
|
||||
firmwares could be added to linux-firmware.git.
|
||||
|
||||
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
|
||||
---
|
||||
drivers/usb/host/xhci-pci.c | 492 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 492 insertions(+)
|
||||
|
||||
--- a/drivers/usb/host/xhci-pci.c
|
||||
+++ b/drivers/usb/host/xhci-pci.c
|
||||
@@ -24,6 +24,8 @@
|
||||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/acpi.h>
|
||||
+#include <linux/firmware.h>
|
||||
+#include <asm/unaligned.h>
|
||||
|
||||
#include "xhci.h"
|
||||
#include "xhci-trace.h"
|
||||
@@ -239,6 +241,458 @@ static void xhci_pme_acpi_rtd3_enable(st
|
||||
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
|
||||
#endif /* CONFIG_ACPI */
|
||||
|
||||
+static const struct renesas_fw_entry {
|
||||
+ const char *firmware_name;
|
||||
+ u16 device;
|
||||
+ u8 revision;
|
||||
+ u16 expected_version;
|
||||
+} renesas_fw_table[] = {
|
||||
+ /*
|
||||
+ * Only the uPD720201K8-711-BAC-A or uPD720202K8-711-BAA-A
|
||||
+ * are listed in R19UH0078EJ0500 Rev.5.00 as devices which
|
||||
+ * need the software loader.
|
||||
+ *
|
||||
+ * PP2U/ReleaseNote_USB3-201-202-FW.txt:
|
||||
+ *
|
||||
+ * Note: This firmware is for the following devices.
|
||||
+ * - uPD720201 ES 2.0 sample whose revision ID is 2.
|
||||
+ * - uPD720201 ES 2.1 sample & CS sample & Mass product, ID is 3.
|
||||
+ * - uPD720202 ES 2.0 sample & CS sample & Mass product, ID is 2.
|
||||
+ */
|
||||
+ { "K2013080.mem", 0x0014, 0x02, 0x2013 },
|
||||
+ { "K2013080.mem", 0x0014, 0x03, 0x2013 },
|
||||
+ { "K2013080.mem", 0x0015, 0x02, 0x2013 },
|
||||
+};
|
||||
+
|
||||
+static const struct renesas_fw_entry *renesas_needs_fw_dl(struct pci_dev *dev)
|
||||
+{
|
||||
+ const struct renesas_fw_entry *entry;
|
||||
+ size_t i;
|
||||
+
|
||||
+ /* This loader will only work with a RENESAS device. */
|
||||
+ if (!(dev->vendor == PCI_VENDOR_ID_RENESAS))
|
||||
+ return NULL;
|
||||
+
|
||||
+ for (i = 0; i < ARRAY_SIZE(renesas_fw_table); i++) {
|
||||
+ entry = &renesas_fw_table[i];
|
||||
+ if (entry->device == dev->device &&
|
||||
+ entry->revision == dev->revision)
|
||||
+ return entry;
|
||||
+ }
|
||||
+
|
||||
+ return NULL;
|
||||
+}
|
||||
+
|
||||
+static int renesas_fw_download_image(struct pci_dev *dev,
|
||||
+ const u32 *fw,
|
||||
+ size_t step)
|
||||
+{
|
||||
+ size_t i;
|
||||
+ int err;
|
||||
+ u8 fw_status;
|
||||
+ bool data0_or_data1;
|
||||
+
|
||||
+ /*
|
||||
+ * The hardware does alternate between two 32-bit pages.
|
||||
+ * (This is because each row of the firmware is 8 bytes).
|
||||
+ *
|
||||
+ * for even steps we use DATA0, for odd steps DATA1.
|
||||
+ */
|
||||
+ data0_or_data1 = (step & 1) == 1;
|
||||
+
|
||||
+ /* step+1. Read "Set DATAX" and confirm it is cleared. */
|
||||
+ for (i = 0; i < 10000; i++) {
|
||||
+ err = pci_read_config_byte(dev, 0xF5, &fw_status);
|
||||
+ if (err)
|
||||
+ return pcibios_err_to_errno(err);
|
||||
+ if (!(fw_status & BIT(data0_or_data1)))
|
||||
+ break;
|
||||
+
|
||||
+ udelay(1);
|
||||
+ }
|
||||
+ if (i == 10000)
|
||||
+ return -ETIMEDOUT;
|
||||
+
|
||||
+ /*
|
||||
+ * step+2. Write FW data to "DATAX".
|
||||
+ * "LSB is left" => force little endian
|
||||
+ */
|
||||
+ err = pci_write_config_dword(dev, data0_or_data1 ? 0xFC : 0xF8,
|
||||
+ (__force u32) cpu_to_le32(fw[step]));
|
||||
+ if (err)
|
||||
+ return pcibios_err_to_errno(err);
|
||||
+
|
||||
+ udelay(100);
|
||||
+
|
||||
+ /* step+3. Set "Set DATAX". */
|
||||
+ err = pci_write_config_byte(dev, 0xF5, BIT(data0_or_data1));
|
||||
+ if (err)
|
||||
+ return pcibios_err_to_errno(err);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int renesas_fw_verify(struct pci_dev *dev,
|
||||
+ const void *fw_data,
|
||||
+ size_t length)
|
||||
+{
|
||||
+ const struct renesas_fw_entry *entry = renesas_needs_fw_dl(dev);
|
||||
+ u16 fw_version_pointer;
|
||||
+ u16 fw_version;
|
||||
+
|
||||
+ if (!entry)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ /*
|
||||
+ * The Firmware's Data Format is describe in
|
||||
+ * "6.3 Data Format" R19UH0078EJ0500 Rev.5.00 page 124
|
||||
+ */
|
||||
+
|
||||
+ /* "Each row is 8 bytes". => firmware size must be a multiple of 8. */
|
||||
+ if (length % 8 != 0) {
|
||||
+ dev_err(&dev->dev, "firmware size is not a multipe of 8.");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * The bootrom chips of the big brother have sizes up to 64k, let's
|
||||
+ * assume that's the biggest the firmware can get.
|
||||
+ */
|
||||
+ if (length < 0x1000 || length >= 0x10000) {
|
||||
+ dev_err(&dev->dev, "firmware is size %zd is not (4k - 64k).",
|
||||
+ length);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ /* The First 2 bytes are fixed value (55aa). "LSB on Left" */
|
||||
+ if (get_unaligned_le16(fw_data) != 0x55aa) {
|
||||
+ dev_err(&dev->dev, "no valid firmware header found.");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ /* verify the firmware version position and print it. */
|
||||
+ fw_version_pointer = get_unaligned_le16(fw_data + 4);
|
||||
+ if (fw_version_pointer + 2 >= length) {
|
||||
+ dev_err(&dev->dev, "firmware version pointer is outside of the firmware image.");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ fw_version = get_unaligned_le16(fw_data + fw_version_pointer);
|
||||
+ dev_dbg(&dev->dev, "got firmware version: %02x.", fw_version);
|
||||
+
|
||||
+ if (fw_version != entry->expected_version) {
|
||||
+ dev_err(&dev->dev, "firmware version mismatch, expected version: %02x.",
|
||||
+ entry->expected_version);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int renesas_fw_check_running(struct pci_dev *pdev)
|
||||
+{
|
||||
+ int err;
|
||||
+ u8 fw_state;
|
||||
+
|
||||
+ /*
|
||||
+ * Test if the device is actually needing the firmware. As most
|
||||
+ * BIOSes will initialize the device for us. If the device is
|
||||
+ * initialized.
|
||||
+ */
|
||||
+ err = pci_read_config_byte(pdev, 0xF4, &fw_state);
|
||||
+ if (err)
|
||||
+ return pcibios_err_to_errno(err);
|
||||
+
|
||||
+ /*
|
||||
+ * Check if "FW Download Lock" is locked. If it is and the FW is
|
||||
+ * ready we can simply continue. If the FW is not ready, we have
|
||||
+ * to give up.
|
||||
+ */
|
||||
+ if (fw_state & BIT(1)) {
|
||||
+ dev_dbg(&pdev->dev, "FW Download Lock is engaged.");
|
||||
+
|
||||
+ if (fw_state & BIT(4))
|
||||
+ return 0;
|
||||
+
|
||||
+ dev_err(&pdev->dev, "FW Download Lock is set and FW is not ready. Giving Up.");
|
||||
+ return -EIO;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * Check if "FW Download Enable" is set. If someone (us?) tampered
|
||||
+ * with it and it can't be resetted, we have to give up too... and
|
||||
+ * ask for a forgiveness and a reboot.
|
||||
+ */
|
||||
+ if (fw_state & BIT(0)) {
|
||||
+ dev_err(&pdev->dev, "FW Download Enable is stale. Giving Up (poweroff/reboot needed).");
|
||||
+ return -EIO;
|
||||
+ }
|
||||
+
|
||||
+ /* Otherwise, Check the "Result Code" Bits (6:4) and act accordingly */
|
||||
+ switch ((fw_state & 0x70)) {
|
||||
+ case 0: /* No result yet */
|
||||
+ dev_dbg(&pdev->dev, "FW is not ready/loaded yet.");
|
||||
+
|
||||
+ /* tell the caller, that this device needs the firmware. */
|
||||
+ return 1;
|
||||
+
|
||||
+ case BIT(4): /* Success, device should be working. */
|
||||
+ dev_dbg(&pdev->dev, "FW is ready.");
|
||||
+ return 0;
|
||||
+
|
||||
+ case BIT(5): /* Error State */
|
||||
+ dev_err(&pdev->dev, "hardware is in an error state. Giving up (poweroff/reboot needed).");
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ default: /* All other states are marked as "Reserved states" */
|
||||
+ dev_err(&pdev->dev, "hardware is in an invalid state %x. Giving up (poweroff/reboot needed).",
|
||||
+ (fw_state & 0x70) >> 4);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int renesas_hw_check_run_stop_busy(struct pci_dev *pdev)
|
||||
+{
|
||||
+#if 0
|
||||
+ u32 val;
|
||||
+
|
||||
+ /*
|
||||
+ * 7.1.3 Note 3: "... must not set 'FW Download Enable' when
|
||||
+ * 'RUN/STOP' of USBCMD Register is set"
|
||||
+ */
|
||||
+ val = readl(hcd->regs + 0x20);
|
||||
+ if (val & BIT(0)) {
|
||||
+ dev_err(&pdev->dev, "hardware is busy and can't receive a FW.");
|
||||
+ return -EBUSY;
|
||||
+ }
|
||||
+#endif
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int renesas_fw_download(struct pci_dev *pdev,
|
||||
+ const struct firmware *fw, unsigned int retry_counter)
|
||||
+{
|
||||
+ const u32 *fw_data = (const u32 *) fw->data;
|
||||
+ size_t i;
|
||||
+ int err;
|
||||
+ u8 fw_status;
|
||||
+
|
||||
+ /*
|
||||
+ * For more information and the big picture: please look at the
|
||||
+ * "Firmware Download Sequence" in "7.1 FW Download Interface"
|
||||
+ * of R19UH0078EJ0500 Rev.5.00 page 131
|
||||
+ */
|
||||
+ err = renesas_hw_check_run_stop_busy(pdev);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+
|
||||
+ /*
|
||||
+ * 0. Set "FW Download Enable" bit in the
|
||||
+ * "FW Download Control & Status Register" at 0xF4
|
||||
+ */
|
||||
+ err = pci_write_config_byte(pdev, 0xF4, BIT(0));
|
||||
+ if (err)
|
||||
+ return pcibios_err_to_errno(err);
|
||||
+
|
||||
+ /* 1 - 10 follow one step after the other. */
|
||||
+ for (i = 0; i < fw->size / 4; i++) {
|
||||
+ err = renesas_fw_download_image(pdev, fw_data, i);
|
||||
+ if (err) {
|
||||
+ dev_err(&pdev->dev, "Firmware Download Step %zd failed at position %zd bytes with (%d).",
|
||||
+ i, i * 4, err);
|
||||
+ return err;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * This sequence continues until the last data is written to
|
||||
+ * "DATA0" or "DATA1". Naturally, we wait until "SET DATA0/1"
|
||||
+ * is cleared by the hardware beforehand.
|
||||
+ */
|
||||
+ for (i = 0; i < 10000; i++) {
|
||||
+ err = pci_read_config_byte(pdev, 0xF5, &fw_status);
|
||||
+ if (err)
|
||||
+ return pcibios_err_to_errno(err);
|
||||
+ if (!(fw_status & (BIT(0) | BIT(1))))
|
||||
+ break;
|
||||
+
|
||||
+ udelay(1);
|
||||
+ }
|
||||
+ if (i == 10000)
|
||||
+ dev_warn(&pdev->dev, "Final Firmware Download step timed out.");
|
||||
+
|
||||
+ /*
|
||||
+ * 11. After finishing writing the last data of FW, the
|
||||
+ * System Software must clear "FW Download Enable"
|
||||
+ */
|
||||
+ err = pci_write_config_byte(pdev, 0xF4, 0);
|
||||
+ if (err)
|
||||
+ return pcibios_err_to_errno(err);
|
||||
+
|
||||
+ /* 12. Read "Result Code" and confirm it is good. */
|
||||
+ for (i = 0; i < 10000; i++) {
|
||||
+ err = pci_read_config_byte(pdev, 0xF4, &fw_status);
|
||||
+ if (err)
|
||||
+ return pcibios_err_to_errno(err);
|
||||
+ if (fw_status & BIT(4))
|
||||
+ break;
|
||||
+
|
||||
+ udelay(1);
|
||||
+ }
|
||||
+ if (i == 10000) {
|
||||
+ /* Timed out / Error - let's see if we can fix this */
|
||||
+ err = renesas_fw_check_running(pdev);
|
||||
+ switch (err) {
|
||||
+ case 0: /*
|
||||
+ * we shouldn't end up here.
|
||||
+ * maybe it took a little bit longer.
|
||||
+ * But all should be well?
|
||||
+ */
|
||||
+ break;
|
||||
+
|
||||
+ case 1: /* (No result yet? - we can try to retry) */
|
||||
+ if (retry_counter < 10) {
|
||||
+ retry_counter++;
|
||||
+ dev_warn(&pdev->dev, "Retry Firmware download: %d try.",
|
||||
+ retry_counter);
|
||||
+ return renesas_fw_download(pdev, fw,
|
||||
+ retry_counter);
|
||||
+ }
|
||||
+ return -ETIMEDOUT;
|
||||
+
|
||||
+ default:
|
||||
+ return err;
|
||||
+ }
|
||||
+ }
|
||||
+ /*
|
||||
+ * Optional last step: Engage Firmware Lock
|
||||
+ *
|
||||
+ * err = pci_write_config_byte(pdev, 0xF4, BIT(2));
|
||||
+ * if (err)
|
||||
+ * return pcibios_err_to_errno(err);
|
||||
+ */
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+struct renesas_fw_ctx {
|
||||
+ struct pci_dev *pdev;
|
||||
+ const struct pci_device_id *id;
|
||||
+ bool resume;
|
||||
+};
|
||||
+
|
||||
+static int xhci_pci_probe(struct pci_dev *pdev,
|
||||
+ const struct pci_device_id *id);
|
||||
+
|
||||
+static void renesas_fw_callback(const struct firmware *fw,
|
||||
+ void *context)
|
||||
+{
|
||||
+ struct renesas_fw_ctx *ctx = context;
|
||||
+ struct pci_dev *pdev = ctx->pdev;
|
||||
+ struct device *parent = pdev->dev.parent;
|
||||
+ int err = -ENOENT;
|
||||
+
|
||||
+ if (fw) {
|
||||
+ err = renesas_fw_verify(pdev, fw->data, fw->size);
|
||||
+ if (!err) {
|
||||
+ err = renesas_fw_download(pdev, fw, 0);
|
||||
+ release_firmware(fw);
|
||||
+ if (!err) {
|
||||
+ if (ctx->resume)
|
||||
+ return;
|
||||
+
|
||||
+ err = xhci_pci_probe(pdev, ctx->id);
|
||||
+ if (!err) {
|
||||
+ /* everything worked */
|
||||
+ devm_kfree(&pdev->dev, ctx);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ /* in case of an error - fall through */
|
||||
+ } else {
|
||||
+ dev_err(&pdev->dev, "firmware failed to download (%d).",
|
||||
+ err);
|
||||
+ }
|
||||
+ }
|
||||
+ } else {
|
||||
+ dev_err(&pdev->dev, "firmware failed to load (%d).", err);
|
||||
+ }
|
||||
+
|
||||
+ dev_info(&pdev->dev, "Unloading driver");
|
||||
+
|
||||
+ if (parent)
|
||||
+ device_lock(parent);
|
||||
+
|
||||
+ device_release_driver(&pdev->dev);
|
||||
+
|
||||
+ if (parent)
|
||||
+ device_unlock(parent);
|
||||
+
|
||||
+ pci_dev_put(pdev);
|
||||
+}
|
||||
+
|
||||
+static int renesas_fw_alive_check(struct pci_dev *pdev)
|
||||
+{
|
||||
+ const struct renesas_fw_entry *entry;
|
||||
+ int err;
|
||||
+
|
||||
+ /* check if we have a eligible RENESAS' uPD720201/2 w/o FW. */
|
||||
+ entry = renesas_needs_fw_dl(pdev);
|
||||
+ if (!entry)
|
||||
+ return 0;
|
||||
+
|
||||
+ err = renesas_fw_check_running(pdev);
|
||||
+ /* Also go ahead, if the firmware is running */
|
||||
+ if (err == 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ /* At this point, we can be sure that the FW isn't ready. */
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static int renesas_fw_download_to_hw(struct pci_dev *pdev,
|
||||
+ const struct pci_device_id *id,
|
||||
+ bool do_resume)
|
||||
+{
|
||||
+ const struct renesas_fw_entry *entry;
|
||||
+ struct renesas_fw_ctx *ctx;
|
||||
+ int err;
|
||||
+
|
||||
+ /* check if we have a eligible RENESAS' uPD720201/2 w/o FW. */
|
||||
+ entry = renesas_needs_fw_dl(pdev);
|
||||
+ if (!entry)
|
||||
+ return 0;
|
||||
+
|
||||
+ err = renesas_fw_check_running(pdev);
|
||||
+ /* Continue ahead, if the firmware is already running. */
|
||||
+ if (err == 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (err != 1)
|
||||
+ return err;
|
||||
+
|
||||
+ ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
|
||||
+ if (!ctx)
|
||||
+ return -ENOMEM;
|
||||
+ ctx->pdev = pdev;
|
||||
+ ctx->resume = do_resume;
|
||||
+ ctx->id = id;
|
||||
+
|
||||
+ pci_dev_get(pdev);
|
||||
+ err = request_firmware_nowait(THIS_MODULE, 1, entry->firmware_name,
|
||||
+ &pdev->dev, GFP_KERNEL, ctx, renesas_fw_callback);
|
||||
+ if (err) {
|
||||
+ pci_dev_put(pdev);
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * The renesas_fw_callback() callback will continue the probe
|
||||
+ * process, once it aquires the firmware.
|
||||
+ */
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
/* called during probe() after chip reset completes */
|
||||
static int xhci_pci_setup(struct usb_hcd *hcd)
|
||||
{
|
||||
@@ -278,6 +732,22 @@ static int xhci_pci_probe(struct pci_dev
|
||||
struct hc_driver *driver;
|
||||
struct usb_hcd *hcd;
|
||||
|
||||
+ /*
|
||||
+ * Check if this device is a RENESAS uPD720201/2 device.
|
||||
+ * Otherwise, we can continue with xhci_pci_probe as usual.
|
||||
+ */
|
||||
+ retval = renesas_fw_download_to_hw(dev, id, false);
|
||||
+ switch (retval) {
|
||||
+ case 0:
|
||||
+ break;
|
||||
+
|
||||
+ case 1: /* let it load the firmware and recontinue the probe. */
|
||||
+ return 0;
|
||||
+
|
||||
+ default:
|
||||
+ return retval;
|
||||
+ };
|
||||
+
|
||||
driver = (struct hc_driver *)id->driver_data;
|
||||
|
||||
/* Prevent runtime suspending between USB-2 and USB-3 initialization */
|
||||
@@ -335,6 +805,16 @@ static void xhci_pci_remove(struct pci_d
|
||||
{
|
||||
struct xhci_hcd *xhci;
|
||||
|
||||
+ if (renesas_fw_alive_check(dev)) {
|
||||
+ /*
|
||||
+ * bail out early, if this was a renesas device w/o FW.
|
||||
+ * Else we might hit the NMI watchdog in xhci_handsake
|
||||
+ * during xhci_reset as part of the driver's unloading.
|
||||
+ * which we forced in the renesas_fw_callback().
|
||||
+ */
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
xhci = hcd_to_xhci(pci_get_drvdata(dev));
|
||||
xhci->xhc_state |= XHCI_STATE_REMOVING;
|
||||
if (xhci->shared_hcd) {
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
From a0dc613140bab907a3d5787a7ae7b0638bf674d0 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Thu, 23 Jun 2016 20:28:20 +0200
|
||||
Subject: [PATCH] usb: xhci: force MSI for uPD720201 and
|
||||
uPD720202
|
||||
|
||||
The APM82181 does not support MSI-X. When probed, it will
|
||||
produce a noisy warning.
|
||||
|
||||
---
|
||||
drivers/usb/host/pci-quirks.c | 362 ++++++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 362 insertions(+)
|
||||
|
||||
--- a/drivers/usb/host/xhci-pci.c
|
||||
+++ b/drivers/usb/host/xhci-pci.c
|
||||
@@ -196,7 +196,7 @@ static void xhci_pci_quirks(struct devic
|
||||
xhci->quirks |= XHCI_TRUST_TX_LENGTH;
|
||||
if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
|
||||
pdev->device == 0x0015)
|
||||
- xhci->quirks |= XHCI_RESET_ON_RESUME;
|
||||
+ xhci->quirks |= XHCI_RESET_ON_RESUME | XHCI_FORCE_MSI;
|
||||
if (pdev->vendor == PCI_VENDOR_ID_VIA)
|
||||
xhci->quirks |= XHCI_RESET_ON_RESUME;
|
||||
|
||||
--- a/drivers/usb/host/xhci.c
|
||||
+++ b/drivers/usb/host/xhci.c
|
||||
@@ -390,10 +390,14 @@ static int xhci_try_enable_msi(struct us
|
||||
free_irq(hcd->irq, hcd);
|
||||
hcd->irq = 0;
|
||||
|
||||
- ret = xhci_setup_msix(xhci);
|
||||
- if (ret)
|
||||
- /* fall back to msi*/
|
||||
+ if (xhci->quirks & XHCI_FORCE_MSI) {
|
||||
ret = xhci_setup_msi(xhci);
|
||||
+ } else {
|
||||
+ ret = xhci_setup_msix(xhci);
|
||||
+ if (ret)
|
||||
+ /* fall back to msi*/
|
||||
+ ret = xhci_setup_msi(xhci);
|
||||
+ }
|
||||
|
||||
if (!ret)
|
||||
/* hcd->irq is 0, we have MSI */
|
||||
--- a/drivers/usb/host/xhci.h
|
||||
+++ b/drivers/usb/host/xhci.h
|
||||
@@ -1680,6 +1680,7 @@ struct xhci_hcd {
|
||||
/* support xHCI 0.96 spec USB2 software LPM */
|
||||
unsigned sw_lpm_support:1;
|
||||
/* support xHCI 1.0 spec USB2 hardware LPM */
|
||||
+#define XHCI_FORCE_MSI (1 << 24)
|
||||
unsigned hw_lpm_support:1;
|
||||
/* cached usb2 extened protocol capabilites */
|
||||
u32 *ext_caps;
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
--- a/drivers/usb/dwc2/platform.c
|
||||
+++ b/drivers/usb/dwc2/platform.c
|
||||
@@ -279,6 +279,37 @@ static int dwc2_get_dr_mode(struct dwc2_
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static const struct dwc2_core_params params_amcc_dwc_otg = {
|
||||
+ .otg_cap = DWC2_CAP_PARAM_HNP_SRP_CAPABLE,
|
||||
+ .otg_ver = -1,
|
||||
+ .dma_enable = -1,
|
||||
+ .dma_desc_enable = -1,
|
||||
+ .speed = -1,
|
||||
+ .enable_dynamic_fifo = -1,
|
||||
+ .en_multiple_tx_fifo = -1,
|
||||
+ .host_rx_fifo_size = -1,
|
||||
+ .host_nperio_tx_fifo_size = -1,
|
||||
+ .host_perio_tx_fifo_size = -1,
|
||||
+ .max_transfer_size = -1,
|
||||
+ .max_packet_count = -1,
|
||||
+ .host_channels = -1,
|
||||
+ .phy_type = -1,
|
||||
+ .phy_utmi_width = -1,
|
||||
+ .phy_ulpi_ddr = -1,
|
||||
+ .phy_ulpi_ext_vbus = -1,
|
||||
+ .i2c_enable = -1,
|
||||
+ .ulpi_fs_ls = -1,
|
||||
+ .host_support_fs_ls_low_power = -1,
|
||||
+ .host_ls_low_power_phy_clk = -1,
|
||||
+ .ts_dline = -1,
|
||||
+ .reload_ctl = -1,
|
||||
+ .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
|
||||
+ GAHBCFG_HBSTLEN_SHIFT,
|
||||
+ .uframe_sched = -1,
|
||||
+ .external_id_pin_ctl = -1,
|
||||
+ .hibernation = -1,
|
||||
+};
|
||||
+
|
||||
static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(hsotg->dev);
|
||||
@@ -511,6 +542,7 @@ static void dwc2_driver_shutdown(struct
|
||||
}
|
||||
|
||||
static const struct of_device_id dwc2_of_match_table[] = {
|
||||
+ { .compatible = "amcc,usb-otg-405ex", .data = ¶ms_amcc_dwc_otg },
|
||||
{ .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 },
|
||||
{ .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 },
|
||||
{ .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 },
|
||||
File diff suppressed because it is too large
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Reference in a new issue