KumiSystems/openwrtv4
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

lantiq: Fix PCIe bus when PCI is also enabled.

Browse source 
The PCIe bus seems to require a hack/workaround when PCI is enabled as
well. Unfortunately this is guarded by an CONFIG_IFX_PCI ifdef, which is
only defined in lantiq's BSP code. The config symbol for the upstream
lantiq PCI driver is CONFIG_PCI_LANTIQ.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 45717
This commit is contained in:
John Crispin 2015-05-23 15:25:51 +00:00
parent 47eca7a1ca
commit 390924e662
1 changed files with 10 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch
View file

@ -4115,11 +4115,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+{
+ u32 tbus_number = bus_number;
+
+#ifdef CONFIG_IFX_PCI
+#ifdef CONFIG_PCI_LANTIQ
+ if (pcibios_host_nr() > 1) {
+ tbus_number -= pcibios_1st_host_bus_nr();
+ }
+#endif /* CONFIG_IFX_PCI */
+#endif /* CONFIG_PCI_LANTIQ */
+ return tbus_number;
+}
+
@ -4141,14 +4141,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ }
+
+ if (read) { /* Read hack */
+ #ifdef CONFIG_IFX_PCI
+ #ifdef CONFIG_PCI_LANTIQ
+ if (pcibios_host_nr() > 1) {
+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
+ }
+ #endif /* CONFIG_IFX_PCI */
+ #endif /* CONFIG_PCI_LANTIQ */
+ }
+ else { /* Write hack */
+ #ifdef CONFIG_IFX_PCI
+ #ifdef CONFIG_PCI_LANTIQ
+ if (pcibios_host_nr() > 1) {
+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
+ }
@ -5457,11 +5457,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+{
+ u32 tbus_number = bus_number;
+
+#ifdef CONFIG_IFX_PCI
+#ifdef CONFIG_PCI_LANTIQ
+ if (pcibios_host_nr() > 1) {
+ tbus_number -= pcibios_1st_host_bus_nr();
+ }
+#endif /* CONFIG_IFX_PCI */
+#endif /* CONFIG_PCI_LANTIQ */
+ return tbus_number;
+}
+
@ -5483,14 +5483,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ }
+
+ if (read) { /* Read hack */
+ #ifdef CONFIG_IFX_PCI
+ #ifdef CONFIG_PCI_LANTIQ
+ if (pcibios_host_nr() > 1) {
+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
+ }
+ #endif /* CONFIG_IFX_PCI */
+ #endif /* CONFIG_PCI_LANTIQ */
+ }
+ else { /* Write hack */
+ #ifdef CONFIG_IFX_PCI
+ #ifdef CONFIG_PCI_LANTIQ
+ if (pcibios_host_nr() > 1) {
+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
+ }