bcm53xx: add temporary BCM53573 ILP clock driver
It wasn't accepted upstream as there was a discusson on Northstar vs. BCM53573. Once we get a new ARM arch Kconfig entry it should be possible to upstream it. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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From 65acc8219d271d29b918ae4d6fe4d520203f25ae Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Fri, 29 Jul 2016 14:48:19 +0200
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Subject: [PATCH V3] clk: bcm: Add driver for Northstar ILP clock
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This clock is present on cheaper Northstar devices like BCM53573 or
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BCM47189 using Corex-A7. ILP is a part of PMU (Power Management Unit)
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and so it should be defined as one of its subnodes (subdevices). For
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more details see Documentation entry.
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Unfortunately there isn't a set of registers related to ILP clock only.
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We use registers 0x66c, 0x674 and 0x6dc and between them there are e.g.
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"retention*" and "control_ext" regs. This is why this driver maps all
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0x1000 B of space.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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V2: Rebase on top of clk-next
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Use ALP as parent clock
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Improve comments
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Switch from ioremap_nocache to ioremap
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Check of_clk_add_provide result for error
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V3: Drop #include <linux/moduleh>
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Make ILP DT entry part of PMU
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Describe ILP as subdevice of PMU in Documentation
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---
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.../devicetree/bindings/clock/brcm,ns-ilp.txt | 40 ++++++
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drivers/clk/bcm/Makefile | 1 +
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drivers/clk/bcm/clk-ns-ilp.c | 146 +++++++++++++++++++++
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3 files changed, 187 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/brcm,ns-ilp.txt
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create mode 100644 drivers/clk/bcm/clk-ns-ilp.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/brcm,ns-ilp.txt
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@@ -0,0 +1,40 @@
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+Broadcom Northstar ILP clock
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+============================
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+
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+This binding uses the common clock binding:
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+ Documentation/devicetree/bindings/clock/clock-bindings.txt
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+
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+This binding is used for ILP clock (sometimes referred as "slow clock")
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+on Broadcom Northstar devices using Corex-A7 CPU.
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+
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+This clock is part of PMU (Power Management Unit), a Broadcom's device
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+handing power-related aspects. Please note PMU contains more subdevices,
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+ILP is only one of them.
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+
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+ILP's rate has to be calculated on runtime and it depends on ALP clock
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+which has to be referenced.
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+
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+Required properties:
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+- compatible: "brcm,ns-ilp"
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+- reg: iomem address range of PMU (Power Management Unit)
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+- reg-names: "pmu", the only needed & supported reg right now
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+- clocks: has to reference an ALP clock
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+- #clock-cells: should be <0>
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+
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+Example:
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+
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+pmu@18012000 {
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+ compatible = "simple-bus";
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+ ranges = <0x00000000 0x18012000 0x00001000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ ilp: ilp@0 {
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+ compatible = "brcm,ns-ilp";
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+ reg = <0 0x1000>;
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+ reg-names = "pmu";
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+ clocks = <&alp>;
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+ #clock-cells = <0>;
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+ clock-output-names = "ilp";
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+ };
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+};
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--- a/drivers/clk/bcm/Makefile
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+++ b/drivers/clk/bcm/Makefile
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@@ -8,3 +8,4 @@ obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns
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obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
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obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o
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obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
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+obj-$(CONFIG_ARCH_BCM_5301X) += clk-ns-ilp.o
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--- /dev/null
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+++ b/drivers/clk/bcm/clk-ns-ilp.c
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@@ -0,0 +1,146 @@
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+/*
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+ * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/slab.h>
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+
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+#define PMU_XTAL_FREQ_RATIO 0x66c
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+#define XTAL_ALP_PER_4ILP 0x00001fff
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+#define XTAL_CTL_EN 0x80000000
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+#define PMU_SLOW_CLK_PERIOD 0x6dc
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+
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+struct ns_ilp {
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+ struct clk *clk;
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+ struct clk_hw hw;
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+ void __iomem *pmu;
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+};
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+
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+static int ns_ilp_enable(struct clk_hw *hw)
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+{
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+ struct ns_ilp *ilp = container_of(hw, struct ns_ilp, hw);
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+
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+ writel(0x10199, ilp->pmu + PMU_SLOW_CLK_PERIOD);
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+ writel(0x10000, ilp->pmu + 0x674);
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+
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+ return 0;
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+}
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+
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+static unsigned long ns_ilp_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct ns_ilp *ilp = container_of(hw, struct ns_ilp, hw);
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+ void __iomem *pmu = ilp->pmu;
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+ u32 last_val, cur_val;
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+ u32 sum = 0, num = 0, loop_num = 0;
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+ u32 avg;
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+
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+ /* Enable measurement */
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+ writel(XTAL_CTL_EN, pmu + PMU_XTAL_FREQ_RATIO);
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+
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+ /* Read initial value */
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+ last_val = readl(pmu + PMU_XTAL_FREQ_RATIO) & XTAL_ALP_PER_4ILP;
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+
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+ /*
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+ * At minimum we should loop for a bit to let hardware do the
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+ * measurement. This isn't very accurate however, so for a better
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+ * precision lets try getting 20 different values for and use average.
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+ */
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+ while (num < 20) {
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+ cur_val = readl(pmu + PMU_XTAL_FREQ_RATIO) & XTAL_ALP_PER_4ILP;
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+
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+ if (cur_val != last_val) {
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+ /* Got different value, use it */
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+ sum += cur_val;
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+ num++;
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+ loop_num = 0;
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+ last_val = cur_val;
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+ } else if (++loop_num > 5000) {
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+ /* Same value over and over, give up */
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+ sum += cur_val;
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+ num++;
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+ break;
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+ }
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+ }
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+
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+ /* Disable measurement to save power */
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+ writel(0x0, pmu + PMU_XTAL_FREQ_RATIO);
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+
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+ avg = sum / num;
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+
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+ return parent_rate * 4 / avg;
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+}
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+
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+static const struct clk_ops ns_ilp_clk_ops = {
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+ .enable = ns_ilp_enable,
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+ .recalc_rate = ns_ilp_recalc_rate,
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+};
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+
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+static void ns_ilp_init(struct device_node *np)
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+{
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+ struct ns_ilp *ilp;
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+ struct resource res;
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+ struct clk_init_data init = { 0 };
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+ const char *parent_name;
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+ int index;
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+ int err;
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+
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+ ilp = kzalloc(sizeof(*ilp), GFP_KERNEL);
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+ if (!ilp)
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+ return;
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+
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+ parent_name = of_clk_get_parent_name(np, 0);
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+ if (!parent_name) {
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+ err = -ENOENT;
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+ goto err_free_ilp;
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+ }
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+
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+ /* TODO: This looks generic, try making it OF helper. */
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+ index = of_property_match_string(np, "reg-names", "pmu");
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+ if (index < 0) {
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+ err = index;
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+ goto err_free_ilp;
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+ }
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+ err = of_address_to_resource(np, index, &res);
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+ if (err)
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+ goto err_free_ilp;
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+ ilp->pmu = ioremap(res.start, resource_size(&res));
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+ if (IS_ERR(ilp->pmu)) {
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+ err = PTR_ERR(ilp->pmu);
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+ goto err_free_ilp;
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+ }
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+
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+ init.name = np->name;
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+ init.ops = &ns_ilp_clk_ops;
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+ init.parent_names = &parent_name;
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+ init.num_parents = 1;
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+
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+ ilp->hw.init = &init;
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+ ilp->clk = clk_register(NULL, &ilp->hw);
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+ if (WARN_ON(IS_ERR(ilp->clk)))
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+ goto err_unmap_pmu;
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+
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+ err = of_clk_add_provider(np, of_clk_src_simple_get, ilp->clk);
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+ if (err)
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+ goto err_clk_unregister;
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+
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+ return;
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+
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+err_clk_unregister:
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+ clk_unregister(ilp->clk);
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+err_unmap_pmu:
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+ iounmap(ilp->pmu);
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+err_free_ilp:
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+ kfree(ilp);
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+ pr_err("Failed to init ILP clock: %d\n", err);
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+}
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+CLK_OF_DECLARE(ns_ilp_clk, "brcm,ns-ilp", ns_ilp_init);
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