ar71xx: fix MDIO access on ar7242 (based on a patch by Jess Zhu)
SVN-Revision: 26777
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2336d4b438
commit
36aecb08b8
2 changed files with 63 additions and 25 deletions
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@ -105,29 +105,6 @@ struct platform_device ar71xx_mdio_device = {
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},
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};
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void __init ar71xx_add_device_mdio(u32 phy_mask)
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{
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7240:
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ar71xx_mdio_data.is_ar7240 = 1;
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break;
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case AR71XX_SOC_AR7241:
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ar71xx_mdio_data.is_ar7240 = 1;
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ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE;
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ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1;
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break;
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case AR71XX_SOC_AR7242:
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ar71xx_mdio_data.is_ar7240 = 1;
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break;
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default:
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break;
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}
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ar71xx_mdio_data.phy_mask = phy_mask;
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platform_device_register(&ar71xx_mdio_device);
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}
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static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
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{
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void __iomem *base;
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@ -157,6 +134,31 @@ static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
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iounmap(base);
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}
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void __init ar71xx_add_device_mdio(u32 phy_mask)
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{
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7240:
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ar71xx_mdio_data.is_ar7240 = 1;
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break;
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case AR71XX_SOC_AR7241:
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ar71xx_mdio_data.is_ar7240 = 1;
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ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE;
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ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1;
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break;
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case AR71XX_SOC_AR7242:
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
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AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
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AR71XX_ETH0_PLL_SHIFT);
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break;
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default:
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break;
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}
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ar71xx_mdio_data.phy_mask = phy_mask;
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platform_device_register(&ar71xx_mdio_device);
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}
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struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
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struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
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@ -219,6 +221,14 @@ static void ar724x_set_pll_ge1(int speed)
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/* TODO */
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}
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static void ar7242_set_pll_ge0(int speed)
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{
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u32 val = ar71xx_get_eth_pll(0, speed);
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ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR7242_PLL_REG_ETH0_INT_CLOCK,
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val, AR71XX_ETH0_PLL_SHIFT);
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}
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static void ar91xx_set_pll_ge0(int speed)
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{
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u32 val = ar71xx_get_eth_pll(0, speed);
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@ -339,6 +349,10 @@ struct platform_device ar71xx_eth1_device = {
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#define AR724X_PLL_VAL_100 0x00001099
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#define AR724X_PLL_VAL_10 0x00991099
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#define AR7242_PLL_VAL_1000 0x1c000000
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#define AR7242_PLL_VAL_100 0x00000101
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#define AR7242_PLL_VAL_10 0x00001616
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#define AR91XX_PLL_VAL_1000 0x1a000000
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#define AR91XX_PLL_VAL_100 0x13000a44
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#define AR91XX_PLL_VAL_10 0x00441099
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@ -370,12 +384,17 @@ static void __init ar71xx_init_eth_pll_data(unsigned int id)
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case AR71XX_SOC_AR7240:
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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pll_10 = AR724X_PLL_VAL_10;
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pll_100 = AR724X_PLL_VAL_100;
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pll_1000 = AR724X_PLL_VAL_1000;
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break;
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case AR71XX_SOC_AR7242:
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pll_10 = AR7242_PLL_VAL_10;
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pll_100 = AR7242_PLL_VAL_100;
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pll_1000 = AR7242_PLL_VAL_1000;
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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pll_10 = AR91XX_PLL_VAL_10;
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@ -465,8 +484,25 @@ void __init ar71xx_add_device_eth(unsigned int id)
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pdata->has_gbit = 1;
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break;
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
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ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
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pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
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: ar724x_ddr_flush_ge0;
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pdata->set_pll = id ? ar724x_set_pll_ge1
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: ar7242_set_pll_ge0;
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pdata->has_gbit = 1;
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pdata->is_ar724x = 1;
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if (!pdata->fifo_cfg1)
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pdata->fifo_cfg1 = 0x0010ffff;
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if (!pdata->fifo_cfg2)
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pdata->fifo_cfg2 = 0x015500aa;
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if (!pdata->fifo_cfg3)
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pdata->fifo_cfg3 = 0x01f00140;
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break;
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case AR71XX_SOC_AR7241:
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ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
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ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
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/* fall through */
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@ -166,6 +166,8 @@ extern enum ar71xx_soc_type ar71xx_soc;
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#define AR724X_DDR_DIV_SHIFT 22
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#define AR724X_DDR_DIV_MASK 0x3
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#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
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#define AR91XX_PLL_REG_CPU_CONFIG 0x00
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#define AR91XX_PLL_REG_ETH_CONFIG 0x04
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#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
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