flush more register writings
SVN-Revision: 16415
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73eee8e138
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1 changed files with 12 additions and 0 deletions
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@ -113,6 +113,9 @@ static void ar71xx_gpio_irq_unmask(unsigned int irq)
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irq -= AR71XX_GPIO_IRQ_BASE;
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irq -= AR71XX_GPIO_IRQ_BASE;
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ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
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ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
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ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
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ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
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/* flush write */
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ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
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}
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}
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static void ar71xx_gpio_irq_mask(unsigned int irq)
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static void ar71xx_gpio_irq_mask(unsigned int irq)
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@ -120,6 +123,9 @@ static void ar71xx_gpio_irq_mask(unsigned int irq)
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irq -= AR71XX_GPIO_IRQ_BASE;
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irq -= AR71XX_GPIO_IRQ_BASE;
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ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
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ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
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ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
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ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
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/* flush write */
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ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
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}
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}
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#if 0
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#if 0
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@ -211,6 +217,9 @@ static void ar71xx_misc_irq_unmask(unsigned int irq)
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irq -= AR71XX_MISC_IRQ_BASE;
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irq -= AR71XX_MISC_IRQ_BASE;
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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}
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static void ar71xx_misc_irq_mask(unsigned int irq)
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static void ar71xx_misc_irq_mask(unsigned int irq)
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@ -218,6 +227,9 @@ static void ar71xx_misc_irq_mask(unsigned int irq)
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irq -= AR71XX_MISC_IRQ_BASE;
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irq -= AR71XX_MISC_IRQ_BASE;
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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}
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struct irq_chip ar71xx_misc_irq_chip = {
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struct irq_chip ar71xx_misc_irq_chip = {
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