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regroup interrupt controller register definitions in hardware.h

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SVN-Revision: 32485
This commit is contained in:
Florian Fainelli 2012-06-23 11:03:29 +00:00
parent 7ed9369cb3
commit 2c47bbc199
3 changed files with 10 additions and 8 deletions
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6
target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/include/mach/entry-macro.S
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@ -11,8 +11,8 @@
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \tmp, #0x40
ldr \irqstat, [\base, \tmp]
mov \tmp, #MCS814X_IRQ_STS0 @ load tmp with STS0 register offset
ldr \irqstat, [\base, \tmp] @ load value at base + tmp
tst \irqstat, \irqstat @ test if no active IRQ's
beq 1002f @ if no active irqs return with status 0
mov \irqnr, #0 @ start from irq zero
@ -23,7 +23,7 @@
moveq \tmp, \tmp, lsl #1 @ shift mask one to left
beq 1001b @ if zero then loop again
mov \irqstat, \tmp @ save the return mask
mov \tmp, #0x00 @ ICR offset
mov \tmp, #MCS814X_IRQ_STS0 @ load tmp with ICR offset
str \irqstat, [\base, \tmp] @ clear irq with selected mask
1002:
.endm

6
target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/include/mach/hardware.h
View file

@ -14,6 +14,12 @@
#define MCS814X_IO_START 0x40000000
#define MCS814X_IO_SIZE 0x00100000
/* IRQ controller register offset */
#define MCS814X_IRQ_ICR 0x00
#define MCS814X_IRQ_ISR 0x04
#define MCS814X_IRQ_MASK 0x20
#define MCS814X_IRQ_STS0 0x40
#define _PHYS_CONFADDR 0x40000000
#define _VIRT_CONFADDR MCS814X_IO_BASE

6
target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/irq.c
View file

@ -14,11 +14,7 @@
#include <asm/exception.h>
#include <asm/mach/irq.h>
#define MCS814X_IRQ_ICR 0x00
#define MCS814X_IRQ_ISR 0x04
#define MCS814X_IRQ_MASK 0x20
#define MCS814X_IRQ_STS0 0x40
#include <mach/hardware.h>
void __iomem *mcs814x_intc_base;