ar71xx: only enable the rx engine after the link is up, fixes a race condition that got rx stuck when the interface is brought up during lots of inbound traffic (thx, matteo)
SVN-Revision: 27035
This commit is contained in:
parent
0ebc93831f
commit
2b5402d128
1 changed files with 68 additions and 67 deletions
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@ -344,6 +344,71 @@ static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
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return "?";
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}
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static void ag71xx_dma_reset(struct ag71xx *ag)
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{
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u32 val;
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int i;
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ag71xx_dump_dma_regs(ag);
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/* stop RX and TX */
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ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
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ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
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/*
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* give the hardware some time to really stop all rx/tx activity
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* clearing the descriptors too early causes random memory corruption
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*/
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mdelay(1);
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/* clear descriptor addresses */
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ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
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ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
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/* clear pending RX/TX interrupts */
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for (i = 0; i < 256; i++) {
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
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}
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/* clear pending errors */
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
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val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
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if (val)
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printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
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ag->dev->name, val);
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val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
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/* mask out reserved bits */
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val &= ~0xff000000;
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if (val)
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printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
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ag->dev->name, val);
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ag71xx_dump_dma_regs(ag);
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}
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static void ag71xx_hw_start(struct ag71xx *ag)
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{
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/* start RX engine */
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ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
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/* enable interrupts */
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ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
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}
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static void ag71xx_hw_stop(struct ag71xx *ag)
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{
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/* disable all interrupts */
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ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
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ag71xx_dma_reset(ag);
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}
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void ag71xx_link_adjust(struct ag71xx *ag)
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{
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
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@ -353,6 +418,7 @@ void ag71xx_link_adjust(struct ag71xx *ag)
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u32 mii_speed;
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if (!ag->link) {
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ag71xx_hw_stop(ag);
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netif_carrier_off(ag->dev);
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if (netif_msg_link(ag))
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printk(KERN_INFO "%s: link down\n", ag->dev->name);
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@ -405,6 +471,8 @@ void ag71xx_link_adjust(struct ag71xx *ag)
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
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ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
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ag71xx_hw_start(ag);
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netif_carrier_on(ag->dev);
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if (netif_msg_link(ag))
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printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
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@ -444,54 +512,6 @@ static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
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ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
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}
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static void ag71xx_dma_reset(struct ag71xx *ag)
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{
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u32 val;
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int i;
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ag71xx_dump_dma_regs(ag);
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/* stop RX and TX */
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ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
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ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
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/*
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* give the hardware some time to really stop all rx/tx activity
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* clearing the descriptors too early causes random memory corruption
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*/
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mdelay(1);
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/* clear descriptor addresses */
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ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
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ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
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/* clear pending RX/TX interrupts */
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for (i = 0; i < 256; i++) {
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
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}
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/* clear pending errors */
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
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val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
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if (val)
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printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
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ag->dev->name, val);
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val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
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/* mask out reserved bits */
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val &= ~0xff000000;
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if (val)
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printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
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ag->dev->name, val);
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ag71xx_dump_dma_regs(ag);
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}
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#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
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MAC_CFG1_SRX | MAC_CFG1_STX)
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@ -550,23 +570,6 @@ static void ag71xx_hw_init(struct ag71xx *ag)
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ag71xx_dma_reset(ag);
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}
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static void ag71xx_hw_start(struct ag71xx *ag)
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{
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/* start RX engine */
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ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
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/* enable interrupts */
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ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
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}
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static void ag71xx_hw_stop(struct ag71xx *ag)
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{
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/* disable all interrupts */
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ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
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ag71xx_dma_reset(ag);
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}
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static int ag71xx_open(struct net_device *dev)
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{
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struct ag71xx *ag = netdev_priv(dev);
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@ -586,8 +589,6 @@ static int ag71xx_open(struct net_device *dev)
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ag71xx_hw_set_macaddr(ag, dev->dev_addr);
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ag71xx_hw_start(ag);
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netif_start_queue(dev);
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return 0;
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