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ar71xx: Add QCA953X version2 SoC support

Browse source 
http://patchwork.ozlabs.org/patch/435234/

Signed-off-by: 郭传鈜 <gch981213@gmail.com>
Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 44527
This commit is contained in:
John Crispin 2015-02-24 12:01:00 +00:00
parent 9358a8a798
commit 1c5a2826e3
2 changed files with 40 additions and 22 deletions
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38
target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
View file

@ -22,7 +22,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
--- a/arch/mips/ath79/Kconfig --- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig
@@ -1158,6 +1158,10 @@ config SOC_AR934X @@ -1168,6 +1168,10 @@ config SOC_AR934X
select PCI_AR724X if PCI select PCI_AR724X if PCI
def_bool n def_bool n
@ -33,7 +33,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
config SOC_QCA955X config SOC_QCA955X
select HW_HAS_PCI select HW_HAS_PCI
select PCI_AR724X if PCI select PCI_AR724X if PCI
@@ -1200,7 +1204,7 @@ config ATH79_DEV_USB @@ -1210,7 +1214,7 @@ config ATH79_DEV_USB
def_bool n def_bool n
config ATH79_DEV_WMAC config ATH79_DEV_WMAC
@ -233,11 +233,12 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
else else
--- a/arch/mips/ath79/early_printk.c --- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c +++ b/arch/mips/ath79/early_printk.c
@@ -114,6 +114,7 @@ static void prom_putchar_init(void) @@ -114,6 +114,8 @@ static void prom_putchar_init(void)
case REV_ID_MAJOR_AR9341: case REV_ID_MAJOR_AR9341:
case REV_ID_MAJOR_AR9342: case REV_ID_MAJOR_AR9342:
case REV_ID_MAJOR_AR9344: case REV_ID_MAJOR_AR9344:
+ case REV_ID_MAJOR_QCA9533: + case REV_ID_MAJOR_QCA9533:
+ case REV_ID_MAJOR_QCA9533_V2:
case REV_ID_MAJOR_QCA9556: case REV_ID_MAJOR_QCA9556:
case REV_ID_MAJOR_QCA9558: case REV_ID_MAJOR_QCA9558:
_prom_putchar = prom_putchar_ar71xx; _prom_putchar = prom_putchar_ar71xx;
@ -283,10 +284,22 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
ath79_ip3_handler = ath79_default_ip3_handler; ath79_ip3_handler = ath79_default_ip3_handler;
--- a/arch/mips/ath79/setup.c --- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c
@@ -151,6 +151,12 @@ static void __init ath79_detect_sys_type @@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
u32 major;
u32 minor;
u32 rev = 0;
+ u32 ver = 1;
id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
major = id & REV_ID_MAJOR_MASK;
@@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
rev = id & AR934X_REV_ID_REVISION_MASK; rev = id & AR934X_REV_ID_REVISION_MASK;
break; break;
+ case REV_ID_MAJOR_QCA9533_V2:
+ ver = 2;
+ /* drop through */
+
+ case REV_ID_MAJOR_QCA9533: + case REV_ID_MAJOR_QCA9533:
+ ath79_soc = ATH79_SOC_QCA9533; + ath79_soc = ATH79_SOC_QCA9533;
+ chip = "9533"; + chip = "9533";
@ -296,15 +309,19 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
case REV_ID_MAJOR_QCA9556: case REV_ID_MAJOR_QCA9556:
ath79_soc = ATH79_SOC_QCA9556; ath79_soc = ATH79_SOC_QCA9556;
chip = "9556"; chip = "9556";
@@ -169,7 +175,7 @@ static void __init ath79_detect_sys_type @@ -169,9 +180,9 @@ static void __init ath79_detect_sys_type
ath79_soc_rev = rev; ath79_soc_rev = rev;
- if (soc_is_qca955x()) - if (soc_is_qca955x())
- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
- chip, rev);
+ if (soc_is_qca953x() || soc_is_qca955x()) + if (soc_is_qca953x() || soc_is_qca955x())
sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
chip, rev); + chip, ver, rev);
else else
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
pr_info("SoC: %s\n", ath79_sys_type);
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -105,6 +105,9 @@ @@ -105,6 +105,9 @@
@ -381,15 +398,16 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
@@ -565,6 +611,7 @@ @@ -565,6 +611,8 @@
#define REV_ID_MAJOR_AR9341 0x0120 #define REV_ID_MAJOR_AR9341 0x0120
#define REV_ID_MAJOR_AR9342 0x1120 #define REV_ID_MAJOR_AR9342 0x1120
#define REV_ID_MAJOR_AR9344 0x2120 #define REV_ID_MAJOR_AR9344 0x2120
+#define REV_ID_MAJOR_QCA9533 0x0140 +#define REV_ID_MAJOR_QCA9533 0x0140
+#define REV_ID_MAJOR_QCA9533_V2 0x0160
#define REV_ID_MAJOR_QCA9556 0x0130 #define REV_ID_MAJOR_QCA9556 0x0130
#define REV_ID_MAJOR_QCA9558 0x1130 #define REV_ID_MAJOR_QCA9558 0x1130
@@ -587,6 +634,8 @@ @@ -587,6 +635,8 @@
#define AR934X_REV_ID_REVISION_MASK 0xf #define AR934X_REV_ID_REVISION_MASK 0xf
@ -398,7 +416,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_REV_ID_REVISION_MASK 0xf #define QCA955X_REV_ID_REVISION_MASK 0xf
/* /*
@@ -640,6 +689,7 @@ @@ -640,6 +690,7 @@
#define AR913X_GPIO_COUNT 22 #define AR913X_GPIO_COUNT 22
#define AR933X_GPIO_COUNT 30 #define AR933X_GPIO_COUNT 30
#define AR934X_GPIO_COUNT 23 #define AR934X_GPIO_COUNT 23

24
target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
View file

@ -276,8 +276,8 @@
--- a/arch/mips/ath79/early_printk.c --- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c +++ b/arch/mips/ath79/early_printk.c
@@ -117,6 +117,8 @@ static void prom_putchar_init(void) @@ -118,6 +118,8 @@ static void prom_putchar_init(void)
case REV_ID_MAJOR_QCA9533: case REV_ID_MAJOR_QCA9533_V2:
case REV_ID_MAJOR_QCA9556: case REV_ID_MAJOR_QCA9556:
case REV_ID_MAJOR_QCA9558: case REV_ID_MAJOR_QCA9558:
+ case REV_ID_MAJOR_TP9343: + case REV_ID_MAJOR_TP9343:
@ -445,7 +445,7 @@
} }
--- a/arch/mips/ath79/Kconfig --- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig
@@ -1167,6 +1167,12 @@ config SOC_QCA955X @@ -1177,6 +1177,12 @@ config SOC_QCA955X
select PCI_AR724X if PCI select PCI_AR724X if PCI
def_bool n def_bool n
@ -458,7 +458,7 @@
config ATH79_DEV_M25P80 config ATH79_DEV_M25P80
select ATH79_DEV_SPI select ATH79_DEV_SPI
def_bool n def_bool n
@@ -1204,7 +1210,7 @@ config ATH79_DEV_USB @@ -1214,7 +1220,7 @@ config ATH79_DEV_USB
def_bool n def_bool n
config ATH79_DEV_WMAC config ATH79_DEV_WMAC
@ -519,7 +519,7 @@
return -ENODEV; return -ENODEV;
--- a/arch/mips/ath79/setup.c --- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c
@@ -170,15 +170,30 @@ static void __init ath79_detect_sys_type @@ -175,15 +175,30 @@ static void __init ath79_detect_sys_type
rev = id & QCA955X_REV_ID_REVISION_MASK; rev = id & QCA955X_REV_ID_REVISION_MASK;
break; break;
@ -543,8 +543,8 @@
- if (soc_is_qca953x() || soc_is_qca955x()) - if (soc_is_qca953x() || soc_is_qca955x())
+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561()) + if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
chip, rev); chip, ver, rev);
+ else if (soc_is_tp9343()) + else if (soc_is_tp9343())
+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", + sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
+ chip, rev); + chip, rev);
@ -686,8 +686,8 @@
#define REV_ID_MAJOR_MASK 0xfff0 #define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0 #define REV_ID_MAJOR_AR71XX 0x00a0
#define REV_ID_MAJOR_AR913X 0x00b0 #define REV_ID_MAJOR_AR913X 0x00b0
@@ -614,6 +712,8 @@ @@ -615,6 +713,8 @@
#define REV_ID_MAJOR_QCA9533 0x0140 #define REV_ID_MAJOR_QCA9533_V2 0x0160
#define REV_ID_MAJOR_QCA9556 0x0130 #define REV_ID_MAJOR_QCA9556 0x0130
#define REV_ID_MAJOR_QCA9558 0x1130 #define REV_ID_MAJOR_QCA9558 0x1130
+#define REV_ID_MAJOR_TP9343 0x0150 +#define REV_ID_MAJOR_TP9343 0x0150
@ -695,7 +695,7 @@
#define AR71XX_REV_ID_MINOR_MASK 0x3 #define AR71XX_REV_ID_MINOR_MASK 0x3
#define AR71XX_REV_ID_MINOR_AR7130 0x0 #define AR71XX_REV_ID_MINOR_AR7130 0x0
@@ -638,6 +738,8 @@ @@ -639,6 +739,8 @@
#define QCA955X_REV_ID_REVISION_MASK 0xf #define QCA955X_REV_ID_REVISION_MASK 0xf
@ -704,7 +704,7 @@
/* /*
* SPI block * SPI block
*/ */
@@ -683,6 +785,19 @@ @@ -684,6 +786,19 @@
#define AR934X_GPIO_REG_OUT_FUNC5 0x40 #define AR934X_GPIO_REG_OUT_FUNC5 0x40
#define AR934X_GPIO_REG_FUNC 0x6c #define AR934X_GPIO_REG_FUNC 0x6c
@ -724,7 +724,7 @@
#define AR71XX_GPIO_COUNT 16 #define AR71XX_GPIO_COUNT 16
#define AR7240_GPIO_COUNT 18 #define AR7240_GPIO_COUNT 18
#define AR7241_GPIO_COUNT 20 #define AR7241_GPIO_COUNT 20
@@ -691,6 +806,7 @@ @@ -692,6 +807,7 @@
#define AR934X_GPIO_COUNT 23 #define AR934X_GPIO_COUNT 23
#define QCA953X_GPIO_COUNT 24 #define QCA953X_GPIO_COUNT 24
#define QCA955X_GPIO_COUNT 24 #define QCA955X_GPIO_COUNT 24