linux/generic: add MIB counters and port status to ADM6996 switch
This patch adds port status information and MIB counters to the ADM6996 switch driver. The driver supports also the older ADM6996L-variant, but I'm not able to test this patch on that chip. According to the datasheet the same registers exist there as well, so I think it should work, but any feedback is appreciated. Signed-off-by: Matti Laakso <malaakso at elisanet.fi> SVN-Revision: 40542
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@ -6,6 +6,7 @@
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* Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org>
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* Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org>
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* VLAN support Copyright (c) 2010, 2011 Peter Lebbing <peter@digitalbrains.com>
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* VLAN support Copyright (c) 2010, 2011 Peter Lebbing <peter@digitalbrains.com>
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* Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>
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* Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>
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* Copyright (c) 2014 Matti Laakso <malaakso@elisanet.fi>
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License v2 as published by the
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* under the terms of the GNU General Public License v2 as published by the
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@ -54,6 +55,11 @@ static const char * const adm6996_model_name[] =
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"ADM6996L"
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"ADM6996L"
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};
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};
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struct adm6996_mib_desc {
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unsigned int offset;
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const char *name;
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};
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struct adm6996_priv {
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struct adm6996_priv {
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struct switch_dev dev;
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struct switch_dev dev;
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void *priv;
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void *priv;
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@ -78,6 +84,9 @@ struct adm6996_priv {
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u16 vlan_id[ADM_NUM_VLANS];
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u16 vlan_id[ADM_NUM_VLANS];
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u8 vlan_table[ADM_NUM_VLANS]; /* bitmap, 1 = port is member */
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u8 vlan_table[ADM_NUM_VLANS]; /* bitmap, 1 = port is member */
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u8 vlan_tagged[ADM_NUM_VLANS]; /* bitmap, 1 = tagged member */
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u8 vlan_tagged[ADM_NUM_VLANS]; /* bitmap, 1 = tagged member */
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struct mutex mib_lock;
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char buf[2048];
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struct mutex reg_mutex;
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struct mutex reg_mutex;
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@ -89,6 +98,21 @@ struct adm6996_priv {
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#define to_adm(_dev) container_of(_dev, struct adm6996_priv, dev)
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#define to_adm(_dev) container_of(_dev, struct adm6996_priv, dev)
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#define phy_to_adm(_phy) ((struct adm6996_priv *) (_phy)->priv)
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#define phy_to_adm(_phy) ((struct adm6996_priv *) (_phy)->priv)
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#define MIB_DESC(_o, _n) \
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{ \
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.offset = (_o), \
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.name = (_n), \
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}
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static const struct adm6996_mib_desc adm6996_mibs[] = {
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MIB_DESC(ADM_CL0, "RxPacket"),
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MIB_DESC(ADM_CL6, "RxByte"),
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MIB_DESC(ADM_CL12, "TxPacket"),
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MIB_DESC(ADM_CL18, "TxByte"),
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MIB_DESC(ADM_CL24, "Collision"),
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MIB_DESC(ADM_CL30, "Error"),
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};
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static inline u16
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static inline u16
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r16(struct adm6996_priv *priv, enum admreg reg)
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r16(struct adm6996_priv *priv, enum admreg reg)
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{
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{
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@ -773,6 +797,99 @@ adm6996_reset_switch(struct switch_dev *dev)
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return 0;
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return 0;
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}
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}
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static int
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adm6996_get_port_link(struct switch_dev *dev, int port,
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struct switch_port_link *link)
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{
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struct adm6996_priv *priv = to_adm(dev);
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u16 reg = 0;
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u32 speed;
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if (port >= ADM_NUM_PORTS)
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return -EINVAL;
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switch (port) {
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case 0:
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reg = r16(priv, ADM_PS0);
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break;
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case 1:
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reg = r16(priv, ADM_PS0);
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reg = reg >> 8;
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break;
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case 2:
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reg = r16(priv, ADM_PS1);
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break;
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case 3:
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reg = r16(priv, ADM_PS1);
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reg = reg >> 8;
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break;
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case 4:
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reg = r16(priv, ADM_PS1);
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reg = reg >> 12;
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break;
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case 5:
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reg = r16(priv, ADM_PS2);
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/* Bits 0, 1, 3 and 4. */
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reg = (reg & 3) | ((reg & 24) >> 1);
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break;
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default:
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return -EINVAL;
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}
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link->link = reg & ADM_PS_LS;
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if (!link->link)
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return 0;
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link->aneg = true;
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link->duplex = reg & ADM_PS_DS;
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link->tx_flow = reg & ADM_PS_FCS;
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link->rx_flow = reg & ADM_PS_FCS;
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if (reg & ADM_PS_SS)
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link->speed = SWITCH_PORT_SPEED_100;
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else
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link->speed = SWITCH_PORT_SPEED_10;
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return 0;
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}
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static int
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adm6996_sw_get_port_mib(struct switch_dev *dev,
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const struct switch_attr *attr,
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struct switch_val *val)
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{
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struct adm6996_priv *priv = to_adm(dev);
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int port;
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char *buf = priv->buf;
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int i, len = 0;
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u32 reg = 0;
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port = val->port_vlan;
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if (port >= ADM_NUM_PORTS)
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return -EINVAL;
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mutex_lock(&priv->mib_lock);
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len += snprintf(buf + len, sizeof(priv->buf) - len,
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"Port %d MIB counters\n",
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port);
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for (i = 0; i < ARRAY_SIZE(adm6996_mibs); i++) {
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reg = r16(priv, adm6996_mibs[i].offset + ADM_OFFSET_PORT(port));
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reg += r16(priv, adm6996_mibs[i].offset + ADM_OFFSET_PORT(port) + 1) << 16;
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len += snprintf(buf + len, sizeof(priv->buf) - len,
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"%-12s: %lu\n",
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adm6996_mibs[i].name,
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reg);
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}
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mutex_unlock(&priv->mib_lock);
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val->value.s = buf;
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val->len = len;
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return 0;
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}
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static struct switch_attr adm6996_globals[] = {
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static struct switch_attr adm6996_globals[] = {
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{
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{
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.type = SWITCH_TYPE_INT,
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.type = SWITCH_TYPE_INT,
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@ -802,6 +919,13 @@ static struct switch_attr adm6996_globals[] = {
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};
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};
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static struct switch_attr adm6996_port[] = {
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static struct switch_attr adm6996_port[] = {
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{
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.type = SWITCH_TYPE_STRING,
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.name = "mib",
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.description = "Get port's MIB counters",
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.set = NULL,
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.get = adm6996_sw_get_port_mib,
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},
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};
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};
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static struct switch_attr adm6996_vlan[] = {
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static struct switch_attr adm6996_vlan[] = {
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@ -833,6 +957,7 @@ static const struct switch_dev_ops adm6996_ops = {
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.set_vlan_ports = adm6996_set_ports,
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.set_vlan_ports = adm6996_set_ports,
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.apply_config = adm6996_hw_apply,
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.apply_config = adm6996_hw_apply,
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.reset_switch = adm6996_reset_switch,
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.reset_switch = adm6996_reset_switch,
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.get_port_link = adm6996_get_port_link,
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};
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};
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static int adm6996_switch_init(struct adm6996_priv *priv, const char *alias, struct net_device *netdev)
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static int adm6996_switch_init(struct adm6996_priv *priv, const char *alias, struct net_device *netdev)
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@ -899,6 +1024,7 @@ static int adm6996_config_init(struct phy_device *pdev)
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return -ENOMEM;
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return -ENOMEM;
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mutex_init(&priv->reg_mutex);
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mutex_init(&priv->reg_mutex);
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mutex_init(&priv->mib_lock);
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priv->priv = pdev;
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priv->priv = pdev;
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priv->read = adm6996_read_mii_reg;
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priv->read = adm6996_read_mii_reg;
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priv->write = adm6996_write_mii_reg;
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priv->write = adm6996_write_mii_reg;
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@ -50,6 +50,16 @@ enum admreg {
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ADM_COUNTER_BASE = 0xa0,
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ADM_COUNTER_BASE = 0xa0,
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ADM_SIG0 = ADM_COUNTER_BASE + 0,
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ADM_SIG0 = ADM_COUNTER_BASE + 0,
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ADM_SIG1 = ADM_COUNTER_BASE + 1,
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ADM_SIG1 = ADM_COUNTER_BASE + 1,
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ADM_PS0 = ADM_COUNTER_BASE + 2,
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ADM_PS1 = ADM_COUNTER_BASE + 3,
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ADM_PS2 = ADM_COUNTER_BASE + 4,
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ADM_CL0 = ADM_COUNTER_BASE + 8, /* RxPacket */
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ADM_CL6 = ADM_COUNTER_BASE + 0x1a, /* RxByte */
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ADM_CL12 = ADM_COUNTER_BASE + 0x2c, /* TxPacket */
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ADM_CL18 = ADM_COUNTER_BASE + 0x3e, /* TxByte */
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ADM_CL24 = ADM_COUNTER_BASE + 0x50, /* Coll */
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ADM_CL30 = ADM_COUNTER_BASE + 0x62, /* Err */
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#define ADM_OFFSET_PORT(n) ((n * 4) - (n / 4) * 2 - (n / 5) * 2)
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ADM_PHY_BASE = 0x200,
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ADM_PHY_BASE = 0x200,
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#define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n))
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#define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n))
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};
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};
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@ -159,6 +169,14 @@ static const u8 adm_portcfg[] = {
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((ports & 0x04) << 2) | ((ports & 0x08) << 3) | \
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((ports & 0x04) << 2) | ((ports & 0x08) << 3) | \
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((ports & 0x10) << 3) | ((ports & 0x20) << 3))
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((ports & 0x10) << 3) | ((ports & 0x20) << 3))
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/* Port status register */
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enum {
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ADM_PS_LS = (1 << 0), /* Link status */
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ADM_PS_SS = (1 << 1), /* Speed status */
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ADM_PS_DS = (1 << 2), /* Duplex status */
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ADM_PS_FCS = (1 << 3) /* Flow control status */
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};
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/*
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/*
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* Split the register address in phy id and register
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* Split the register address in phy id and register
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* it will get combined again by the mdio bus op
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* it will get combined again by the mdio bus op
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