kernel: update spi-nor in 4.9 to spi-nor tree version (next branch)
These are patches queued for 4.11. It adds support for even more hw and removes some annoying WARN_ONCE. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
This commit is contained in:
Rafał Miłecki
parent
6d5419d96a
commit
174ce4c56d
12 changed files with 784 additions and 28 deletions
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From 61cba34bd6c1bddfc38f94cc3f80bdfefcc3393b Mon Sep 17 00:00:00 2001
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From: Ricardo Ribalda <ricardo.ribalda@gmail.com>
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Date: Fri, 2 Dec 2016 12:31:44 +0100
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Subject: [PATCH] mtd: spi-nor: Add support for S3AN spi-nor devices
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Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep
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their configuration data and (optionally) some user data.
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The protocol of this flash follows most of the spi-nor standard. With
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the following differences:
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- Page size might not be a power of two.
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- The address calculation (default addressing mode).
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- The spi nor commands used.
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Protocol is described on Xilinx User Guide UG333
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Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
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Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
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Cc: Brian Norris <computersforpeace@gmail.com>
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Cc: Marek Vasut <marek.vasut@gmail.com>
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Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
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Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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---
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drivers/mtd/spi-nor/spi-nor.c | 154 ++++++++++++++++++++++++++++++++++++++++--
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include/linux/mtd/spi-nor.h | 12 ++++
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2 files changed, 161 insertions(+), 5 deletions(-)
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -75,6 +75,12 @@ struct flash_info {
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* bit. Must be used with
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* SPI_NOR_HAS_LOCK.
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*/
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+#define SPI_S3AN BIT(10) /*
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+ * Xilinx Spartan 3AN In-System Flash
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+ * (MFR cannot be used for probing
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+ * because it has the same value as
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+ * ATMEL flashes)
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+ */
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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@@ -217,6 +223,21 @@ static inline int set_4byte(struct spi_n
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return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
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}
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}
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+
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+static int s3an_sr_ready(struct spi_nor *nor)
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+{
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+ int ret;
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+ u8 val;
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+
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+ ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
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+ if (ret < 0) {
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+ dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
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+ return ret;
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+ }
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+
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+ return !!(val & XSR_RDY);
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+}
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+
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static inline int spi_nor_sr_ready(struct spi_nor *nor)
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{
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int sr = read_sr(nor);
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@@ -238,7 +259,11 @@ static inline int spi_nor_fsr_ready(stru
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static int spi_nor_ready(struct spi_nor *nor)
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{
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int sr, fsr;
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- sr = spi_nor_sr_ready(nor);
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+
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+ if (nor->flags & SNOR_F_READY_XSR_RDY)
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+ sr = s3an_sr_ready(nor);
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+ else
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+ sr = spi_nor_sr_ready(nor);
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if (sr < 0)
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return sr;
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fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
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@@ -320,6 +345,24 @@ static void spi_nor_unlock_and_unprep(st
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}
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/*
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+ * This code converts an address to the Default Address Mode, that has non
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+ * power of two page sizes. We must support this mode because it is the default
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+ * mode supported by Xilinx tools, it can access the whole flash area and
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+ * changing over to the Power-of-two mode is irreversible and corrupts the
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+ * original data.
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+ * Addr can safely be unsigned int, the biggest S3AN device is smaller than
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+ * 4 MiB.
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+ */
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+static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
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+{
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+ unsigned int offset = addr;
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+
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+ offset %= nor->page_size;
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+
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+ return ((addr - offset) << 1) | offset;
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+}
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+
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+/*
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* Initiate the erasure of a single sector
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*/
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static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
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@@ -327,6 +370,9 @@ static int spi_nor_erase_sector(struct s
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u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
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int i;
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+ if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
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+ addr = spi_nor_s3an_addr_convert(nor, addr);
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+
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if (nor->erase)
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return nor->erase(nor, addr);
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@@ -368,7 +414,7 @@ static int spi_nor_erase(struct mtd_info
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return ret;
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/* whole-chip erase? */
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- if (len == mtd->size) {
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+ if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
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unsigned long timeout;
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write_enable(nor);
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@@ -782,6 +828,19 @@ static int spi_nor_is_locked(struct mtd_
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.addr_width = (_addr_width), \
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.flags = (_flags),
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+#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
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+ .id = { \
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+ ((_jedec_id) >> 16) & 0xff, \
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+ ((_jedec_id) >> 8) & 0xff, \
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+ (_jedec_id) & 0xff \
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+ }, \
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+ .id_len = 3, \
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+ .sector_size = (8*_page_size), \
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+ .n_sectors = (_n_sectors), \
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+ .page_size = _page_size, \
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+ .addr_width = 3, \
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+ .flags = SPI_NOR_NO_FR | SPI_S3AN,
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+
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/* NOTE: double check command sets and memory organization when you add
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* more nor chips. This current list focusses on newer chips, which
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* have been converging on command sets which including JEDEC ID.
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@@ -1014,6 +1073,13 @@ static const struct flash_info spi_nor_i
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{ "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
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{ "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
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{ "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
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+
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+ /* Xilinx S3AN Internal Flash */
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+ { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
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+ { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
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+ { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
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+ { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
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+ { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
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{ },
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};
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@@ -1054,7 +1120,12 @@ static int spi_nor_read(struct mtd_info
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return ret;
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while (len) {
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- ret = nor->read(nor, from, len, buf);
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+ loff_t addr = from;
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+
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+ if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
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+ addr = spi_nor_s3an_addr_convert(nor, addr);
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+
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+ ret = nor->read(nor, addr, len, buf);
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if (ret == 0) {
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/* We shouldn't see 0-length reads */
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ret = -EIO;
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@@ -1175,8 +1246,23 @@ static int spi_nor_write(struct mtd_info
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for (i = 0; i < len; ) {
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ssize_t written;
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+ loff_t addr = to + i;
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- page_offset = (to + i) & (nor->page_size - 1);
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+ /*
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+ * If page_size is a power of two, the offset can be quickly
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+ * calculated with an AND operation. On the other cases we
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+ * need to do a modulus operation (more expensive).
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+ * Power of two numbers have only one bit set and we can use
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+ * the instruction hweight32 to detect if we need to do a
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+ * modulus (do_div()) or not.
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+ */
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+ if (hweight32(nor->page_size) == 1) {
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+ page_offset = addr & (nor->page_size - 1);
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+ } else {
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+ uint64_t aux = addr;
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+
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+ page_offset = do_div(aux, nor->page_size);
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+ }
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WARN_ONCE(page_offset,
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"Writing at offset %zu into a NOR page. Writing partial pages may decrease reliability and increase wear of NOR flash.",
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page_offset);
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@@ -1184,8 +1270,11 @@ static int spi_nor_write(struct mtd_info
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page_remain = min_t(size_t,
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nor->page_size - page_offset, len - i);
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+ if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
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+ addr = spi_nor_s3an_addr_convert(nor, addr);
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+
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write_enable(nor);
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- ret = nor->write(nor, to + i, page_remain, buf + i);
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+ ret = nor->write(nor, addr, page_remain, buf + i);
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if (ret < 0)
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goto write_err;
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written = ret;
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@@ -1312,6 +1401,47 @@ static int spi_nor_check(struct spi_nor
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return 0;
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}
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+static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
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+{
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+ int ret;
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+ u8 val;
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+
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+ ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
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+ if (ret < 0) {
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+ dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
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+ return ret;
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+ }
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+
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+ nor->erase_opcode = SPINOR_OP_XSE;
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+ nor->program_opcode = SPINOR_OP_XPP;
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+ nor->read_opcode = SPINOR_OP_READ;
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+ nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
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+
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+ /*
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+ * This flashes have a page size of 264 or 528 bytes (known as
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+ * Default addressing mode). It can be changed to a more standard
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+ * Power of two mode where the page size is 256/512. This comes
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+ * with a price: there is 3% less of space, the data is corrupted
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+ * and the page size cannot be changed back to default addressing
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+ * mode.
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+ *
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+ * The current addressing mode can be read from the XRDSR register
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+ * and should not be changed, because is a destructive operation.
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+ */
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+ if (val & XSR_PAGESIZE) {
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+ /* Flash in Power of 2 mode */
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+ nor->page_size = (nor->page_size == 264) ? 256 : 512;
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+ nor->mtd.writebufsize = nor->page_size;
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+ nor->mtd.size = 8 * nor->page_size * info->n_sectors;
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+ nor->mtd.erasesize = 8 * nor->page_size;
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+ } else {
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+ /* Flash in Default addressing mode */
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+ nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
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+ }
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+
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+ return 0;
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+}
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+
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int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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{
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const struct flash_info *info = NULL;
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@@ -1360,6 +1490,14 @@ int spi_nor_scan(struct spi_nor *nor, co
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mutex_init(&nor->lock);
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/*
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+ * Make sure the XSR_RDY flag is set before calling
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+ * spi_nor_wait_till_ready(). Xilinx S3AN share MFR
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+ * with Atmel spi-nor
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+ */
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+ if (info->flags & SPI_S3AN)
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+ nor->flags |= SNOR_F_READY_XSR_RDY;
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+
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+ /*
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* Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
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* with the software protection bits set
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*/
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@@ -1517,6 +1655,12 @@ int spi_nor_scan(struct spi_nor *nor, co
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nor->read_dummy = spi_nor_read_dummy_cycles(nor);
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+ if (info->flags & SPI_S3AN) {
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+ ret = s3an_nor_scan(info, nor);
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+ if (ret)
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+ return ret;
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+ }
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+
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dev_info(dev, "%s (%lld Kbytes)\n", info->name,
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(long long)mtd->size >> 10);
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -68,6 +68,15 @@
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#define SPINOR_OP_WRDI 0x04 /* Write disable */
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#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
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+/* Used for S3AN flashes only */
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+#define SPINOR_OP_XSE 0x50 /* Sector erase */
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+#define SPINOR_OP_XPP 0x82 /* Page program */
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+#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
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+
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+#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
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+#define XSR_RDY BIT(7) /* Ready */
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+
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+
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/* Used for Macronix and Winbond flashes. */
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#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
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#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
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@@ -119,6 +128,9 @@ enum spi_nor_ops {
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enum spi_nor_option_flags {
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SNOR_F_USE_FSR = BIT(0),
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SNOR_F_HAS_SR_TB = BIT(1),
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+ SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
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+ SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
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+ SNOR_F_READY_XSR_RDY = BIT(4),
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};
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/**
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@ -0,0 +1,28 @@
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From 1e99d0d51ec97bf48edd277658004ce030543d98 Mon Sep 17 00:00:00 2001
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From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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Date: Tue, 6 Dec 2016 17:01:41 +0100
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Subject: [PATCH] mtd: spi-nor: improve macronix_quad_enable()
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The patch checks whether the Quad Enable bit is already set in the Status
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Register. If so, the function exits immediately with a successful return
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code.
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Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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Reviewed-by: Jagan Teki <jagan@openedev.com>
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Acked-by: Marek Vasut <marek.vasut@gmail.com>
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---
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drivers/mtd/spi-nor/spi-nor.c | 3 +++
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1 file changed, 3 insertions(+)
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -1305,6 +1305,9 @@ static int macronix_quad_enable(struct s
|
||||||
|
val = read_sr(nor);
|
||||||
|
if (val < 0)
|
||||||
|
return val;
|
||||||
|
+ if (val & SR_QUAD_EN_MX)
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
write_enable(nor);
|
||||||
|
|
||||||
|
write_sr(nor, val | SR_QUAD_EN_MX);
|
||||||
|
|
@ -0,0 +1,33 @@
|
||||||
|
From dc176595bf184e89bf28fdf91cbc1d050dfe63b3 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
|
||||||
|
Date: Tue, 6 Dec 2016 18:14:24 +0100
|
||||||
|
Subject: [PATCH] mtd: spi-nor: remove WARN_ONCE() message in spi_nor_write()
|
||||||
|
|
||||||
|
This patch removes the WARN_ONCE() test in spi_nor_write().
|
||||||
|
This macro triggers the display of a warning message almost every time we
|
||||||
|
use a UBI file-system because a write operation is performed at offset 64,
|
||||||
|
which is in the middle of the SPI NOR memory page. This is a valid
|
||||||
|
operation for ubifs.
|
||||||
|
|
||||||
|
Hence this warning is pretty annoying and useless so we just remove it.
|
||||||
|
|
||||||
|
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
|
||||||
|
Suggested-by: Richard Weinberger <richard@nod.at>
|
||||||
|
Suggested-by: Andras Szemzo <szemzo.andras@gmail.com>
|
||||||
|
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
|
||||||
|
---
|
||||||
|
drivers/mtd/spi-nor/spi-nor.c | 3 ---
|
||||||
|
1 file changed, 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||||
|
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||||
|
@@ -1263,9 +1263,6 @@ static int spi_nor_write(struct mtd_info
|
||||||
|
|
||||||
|
page_offset = do_div(aux, nor->page_size);
|
||||||
|
}
|
||||||
|
- WARN_ONCE(page_offset,
|
||||||
|
- "Writing at offset %zu into a NOR page. Writing partial pages may decrease reliability and increase wear of NOR flash.",
|
||||||
|
- page_offset);
|
||||||
|
/* the size of data remaining on the first page */
|
||||||
|
page_remain = min_t(size_t,
|
||||||
|
nor->page_size - page_offset, len - i);
|
||||||
|
|
@ -0,0 +1,187 @@
|
||||||
|
From 05aba5763dcf35eddc58aaf99c9f16d19730e0a8 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
|
||||||
|
Date: Thu, 27 Oct 2016 11:55:39 +0200
|
||||||
|
Subject: [PATCH] mtd: spi-nor: rename SPINOR_OP_* macros of the 4-byte address
|
||||||
|
op codes
|
||||||
|
|
||||||
|
This patch renames the SPINOR_OP_* macros of the 4-byte address
|
||||||
|
instruction set so the new names all share a common pattern: the 4-byte
|
||||||
|
address name is built from the 3-byte address name appending the "_4B"
|
||||||
|
suffix.
|
||||||
|
|
||||||
|
The patch also introduces new op codes to support other SPI protocols such
|
||||||
|
as SPI 1-4-4 and SPI 1-2-2.
|
||||||
|
|
||||||
|
This is a transitional patch and will help a later patch of spi-nor.c
|
||||||
|
to automate the translation from the 3-byte address op codes into their
|
||||||
|
4-byte address version.
|
||||||
|
|
||||||
|
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
|
||||||
|
Acked-by: Mark Brown <broonie@kernel.org>
|
||||||
|
Acked-by: Marek Vasut <marek.vasut@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/mtd/devices/serial_flash_cmds.h | 7 -------
|
||||||
|
drivers/mtd/devices/st_spi_fsm.c | 28 ++++++++++++++--------------
|
||||||
|
drivers/mtd/spi-nor/spi-nor.c | 8 ++++----
|
||||||
|
drivers/spi/spi-bcm-qspi.c | 6 +++---
|
||||||
|
include/linux/mtd/spi-nor.h | 22 ++++++++++++++++------
|
||||||
|
5 files changed, 37 insertions(+), 34 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/mtd/devices/serial_flash_cmds.h
|
||||||
|
+++ b/drivers/mtd/devices/serial_flash_cmds.h
|
||||||
|
@@ -18,19 +18,12 @@
|
||||||
|
#define SPINOR_OP_RDVCR 0x85
|
||||||
|
|
||||||
|
/* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
|
||||||
|
-#define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */
|
||||||
|
-#define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */
|
||||||
|
-
|
||||||
|
#define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */
|
||||||
|
#define SPINOR_OP_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
|
||||||
|
#define SPINOR_OP_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
|
||||||
|
#define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
|
||||||
|
#define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
|
||||||
|
|
||||||
|
-/* READ commands with 32-bit addressing */
|
||||||
|
-#define SPINOR_OP_READ4_1_2_2 0xbc
|
||||||
|
-#define SPINOR_OP_READ4_1_4_4 0xec
|
||||||
|
-
|
||||||
|
/* Configuration flags */
|
||||||
|
#define FLASH_FLAG_SINGLE 0x000000ff
|
||||||
|
#define FLASH_FLAG_READ_WRITE 0x00000001
|
||||||
|
--- a/drivers/mtd/devices/st_spi_fsm.c
|
||||||
|
+++ b/drivers/mtd/devices/st_spi_fsm.c
|
||||||
|
@@ -507,13 +507,13 @@ static struct seq_rw_config n25q_read3_c
|
||||||
|
* - 'FAST' variants configured for 8 dummy cycles (see note above.)
|
||||||
|
*/
|
||||||
|
static struct seq_rw_config n25q_read4_configs[] = {
|
||||||
|
- {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8},
|
||||||
|
- {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
|
||||||
|
- {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8},
|
||||||
|
- {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
|
||||||
|
- {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
|
||||||
|
- {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
|
||||||
|
- {0x00, 0, 0, 0, 0, 0x00, 0, 0},
|
||||||
|
+ {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 0, 8},
|
||||||
|
+ {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
|
||||||
|
+ {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 0, 8},
|
||||||
|
+ {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
|
||||||
|
+ {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
|
||||||
|
+ {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
|
||||||
|
+ {0x00, 0, 0, 0, 0, 0x00, 0, 0},
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
@@ -553,13 +553,13 @@ static int stfsm_mx25_en_32bit_addr_seq(
|
||||||
|
* entering a state that is incompatible with the SPIBoot Controller.
|
||||||
|
*/
|
||||||
|
static struct seq_rw_config stfsm_s25fl_read4_configs[] = {
|
||||||
|
- {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4},
|
||||||
|
- {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
|
||||||
|
- {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0},
|
||||||
|
- {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
|
||||||
|
- {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
|
||||||
|
- {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
|
||||||
|
- {0x00, 0, 0, 0, 0, 0x00, 0, 0},
|
||||||
|
+ {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 2, 4},
|
||||||
|
+ {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
|
||||||
|
+ {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 4, 0},
|
||||||
|
+ {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
|
||||||
|
+ {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
|
||||||
|
+ {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
|
||||||
|
+ {0x00, 0, 0, 0, 0, 0x00, 0, 0},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct seq_rw_config stfsm_s25fl_write4_configs[] = {
|
||||||
|
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||||
|
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||||
|
@@ -1625,16 +1625,16 @@ int spi_nor_scan(struct spi_nor *nor, co
|
||||||
|
/* Dedicated 4-byte command set */
|
||||||
|
switch (nor->flash_read) {
|
||||||
|
case SPI_NOR_QUAD:
|
||||||
|
- nor->read_opcode = SPINOR_OP_READ4_1_1_4;
|
||||||
|
+ nor->read_opcode = SPINOR_OP_READ_1_1_4_4B;
|
||||||
|
break;
|
||||||
|
case SPI_NOR_DUAL:
|
||||||
|
- nor->read_opcode = SPINOR_OP_READ4_1_1_2;
|
||||||
|
+ nor->read_opcode = SPINOR_OP_READ_1_1_2_4B;
|
||||||
|
break;
|
||||||
|
case SPI_NOR_FAST:
|
||||||
|
- nor->read_opcode = SPINOR_OP_READ4_FAST;
|
||||||
|
+ nor->read_opcode = SPINOR_OP_READ_FAST_4B;
|
||||||
|
break;
|
||||||
|
case SPI_NOR_NORMAL:
|
||||||
|
- nor->read_opcode = SPINOR_OP_READ4;
|
||||||
|
+ nor->read_opcode = SPINOR_OP_READ_4B;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
nor->program_opcode = SPINOR_OP_PP_4B;
|
||||||
|
--- a/drivers/spi/spi-bcm-qspi.c
|
||||||
|
+++ b/drivers/spi/spi-bcm-qspi.c
|
||||||
|
@@ -371,7 +371,7 @@ static int bcm_qspi_bspi_set_flex_mode(s
|
||||||
|
/* default mode, does not need flex_cmd */
|
||||||
|
flex_mode = 0;
|
||||||
|
else
|
||||||
|
- command = SPINOR_OP_READ4_FAST;
|
||||||
|
+ command = SPINOR_OP_READ_FAST_4B;
|
||||||
|
break;
|
||||||
|
case SPI_NBITS_DUAL:
|
||||||
|
bpc = 0x00000001;
|
||||||
|
@@ -384,7 +384,7 @@ static int bcm_qspi_bspi_set_flex_mode(s
|
||||||
|
} else {
|
||||||
|
command = SPINOR_OP_READ_1_1_2;
|
||||||
|
if (spans_4byte)
|
||||||
|
- command = SPINOR_OP_READ4_1_1_2;
|
||||||
|
+ command = SPINOR_OP_READ_1_1_2_4B;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case SPI_NBITS_QUAD:
|
||||||
|
@@ -399,7 +399,7 @@ static int bcm_qspi_bspi_set_flex_mode(s
|
||||||
|
} else {
|
||||||
|
command = SPINOR_OP_READ_1_1_4;
|
||||||
|
if (spans_4byte)
|
||||||
|
- command = SPINOR_OP_READ4_1_1_4;
|
||||||
|
+ command = SPINOR_OP_READ_1_1_4_4B;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
--- a/include/linux/mtd/spi-nor.h
|
||||||
|
+++ b/include/linux/mtd/spi-nor.h
|
||||||
|
@@ -43,9 +43,13 @@
|
||||||
|
#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
|
||||||
|
#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
|
||||||
|
#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
|
||||||
|
-#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
|
||||||
|
-#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
|
||||||
|
+#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
|
||||||
|
+#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
|
||||||
|
+#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
|
||||||
|
+#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
|
||||||
|
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
|
||||||
|
+#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
|
||||||
|
+#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
|
||||||
|
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
|
||||||
|
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
|
||||||
|
#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
|
||||||
|
@@ -56,11 +60,17 @@
|
||||||
|
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
|
||||||
|
|
||||||
|
/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
|
||||||
|
-#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
|
||||||
|
-#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
|
||||||
|
-#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
|
||||||
|
-#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
|
||||||
|
+#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
|
||||||
|
+#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
|
||||||
|
+#define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
|
||||||
|
+#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
|
||||||
|
+#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
|
||||||
|
+#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
|
||||||
|
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
|
||||||
|
+#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
|
||||||
|
+#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
|
||||||
|
+#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
|
||||||
|
+#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
|
||||||
|
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
|
||||||
|
|
||||||
|
/* Used for SST flashes only. */
|
||||||
|
|
@ -0,0 +1,150 @@
|
||||||
|
From 3274ba26f27becfc4193ec6e229288140651f240 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
|
||||||
|
Date: Thu, 27 Oct 2016 12:03:57 +0200
|
||||||
|
Subject: [PATCH] mtd: spi-nor: add a stateless method to support memory size
|
||||||
|
above 128Mib
|
||||||
|
|
||||||
|
This patch provides an alternative mean to support memory above 16MiB
|
||||||
|
(128Mib) by replacing 3byte address op codes by their associated 4byte
|
||||||
|
address versions.
|
||||||
|
|
||||||
|
Using the dedicated 4byte address op codes doesn't change the internal
|
||||||
|
state of the SPI NOR memory as opposed to using other means such as
|
||||||
|
updating a Base Address Register (BAR) and sending command to enter/leave
|
||||||
|
the 4byte mode.
|
||||||
|
|
||||||
|
Hence when a CPU reset occurs, early bootloaders don't need to be aware
|
||||||
|
of BAR value or 4byte mode being enabled: they can still access the first
|
||||||
|
16MiB of the SPI NOR memory using the regular 3byte address op codes.
|
||||||
|
|
||||||
|
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
|
||||||
|
Tested-by: Vignesh R <vigneshr@ti.com>
|
||||||
|
Acked-by: Marek Vasut <marek.vasut@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/mtd/spi-nor/spi-nor.c | 101 +++++++++++++++++++++++++++++++++---------
|
||||||
|
1 file changed, 80 insertions(+), 21 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||||
|
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||||
|
@@ -81,6 +81,10 @@ struct flash_info {
|
||||||
|
* because it has the same value as
|
||||||
|
* ATMEL flashes)
|
||||||
|
*/
|
||||||
|
+#define SPI_NOR_4B_OPCODES BIT(11) /*
|
||||||
|
+ * Use dedicated 4byte address op codes
|
||||||
|
+ * to support memory size above 128Mib.
|
||||||
|
+ */
|
||||||
|
};
|
||||||
|
|
||||||
|
#define JEDEC_MFR(info) ((info)->id[0])
|
||||||
|
@@ -194,6 +198,78 @@ static inline struct spi_nor *mtd_to_spi
|
||||||
|
return mtd->priv;
|
||||||
|
}
|
||||||
|
|
||||||
|
+
|
||||||
|
+static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
|
||||||
|
+{
|
||||||
|
+ size_t i;
|
||||||
|
+
|
||||||
|
+ for (i = 0; i < size; i++)
|
||||||
|
+ if (table[i][0] == opcode)
|
||||||
|
+ return table[i][1];
|
||||||
|
+
|
||||||
|
+ /* No conversion found, keep input op code. */
|
||||||
|
+ return opcode;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline u8 spi_nor_convert_3to4_read(u8 opcode)
|
||||||
|
+{
|
||||||
|
+ static const u8 spi_nor_3to4_read[][2] = {
|
||||||
|
+ { SPINOR_OP_READ, SPINOR_OP_READ_4B },
|
||||||
|
+ { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
|
||||||
|
+ { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
|
||||||
|
+ { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
|
||||||
|
+ { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
|
||||||
|
+ { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
|
||||||
|
+ ARRAY_SIZE(spi_nor_3to4_read));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline u8 spi_nor_convert_3to4_program(u8 opcode)
|
||||||
|
+{
|
||||||
|
+ static const u8 spi_nor_3to4_program[][2] = {
|
||||||
|
+ { SPINOR_OP_PP, SPINOR_OP_PP_4B },
|
||||||
|
+ { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
|
||||||
|
+ { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
|
||||||
|
+ ARRAY_SIZE(spi_nor_3to4_program));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static inline u8 spi_nor_convert_3to4_erase(u8 opcode)
|
||||||
|
+{
|
||||||
|
+ static const u8 spi_nor_3to4_erase[][2] = {
|
||||||
|
+ { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
|
||||||
|
+ { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
|
||||||
|
+ { SPINOR_OP_SE, SPINOR_OP_SE_4B },
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
|
||||||
|
+ ARRAY_SIZE(spi_nor_3to4_erase));
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
|
||||||
|
+ const struct flash_info *info)
|
||||||
|
+{
|
||||||
|
+ /* Do some manufacturer fixups first */
|
||||||
|
+ switch (JEDEC_MFR(info)) {
|
||||||
|
+ case SNOR_MFR_SPANSION:
|
||||||
|
+ /* No small sector erase for 4-byte command set */
|
||||||
|
+ nor->erase_opcode = SPINOR_OP_SE;
|
||||||
|
+ nor->mtd.erasesize = info->sector_size;
|
||||||
|
+ break;
|
||||||
|
+
|
||||||
|
+ default:
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
|
||||||
|
+ nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
|
||||||
|
+ nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
/* Enable/disable 4-byte addressing mode. */
|
||||||
|
static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
|
||||||
|
int enable)
|
||||||
|
@@ -1621,27 +1697,10 @@ int spi_nor_scan(struct spi_nor *nor, co
|
||||||
|
else if (mtd->size > 0x1000000) {
|
||||||
|
/* enable 4-byte addressing if the device exceeds 16MiB */
|
||||||
|
nor->addr_width = 4;
|
||||||
|
- if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
|
||||||
|
- /* Dedicated 4-byte command set */
|
||||||
|
- switch (nor->flash_read) {
|
||||||
|
- case SPI_NOR_QUAD:
|
||||||
|
- nor->read_opcode = SPINOR_OP_READ_1_1_4_4B;
|
||||||
|
- break;
|
||||||
|
- case SPI_NOR_DUAL:
|
||||||
|
- nor->read_opcode = SPINOR_OP_READ_1_1_2_4B;
|
||||||
|
- break;
|
||||||
|
- case SPI_NOR_FAST:
|
||||||
|
- nor->read_opcode = SPINOR_OP_READ_FAST_4B;
|
||||||
|
- break;
|
||||||
|
- case SPI_NOR_NORMAL:
|
||||||
|
- nor->read_opcode = SPINOR_OP_READ_4B;
|
||||||
|
- break;
|
||||||
|
- }
|
||||||
|
- nor->program_opcode = SPINOR_OP_PP_4B;
|
||||||
|
- /* No small sector erase for 4-byte command set */
|
||||||
|
- nor->erase_opcode = SPINOR_OP_SE_4B;
|
||||||
|
- mtd->erasesize = info->sector_size;
|
||||||
|
- } else
|
||||||
|
+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
|
||||||
|
+ info->flags & SPI_NOR_4B_OPCODES)
|
||||||
|
+ spi_nor_set_4byte_opcodes(nor, info);
|
||||||
|
+ else
|
||||||
|
set_4byte(nor, info, 1);
|
||||||
|
} else {
|
||||||
|
nor->addr_width = 3;
|
||||||
|
|
@ -1,22 +1,26 @@
|
||||||
mtd: spi-nor: Add lock/unlock support for f25l32pa
|
From 252c36bb9c7b98b356f033d16ea83d20fb8b4d3e Mon Sep 17 00:00:00 2001
|
||||||
|
From: Victor Shyba <victor1984@riseup.net>
|
||||||
|
Date: Mon, 2 Jan 2017 22:34:30 -0300
|
||||||
|
Subject: [PATCH] mtd: spi-nor: Add lock/unlock support for f25l32pa
|
||||||
|
|
||||||
This chip has write protection enabled on power-up,
|
This chip has write protection enabled on power-up,
|
||||||
so this flag is necessary to support write operations.
|
so this flag is necessary to support write operations.
|
||||||
|
|
||||||
Signed-off-by: Victor Shyba <victor1984@riseup.net>
|
Signed-off-by: Victor Shyba <victor1984@riseup.net>
|
||||||
Acked-by: Marek Vasut <marek.vasut@gmail.com>
|
Acked-by: Marek Vasut <marek.vasut@gmail.com>
|
||||||
|
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
|
||||||
---
|
---
|
||||||
drivers/mtd/spi-nor/spi-nor.c | 2 +-
|
drivers/mtd/spi-nor/spi-nor.c | 2 +-
|
||||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||||
|
|
||||||
--- a/drivers/mtd/spi-nor/spi-nor.c
|
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||||
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||||
@@ -822,7 +822,7 @@ static const struct flash_info spi_nor_i
|
@@ -956,7 +956,7 @@ static const struct flash_info spi_nor_i
|
||||||
{ "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
|
{ "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
|
||||||
|
|
||||||
/* ESMT */
|
/* ESMT */
|
||||||
- { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
|
- { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
|
||||||
+ { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
|
+ { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
|
||||||
{ "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K) },
|
|
||||||
{ "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K) },
|
|
||||||
|
|
||||||
|
/* Everspin */
|
||||||
|
{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
||||||
|
|
@ -0,0 +1,35 @@
|
||||||
|
From 5f0e0758efddef5b06994a76d8c7f0b8a4c1daae Mon Sep 17 00:00:00 2001
|
||||||
|
From: Ricardo Ribalda <ricardo.ribalda@gmail.com>
|
||||||
|
Date: Wed, 18 Jan 2017 17:40:16 +0100
|
||||||
|
Subject: [PATCH] mtd: spi-nor: Fix S3AN addressing calculation
|
||||||
|
|
||||||
|
The page calculation under spi_nor_s3an_addr_convert() was wrong. On
|
||||||
|
Default Address Mode we need to perform a divide by page_size.
|
||||||
|
|
||||||
|
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
|
||||||
|
Acked-by: Marek Vasut <marek.vasut@gmail.com>
|
||||||
|
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
|
||||||
|
---
|
||||||
|
drivers/mtd/spi-nor/spi-nor.c | 9 ++++++---
|
||||||
|
1 file changed, 6 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||||
|
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||||
|
@@ -431,11 +431,14 @@ static void spi_nor_unlock_and_unprep(st
|
||||||
|
*/
|
||||||
|
static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
|
||||||
|
{
|
||||||
|
- unsigned int offset = addr;
|
||||||
|
+ unsigned int offset;
|
||||||
|
+ unsigned int page;
|
||||||
|
|
||||||
|
- offset %= nor->page_size;
|
||||||
|
+ offset = addr % nor->page_size;
|
||||||
|
+ page = addr / nor->page_size;
|
||||||
|
+ page <<= (nor->page_size > 512) ? 10 : 9;
|
||||||
|
|
||||||
|
- return ((addr - offset) << 1) | offset;
|
||||||
|
+ return page | offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
From 4c5747a390acc9d1da3b332507c8bae7a8ddfc48 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Kamal Dasu <kdasu.kdev@gmail.com>
|
||||||
|
Date: Fri, 20 Jan 2017 14:25:51 -0500
|
||||||
|
Subject: [PATCH] mtd: spi-nor: Add support for gd25q16
|
||||||
|
|
||||||
|
Add GigaDevice GD25Q16 (16M-bit) to supported list.
|
||||||
|
|
||||||
|
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
|
||||||
|
Acked-by: Marek Vasut <marek.vasut@gmail.com>
|
||||||
|
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
|
||||||
|
---
|
||||||
|
drivers/mtd/spi-nor/spi-nor.c | 5 +++++
|
||||||
|
1 file changed, 5 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||||
|
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||||
|
@@ -971,6 +971,11 @@ static const struct flash_info spi_nor_i
|
||||||
|
|
||||||
|
/* GigaDevice */
|
||||||
|
{
|
||||||
|
+ "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
|
||||||
|
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
||||||
|
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
||||||
|
+ },
|
||||||
|
+ {
|
||||||
|
"gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
|
||||||
|
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
||||||
|
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
||||||
|
|
@ -1,21 +0,0 @@
|
||||||
From: "L. D. Pinney" <ldpinney@gmail.com>
|
|
||||||
Date: Thu, 25 Aug 2016 13:07:56 -0500
|
|
||||||
Subject: [PATCH] mtd: spi-nor: add support for ESMT_f25l32qa and ESMT_f25l64qa
|
|
||||||
|
|
||||||
Add Support for the ESMT_F25L32QA and ESMT_F25L64QA
|
|
||||||
These are 4MB and 8MB SPI NOR Chips from Elite Semiconductor Memory Technology
|
|
||||||
|
|
||||||
Signed-off-by: L. D. Pinney <ldpinney@gmail.com>
|
|
||||||
---
|
|
||||||
|
|
||||||
--- a/drivers/mtd/spi-nor/spi-nor.c
|
|
||||||
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
|
||||||
@@ -822,6 +822,8 @@ static const struct flash_info spi_nor_i
|
|
||||||
|
|
||||||
/* ESMT */
|
|
||||||
{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
|
|
||||||
+ { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K) },
|
|
||||||
+ { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K) },
|
|
||||||
|
|
||||||
/* Everspin */
|
|
||||||
{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
|
|
||||||
|
|
@ -4,7 +4,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
||||||
|
|
||||||
--- a/drivers/mtd/spi-nor/spi-nor.c
|
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||||
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||||
@@ -1368,6 +1368,7 @@ int spi_nor_scan(struct spi_nor *nor, co
|
@@ -1588,6 +1588,7 @@ int spi_nor_scan(struct spi_nor *nor, co
|
||||||
|
|
||||||
if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
|
if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
|
||||||
JEDEC_MFR(info) == SNOR_MFR_INTEL ||
|
JEDEC_MFR(info) == SNOR_MFR_INTEL ||
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
--- a/drivers/mtd/spi-nor/spi-nor.c
|
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||||
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||||
@@ -816,6 +816,7 @@ static const struct flash_info spi_nor_i
|
@@ -954,6 +954,7 @@ static const struct flash_info spi_nor_i
|
||||||
{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
|
{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
|
||||||
{ "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
|
{ "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
|
||||||
{ "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
|
{ "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
--- a/drivers/mtd/spi-nor/spi-nor.c
|
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||||
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||||
@@ -873,6 +873,7 @@ static const struct flash_info spi_nor_i
|
@@ -1014,6 +1014,7 @@ static const struct flash_info spi_nor_i
|
||||||
{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
|
{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
|
||||||
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
|
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
|
||||||
{ "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
|
{ "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue