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uboot-sunxi: update to version 2017.07

Browse source 
The deleted patches are already integrated in the upstream U-Boot
version.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Hauke Mehrtens 2017-07-15 18:41:57 +02:00
parent ea9fab904b
commit 1422d4435b
19 changed files with 29 additions and 9077 deletions
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4
package/boot/uboot-sunxi/Makefile
View file

@ -9,9 +9,9 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2016.03
PKG_VERSION:=2017.07
PKG_HASH:=e49337262ecac44dbdeac140f2c6ebd1eba345e0162b0464172e7f05583ed7bb
PKG_HASH:=5374bfdc8acb9a38c025371b1ff20f45e7533668e84e685d0df5d9e7c0e4feff
PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>

3
package/boot/uboot-sunxi/patches/002-add-olimex-a13-som.patch
View file

@ -1,8 +1,7 @@
--- /dev/null
+++ b/configs/OLIMEX_A13_SOM_defconfig
@@ -0,0 +1,18 @@
@@ -0,0 +1,17 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y

22
package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch
View file

@ -1,16 +1,16 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -152,6 +152,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
@@ -254,6 +254,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31-mixtile-loftq.dtb \
+ sun6i-a31-pangolin.dtb \
sun6i-a31s-colorfly-e708-q1.dtb \
sun6i-a31s-cs908.dtb \
sun6i-a31s-primo81.dtb \
sun6i-a31s-sinovoip-bpi-m2.dtb
sun6i-a31s-inet-q972.dtb \
--- a/arch/arm/dts/sun6i-a31.dtsi
+++ b/arch/arm/dts/sun6i-a31.dtsi
@@ -643,6 +643,13 @@
@@ -679,6 +679,13 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
@ -358,17 +358,9 @@
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SUNXI_SPI=y
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -15,7 +15,6 @@ config SUNXI_GEN_SUN6I
separate ahb reset control registers, custom pmic bus, new style
watchdog, etc.
-
choice
prompt "Sunxi SoC Variant"
optional
@@ -533,6 +532,14 @@ config VIDEO_LCD_PANEL_I2C_SCL
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -746,6 +746,14 @@ config VIDEO_LCD_PANEL_I2C_SCL
Set the SCL pin for the LCD i2c interface. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.

1403
package/boot/uboot-sunxi/patches/010-dt-sync-files-with-kernel.patch
View file

File diff suppressed because it is too large Load diff

7211
package/boot/uboot-sunxi/patches/011-dt-sync-dts-files-with-kernel.patch
View file

File diff suppressed because it is too large Load diff

38
package/boot/uboot-sunxi/patches/012-sun6i-fix-clock_twi_onoff.patch
View file

@ -1,38 +0,0 @@
From 730d2f3a41c5ccae71b5008fffdf697d143be68c Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Wed, 16 Mar 2016 20:44:51 +0100
Subject: [PATCH] sunxi: Fix clock_twi_onoff for sun6i
The clock_sun6i.c implementation was not deasserting the reset for
the regular i2c controllers, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -100,13 +100,18 @@ int clock_twi_onoff(int port, int state)
return 0;
}
- /* set the apb clock gate for twi */
- if (state)
+ /* set the apb clock gate and reset for twi */
+ if (state) {
setbits_le32(&ccm->apb2_gate,
CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
- else
+ setbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_TWI_SHIFT + port));
+ } else {
+ clrbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_TWI_SHIFT + port));
clrbits_le32(&ccm->apb2_gate,
CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
+ }
return 0;
}

24
package/boot/uboot-sunxi/patches/013-enable-realtek-phy.patch
View file

@ -1,24 +0,0 @@
From 1eae8f66ff749409eb96e2f3f3387c56232d0b8a Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Wed, 16 Mar 2016 13:46:22 +0100
Subject: [PATCH] sunxi: Enable realtek phy support
Enable building of drivers/net/phy/realtek.c so that realtek phys
get properly initialized.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
include/configs/sunxi-common.h | 1 +
1 file changed, 1 insertion(+)
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -314,6 +314,7 @@ extern int soft_i2c_gpio_scl;
#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
+#define CONFIG_PHY_REALTEK
#endif
#ifdef CONFIG_USB_EHCI_HCD

127
package/boot/uboot-sunxi/patches/014-fix-gmac-init.patch
View file

@ -1,127 +0,0 @@
From fc8991c61c393ce6a9d3dfc97cb56dbbd9e8cbba Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 17 Mar 2016 13:53:03 +0100
Subject: [PATCH] sunxi: Fix gmac not working due to cpu_eth_init no longer
being called
cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-boot.
This commit fixes this by calling the clock, reset and pinmux setup
function from s_init() and enabling the phy power pin (if any) from
board_init().
The enabling of phy power cannot be done from s_init because it uses dm
and dm is not ready yet at this point.
Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Michael Haas <haas@computerlinguist.org>
---
arch/arm/cpu/armv7/sunxi/board.c | 28 +---------------------------
arch/arm/include/asm/arch-sunxi/sys_proto.h | 6 +++++-
board/sunxi/board.c | 5 +++++
board/sunxi/gmac.c | 14 +-------------
4 files changed, 12 insertions(+), 41 deletions(-)
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -136,6 +136,7 @@ void s_init(void)
timer_init();
gpio_init();
i2c_init_board();
+ eth_init_board();
}
#ifdef CONFIG_SPL_BUILD
@@ -243,30 +244,3 @@ void enable_caches(void)
dcache_enable();
}
#endif
-
-#ifdef CONFIG_CMD_NET
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
- __maybe_unused int rc;
-
-#ifdef CONFIG_MACPWR
- gpio_request(CONFIG_MACPWR, "macpwr");
- gpio_direction_output(CONFIG_MACPWR, 1);
- mdelay(200);
-#endif
-
-#ifdef CONFIG_SUNXI_GMAC
- rc = sunxi_gmac_initialize(bis);
- if (rc < 0) {
- printf("sunxi: failed to initialize gmac\n");
- return rc;
- }
-#endif
-
- return 0;
-}
-#endif
--- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -24,6 +24,10 @@ void sdelay(unsigned long);
void return_to_fel(uint32_t lr, uint32_t sp);
/* Board / SoC level designware gmac init */
-int sunxi_gmac_initialize(bd_t *bis);
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUNXI_GMAC
+void eth_init_board(void);
+#else
+static inline void eth_init_board(void) {}
+#endif
#endif
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -90,6 +90,11 @@ int board_init(void)
if (ret)
return ret;
+#ifdef CONFIG_MACPWR
+ gpio_request(CONFIG_MACPWR, "macpwr");
+ gpio_direction_output(CONFIG_MACPWR, 1);
+#endif
+
/* Uses dm gpio code so do this here and not in i2c_init_board() */
return soft_i2c_board_init();
}
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -6,7 +6,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
-int sunxi_gmac_initialize(bd_t *bis)
+void eth_init_board(void)
{
int pin;
struct sunxi_ccm_reg *const ccm =
@@ -79,16 +79,4 @@ int sunxi_gmac_initialize(bd_t *bis)
for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
#endif
-
-#ifdef CONFIG_DM_ETH
- return 0;
-#else
-# ifdef CONFIG_RGMII
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
-# elif defined CONFIG_GMII
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
-# else
- return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
-# endif
-#endif
}

78
package/boot/uboot-sunxi/patches/015-fix-2nd-usb-ctrler-on-sun47i.patch
View file

@ -1,78 +0,0 @@
From 948603d4d637a0e04a3214253b911cfc4ed11220 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Mon, 21 Mar 2016 14:44:35 +0100
Subject: [PATCH] sunxi: Fix 2nd usb controller on sun4i/sun7i no longer
working
The 2nd usb controller on sun4i/sun7i has its base address 0x8000
bytes from the 1st one, rather then 0x1000. Also the ahb clk gates
are interleaved with the ohci clk-gates introducing a hole between
the clks for usb1 and usb2.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
drivers/usb/host/ehci-sunxi.c | 13 +++++++++++--
drivers/usb/host/ohci-sunxi.c | 15 ++++++++++++---
2 files changed, 23 insertions(+), 5 deletions(-)
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -17,6 +17,14 @@
#include <dm.h>
#include "ehci.h"
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+#define BASE_DIST 0x8000
+#define AHB_CLK_DIST 2
+#else
+#define BASE_DIST 0x1000
+#define AHB_CLK_DIST 1
+#endif
+
struct ehci_sunxi_priv {
struct ehci_ctrl ehci;
int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
@@ -39,8 +47,9 @@ static int ehci_usb_probe(struct udevice
#ifdef CONFIG_MACH_SUN8I_H3
priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
#endif
- priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
- priv->ahb_gate_mask <<= priv->phy_index - 1;
+ priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+ priv->phy_index++; /* Non otg phys start at 1 */
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
#ifdef CONFIG_SUNXI_GEN_SUN6I
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -17,6 +17,14 @@
#include <usb.h>
#include "ohci.h"
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+#define BASE_DIST 0x8000
+#define AHB_CLK_DIST 2
+#else
+#define BASE_DIST 0x1000
+#define AHB_CLK_DIST 1
+#endif
+
struct ohci_sunxi_priv {
ohci_t ohci;
int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
@@ -42,9 +50,10 @@ static int ohci_usb_probe(struct udevice
priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
#endif
priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
- priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
- priv->ahb_gate_mask <<= priv->phy_index - 1;
- priv->usb_gate_mask <<= priv->phy_index - 1;
+ priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
+ priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
+ priv->usb_gate_mask <<= priv->phy_index;
+ priv->phy_index++; /* Non otg phys start at 1 */
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);

31
package/boot/uboot-sunxi/patches/016-spl-print-mmc-slot.patch
View file

@ -1,31 +0,0 @@
From 8f10b5c65611e6c15a113bf63289b6696452f90d Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Sun, 20 Mar 2016 14:17:10 +0100
Subject: [PATCH] spl: Print from which mmc slot spl is trying to boot
On some sunxi boards (and presumably also non sunxi boards) u-boot can
be either loaded from a sdcard in a micro-sd slot, or from eMMC.
Print which MMC spl tries to boot from, to help debugging.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
common/spl/spl.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -210,9 +210,9 @@ struct boot_device_name boot_name_table[
{ BOOT_DEVICE_RAM, "RAM" },
#endif
#ifdef CONFIG_SPL_MMC_SUPPORT
- { BOOT_DEVICE_MMC1, "MMC" },
- { BOOT_DEVICE_MMC2, "MMC" },
- { BOOT_DEVICE_MMC2_2, "MMC" },
+ { BOOT_DEVICE_MMC1, "MMC1" },
+ { BOOT_DEVICE_MMC2, "MMC2" },
+ { BOOT_DEVICE_MMC2_2, "MMC2_2" },
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
{ BOOT_DEVICE_NAND, "NAND" },

39
package/boot/uboot-sunxi/patches/017-usb-add-support-for-usb3-vbus-pin.patch
View file

@ -1,39 +0,0 @@
From 60fa63012fcdc3c4ec1497bf5e358f0a90b40949 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 18 Mar 2016 08:42:01 +0100
Subject: [PATCH] sunxi: Add support for USB vbus pin for USB3
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
arch/arm/cpu/armv7/sunxi/usb_phy.c | 1 +
board/sunxi/Kconfig | 6 ++++++
2 files changed, 7 insertions(+)
--- a/arch/arm/cpu/armv7/sunxi/usb_phy.c
+++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c
@@ -76,6 +76,7 @@ static int get_vbus_gpio(int index)
case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
+ case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
}
return -EINVAL;
}
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -341,6 +341,12 @@ config USB2_VBUS_PIN
---help---
See USB1_VBUS_PIN help text.
+config USB3_VBUS_PIN
+ string "Vbus enable pin for usb3 (ehci2)"
+ default ""
+ ---help---
+ See USB1_VBUS_PIN help text.
+
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I

31
package/boot/uboot-sunxi/patches/018-usb-specify-vbus-pins-on-orangepis.patch
View file

@ -1,31 +0,0 @@
From ce0d0926758f631fdd655d438acd32d5935d43a4 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Fri, 18 Mar 2016 08:45:21 +0100
Subject: [PATCH] sunxi: Specify USB vbus pins for orangepi boards
This fixes the USB ports not working on the orangepi_plus and stops us
from messing with gpio-s which we should not touch on the orangepi_pc.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
configs/orangepi_pc_defconfig | 3 +++
configs/orangepi_plus_defconfig | 1 +
2 files changed, 4 insertions(+)
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -14,3 +14,6 @@ CONFIG_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB3_VBUS_PIN=""
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -14,3 +14,4 @@ CONFIG_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN="PG13"

33
package/boot/uboot-sunxi/patches/019-sid-add-efuse-support-for-h3-a83t.patch
View file

@ -1,33 +0,0 @@
From 70fe24ed93fa90eb407d18a5fc9d9ad85ac9184c Mon Sep 17 00:00:00 2001
From: Chen-Yu Tsai <wens@csie.org>
Date: Wed, 27 Jan 2016 16:34:43 +0800
Subject: [PATCH] sunxi: Support SID e-fuses on A83T and H3
On the A83T and H3, the SID block is at a different address.
Furthurmore, the e-fuses are at an offset of 0x200 within the
hardware's address space.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -82,7 +82,14 @@
#define SUNXI_AD_DA_BASE 0x01c22c00
#define SUNXI_KEYPAD_BASE 0x01c23000
#define SUNXI_TZPC_BASE 0x01c23400
+
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3)
+/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
+#define SUNXI_SID_BASE 0x01c14200
+#else
#define SUNXI_SID_BASE 0x01c23800
+#endif
+
#define SUNXI_SJTAG_BASE 0x01c23c00
#define SUNXI_TP_BASE 0x01c25000

23
package/boot/uboot-sunxi/patches/020-boot-display-board-model-on-startup.patch
View file

@ -1,23 +0,0 @@
From 2af25b747340c6c8f6a6b9e27632db577bf4da52 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 22 Feb 2016 22:55:46 -0700
Subject: [PATCH] sunxi: Display the board model on start-up
It is useful to know which sunxi board you are booting. Display this on
start-up to avoid confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
include/configs/sunxi-common.h | 1 +
1 file changed, 1 insertion(+)
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -174,6 +174,7 @@
#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
#define CONFIG_IDENT_STRING " Allwinner Technology"
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */

6
package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch
View file

@ -12,9 +12,9 @@ More specifically, the following settings are now used:
* up to 1152MHz: mul=3, div=2 (unchanged)
* above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -122,11 +122,12 @@ void clock_set_pll1(unsigned int clk)
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -107,11 +107,12 @@ void clock_set_pll1(unsigned int clk)
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int p = 0;

15
package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch
View file

@ -16,9 +16,9 @@ order of magnitude as Boot1.
Furthermore, a bit of documentation is added to clarify that the
required setting for the PLL LDO is 1.37v as per the A31 manual.
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -24,14 +24,27 @@ void clock_init_safe(void)
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -26,13 +26,26 @@ void clock_init_safe(void)
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
@ -34,9 +34,9 @@ required setting for the PLL LDO is 1.37v as per the A31 manual.
clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
- PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+ PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370) );
+ PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370));
clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+
+ /* Give the PLL LDO voltage setting some time to take hold.
+ * Notes:
+ * 1) We need to use sdelay() as the timers aren't set up yet.
@ -44,10 +44,9 @@ required setting for the PLL LDO is 1.37v as per the A31 manual.
+ * iterations through a loop.
+ */
+ sdelay(100000);
+
clock_set_pll1(408000000);
#endif
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -111,13 +111,13 @@

4
package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch
View file

@ -6,11 +6,11 @@ Subject: sun6i: define alternate-function for UART2 on GPG
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -180,6 +180,7 @@ enum sunxi_gpio_number {
@@ -186,6 +186,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPG_SDC1 2
#define SUN8I_GPG_SDC1 2
#define SUN6I_GPG_TWI3 2
+#define SUN6I_GPG_UART2 2
#define SUN5I_GPG_UART1 4
#define SUN4I_GPH_SDC1 5
#define SUN6I_GPH_PWM 2

8
package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch
View file

@ -4,9 +4,9 @@ Date: Tue, 16 Jun 2015 10:53:11 +0200
Subject: ARM: sun6i: Support console on UART2 (GPG6/GPG7)
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -88,6 +88,10 @@ static int gpio_init(void)
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -126,6 +126,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
@ -19,7 +19,7 @@ Subject: ARM: sun6i: Support console on UART2 (GPG6/GPG7)
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -260,6 +260,8 @@ extern int soft_i2c_gpio_scl;
@@ -259,6 +259,8 @@ extern int soft_i2c_gpio_scl;
#endif
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"

6
package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch
View file

@ -4,9 +4,9 @@ Date: Tue, 16 Jun 2015 10:59:38 +0200
Subject: ARM: sunxi: Make CONS_INDEX configurable
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -229,6 +229,14 @@ config SYS_BOARD
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -412,6 +412,14 @@ config SYS_BOARD
config SYS_SOC
default "sunxi"