lantiq: Use the new pinctrl compatible strings

These were introduced in upstream commit
be14811c03cf "pinctrl/lantiq: introduce new dedicated devicetree
bindings" and finally allow us to use the individual pins within our dts
(for example spi_clk, etc.).
Please note that this changes the number of GPIOs which are available for
some SoCs. VRX200 SoCs for example only have 50 pins, but previously 56
pins were exposed. This means that all places which are using hardcoded
GPIO numbers (which are not passed via device-tree) need to be adjusted
(because the first GPIO number is now 462, instead of 456).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48284
This commit is contained in:
Felix Fietkau 2016-01-17 19:55:04 +00:00
parent ee03fc430d
commit 1204a1b1e5
4 changed files with 4 additions and 4 deletions

View file

@ -90,7 +90,7 @@
}; };
gpio: pinmux@E100B10 { gpio: pinmux@E100B10 {
compatible = "lantiq,pinctrl-ase"; compatible = "lantiq,ase-pinctrl";
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
reg = <0xE100B10 0xA0>; reg = <0xE100B10 0xA0>;

View file

@ -101,7 +101,7 @@
}; };
gpio: pinmux@E100B10 { gpio: pinmux@E100B10 {
compatible = "lantiq,pinctrl-xr9"; compatible = "lantiq,xrx100-pinctrl";
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
reg = <0xE100B10 0xA0>; reg = <0xE100B10 0xA0>;

View file

@ -123,7 +123,7 @@
}; };
gpio: pinmux@E100B10 { gpio: pinmux@E100B10 {
compatible = "lantiq,pinctrl-xway"; compatible = "lantiq,danube-pinctrl";
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
reg = <0xE100B10 0xA0>; reg = <0xE100B10 0xA0>;

View file

@ -113,7 +113,7 @@
}; };
gpio: pinmux@E100B10 { gpio: pinmux@E100B10 {
compatible = "lantiq,pinctrl-xr9"; compatible = "lantiq,xrx200-pinctrl";
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
reg = <0xE100B10 0xA0>; reg = <0xE100B10 0xA0>;