lantiq: Use the new pinctrl compatible strings
These were introduced in upstream commit be14811c03cf "pinctrl/lantiq: introduce new dedicated devicetree bindings" and finally allow us to use the individual pins within our dts (for example spi_clk, etc.). Please note that this changes the number of GPIOs which are available for some SoCs. VRX200 SoCs for example only have 50 pins, but previously 56 pins were exposed. This means that all places which are using hardcoded GPIO numbers (which are not passed via device-tree) need to be adjusted (because the first GPIO number is now 462, instead of 456). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48284
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4 changed files with 4 additions and 4 deletions
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@ -90,7 +90,7 @@
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};
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};
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gpio: pinmux@E100B10 {
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gpio: pinmux@E100B10 {
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compatible = "lantiq,pinctrl-ase";
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compatible = "lantiq,ase-pinctrl";
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#gpio-cells = <2>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-controller;
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reg = <0xE100B10 0xA0>;
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reg = <0xE100B10 0xA0>;
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@ -101,7 +101,7 @@
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};
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};
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gpio: pinmux@E100B10 {
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gpio: pinmux@E100B10 {
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compatible = "lantiq,pinctrl-xr9";
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compatible = "lantiq,xrx100-pinctrl";
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#gpio-cells = <2>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-controller;
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reg = <0xE100B10 0xA0>;
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reg = <0xE100B10 0xA0>;
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@ -123,7 +123,7 @@
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};
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};
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gpio: pinmux@E100B10 {
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gpio: pinmux@E100B10 {
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compatible = "lantiq,pinctrl-xway";
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compatible = "lantiq,danube-pinctrl";
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#gpio-cells = <2>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-controller;
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reg = <0xE100B10 0xA0>;
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reg = <0xE100B10 0xA0>;
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@ -113,7 +113,7 @@
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};
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};
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gpio: pinmux@E100B10 {
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gpio: pinmux@E100B10 {
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compatible = "lantiq,pinctrl-xr9";
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compatible = "lantiq,xrx200-pinctrl";
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#gpio-cells = <2>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-controller;
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reg = <0xE100B10 0xA0>;
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reg = <0xE100B10 0xA0>;
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