atheros: rework chained interrupts handling
Call generic_handle_irq() instead of do_IRQ() for chained interrupts, remove XXX_NONE interrupts and call spurious_interrupt() when an interrupt is unexpected. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> SVN-Revision: 42510
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0e86c116cb
2 changed files with 47 additions and 47 deletions
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@ -659,7 +659,7 @@
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+#endif /* __ASM_MACH_AR231X_WAR_H */
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
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@@ -0,0 +1,631 @@
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@@ -0,0 +1,630 @@
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+/*
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+ * Register definitions for AR2315+
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+ *
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@ -688,17 +688,16 @@
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+/*
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+ * Miscellaneous interrupts, which share IP2.
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+ */
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+#define AR2315_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
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+#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+1)
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+#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+2)
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+#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+3)
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+#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+4)
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+#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+5)
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+#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+6)
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+#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+7)
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+#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+8)
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+#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
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+#define AR2315_MISC_IRQ_COUNT 10
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+#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
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+#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
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+#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
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+#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
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+#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
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+#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
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+#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
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+#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
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+#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
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+#define AR2315_MISC_IRQ_COUNT 9
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+
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+/*
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+ * PCI interrupts, which share IP5
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@ -1293,7 +1292,7 @@
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+#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
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@@ -0,0 +1,249 @@
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@@ -0,0 +1,247 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -1321,17 +1320,16 @@
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+/*
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+ * Miscellaneous interrupts, which share IP6.
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+ */
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+#define AR5312_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
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+#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+1)
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+#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+2)
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+#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+3)
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+#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+4)
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+#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+5)
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+#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+6)
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+#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
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+#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+8)
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+#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
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+#define AR5312_MISC_IRQ_COUNT 10
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+#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
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+#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
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+#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
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+#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
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+#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
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+#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
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+#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
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+#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
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+#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
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+#define AR5312_MISC_IRQ_COUNT 9
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+
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+/*
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+ * Address Map
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@ -1395,7 +1393,6 @@
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+#define AR5312_WD_CTRL_RESET 0x0002
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+
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+/* AR5312_ISR register bit field definitions */
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+#define AR5312_ISR_NONE 0x0000
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+#define AR5312_ISR_TIMER 0x0001
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+#define AR5312_ISR_AHBPROC 0x0002
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+#define AR5312_ISR_AHBDMA 0x0004
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@ -1545,7 +1542,7 @@
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+#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
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--- /dev/null
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+++ b/arch/mips/ar231x/ar5312.c
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@@ -0,0 +1,534 @@
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@@ -0,0 +1,536 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -1591,16 +1588,16 @@
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+ ar231x_read_reg(AR5312_IMR);
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+
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+ if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
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+ do_IRQ(AR5312_MISC_IRQ_TIMER);
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+ generic_handle_irq(AR5312_MISC_IRQ_TIMER);
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+ (void)ar231x_read_reg(AR5312_TIMER);
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+ } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
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+ do_IRQ(AR5312_MISC_IRQ_AHB_PROC);
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+ generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
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+ else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
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+ do_IRQ(AR5312_MISC_IRQ_UART0);
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+ generic_handle_irq(AR5312_MISC_IRQ_UART0);
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+ else if (ar231x_misc_intrs & AR5312_ISR_WD)
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+ do_IRQ(AR5312_MISC_IRQ_WATCHDOG);
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+ generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
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+ else
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+ do_IRQ(AR5312_MISC_IRQ_NONE);
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+ spurious_interrupt();
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+}
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+
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+static asmlinkage void
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@ -1620,6 +1617,8 @@
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+ do_IRQ(AR5312_IRQ_MISC_INTRS);
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+ else if (pending & CAUSEF_IP7)
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+ do_IRQ(AR231X_IRQ_CPU_CLOCK);
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+ else
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+ spurious_interrupt();
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+}
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+
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+/* Enable the specified AR5312_MISC_IRQ interrupt */
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@ -1629,7 +1628,7 @@
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+ unsigned int imr;
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+
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+ imr = ar231x_read_reg(AR5312_IMR);
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+ imr |= (1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
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+ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
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+ ar231x_write_reg(AR5312_IMR, imr);
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+}
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+
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@ -1640,7 +1639,7 @@
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+ unsigned int imr;
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+
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+ imr = ar231x_read_reg(AR5312_IMR);
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+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
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+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
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+ ar231x_write_reg(AR5312_IMR, imr);
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+ ar231x_read_reg(AR5312_IMR); /* flush write buffer */
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+}
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@ -2082,7 +2081,7 @@
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+
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--- /dev/null
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+++ b/arch/mips/ar231x/ar2315.c
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@@ -0,0 +1,568 @@
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@@ -0,0 +1,570 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -2147,7 +2146,7 @@
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+ return;
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+
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+ if (bit >= 0)
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+ do_IRQ(AR231X_GPIO_IRQ_BASE + bit);
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+ generic_handle_irq(AR231X_GPIO_IRQ_BASE + bit);
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+}
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+
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+static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
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@ -2156,20 +2155,20 @@
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+ ar231x_read_reg(AR2315_IMR);
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+
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+ if (misc_intr & AR2315_ISR_SPI)
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+ do_IRQ(AR2315_MISC_IRQ_SPI);
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+ generic_handle_irq(AR2315_MISC_IRQ_SPI);
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+ else if (misc_intr & AR2315_ISR_TIMER)
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+ do_IRQ(AR2315_MISC_IRQ_TIMER);
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+ generic_handle_irq(AR2315_MISC_IRQ_TIMER);
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+ else if (misc_intr & AR2315_ISR_AHB)
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+ do_IRQ(AR2315_MISC_IRQ_AHB);
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+ generic_handle_irq(AR2315_MISC_IRQ_AHB);
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+ else if (misc_intr & AR2315_ISR_GPIO)
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+ do_IRQ(AR2315_MISC_IRQ_GPIO);
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+ generic_handle_irq(AR2315_MISC_IRQ_GPIO);
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+ else if (misc_intr & AR2315_ISR_UART0)
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+ do_IRQ(AR2315_MISC_IRQ_UART0);
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+ generic_handle_irq(AR2315_MISC_IRQ_UART0);
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+ else if (misc_intr & AR2315_ISR_WD) {
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+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
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+ do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
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+ generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
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+ } else
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+ do_IRQ(AR2315_MISC_IRQ_NONE);
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+ spurious_interrupt();
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+}
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+
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+/*
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@ -2193,6 +2192,8 @@
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+ do_IRQ(AR2315_IRQ_MISC_INTRS);
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+ else if (pending & CAUSEF_IP7)
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+ do_IRQ(AR231X_IRQ_CPU_CLOCK);
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+ else
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+ spurious_interrupt();
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+}
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+
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+static void ar2315_set_gpiointmask(int gpio, int level)
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+ unsigned int imr;
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+
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+ imr = ar231x_read_reg(AR2315_IMR);
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+ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE - 1);
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+ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
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+ ar231x_write_reg(AR2315_IMR, imr);
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+}
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+
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@ -2249,7 +2250,7 @@
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+ unsigned int imr;
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+
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+ imr = ar231x_read_reg(AR2315_IMR);
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+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
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+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
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+ ar231x_write_reg(AR2315_IMR, imr);
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+}
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+
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+#endif
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
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@@ -0,0 +1,39 @@
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@@ -0,0 +1,38 @@
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+#ifndef __ASM_MACH_AR231X_H
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+#define __ASM_MACH_AR231X_H
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+
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+#define AR231X_GPIO_IRQ_BASE 0x30
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+
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+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
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+#define AR231X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
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+#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
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+
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+static inline u32
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@ -382,7 +382,7 @@
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else if (pending & CAUSEF_IP2)
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do_IRQ(AR2315_IRQ_MISC_INTRS);
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else if (pending & CAUSEF_IP7)
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@@ -566,3 +570,18 @@ ar2315_plat_setup(void)
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@@ -568,3 +572,18 @@ ar2315_plat_setup(void)
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ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
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ar2315_apb_frequency());
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}
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