ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
Incorrect value causes clock inaccuracy as huge as 1/60. Signed-off-by: Dmitry Ivanov <dima@ubnt.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 47363
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1 changed files with 2 additions and 2 deletions
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@ -529,7 +529,7 @@
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+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
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+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
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+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
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+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff
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+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
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+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
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+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
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+
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@ -541,7 +541,7 @@
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+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
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+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
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+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
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+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff
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+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
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+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
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+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
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+
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