add support for bcm6345 SoC, needs testing
SVN-Revision: 14953
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08b7cbe44e
commit
0972ee5331
4 changed files with 83 additions and 2 deletions
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@ -14,6 +14,7 @@ CONFIG_BASE_SMALL=0
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# CONFIG_BCM47XX is not set
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CONFIG_BCM63XX=y
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CONFIG_BCM63XX_CPU_6338=y
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CONFIG_BCM63XX_CPU_6345=y
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CONFIG_BCM63XX_CPU_6348=y
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CONFIG_BCM63XX_CPU_6358=y
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CONFIG_BCM63XX_ENET=y
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@ -8,6 +8,11 @@ config BCM63XX_CPU_6338
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select USB_OHCI_BIG_ENDIAN_DESC
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select USB_OHCI_BIG_ENDIAN_MMIO
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config BCM63XX_CPU_6345
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bool "support 6345 CPU"
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select USB_OHCI_BIG_ENDIAN_DESC
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select USB_OHCI_BIG_ENDIAN_MMIO
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config BCM63XX_CPU_6348
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bool "support 6348 CPU"
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select HW_HAS_PCI
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@ -71,6 +71,26 @@ static const unsigned long bcm96338_regs_spi[] = {
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[SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA,
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};
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/*
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* 6345 register sets and irqs
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*/
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static const unsigned long bcm96345_regs_base[] = {
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[RSET_PERF] = BCM_6345_PERF_BASE,
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[RSET_TIMER] = BCM_6345_TIMER_BASE,
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[RSET_WDT] = BCM_6345_WDT_BASE,
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[RSET_UART0] = BCM_6345_UART0_BASE,
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[RSET_GPIO] = BCM_6345_GPIO_BASE,
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};
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static const int bcm96345_irqs[] = {
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[IRQ_TIMER] = BCM_6345_TIMER_IRQ,
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[IRQ_UART0] = BCM_6345_UART0_IRQ,
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[IRQ_DSL] = BCM_6345_DSL_IRQ,
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[IRQ_ENET0] = BCM_6345_ENET0_IRQ,
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[IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
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};
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/*
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* 6348 register sets and irqs
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*/
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@ -217,9 +237,11 @@ static unsigned int detect_cpu_clock(void)
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{
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unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
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if (BCMCPU_IS_6338()) {
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if (BCMCPU_IS_6338())
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return 240000000;
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}
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if (BCMCPU_IS_6345())
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return 140000000;
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/*
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* frequency depends on PLL configuration:
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@ -294,6 +316,11 @@ void __init bcm63xx_cpu_init(void)
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bcm63xx_irqs = bcm96338_irqs;
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bcm63xx_regs_spi = bcm96338_regs_spi;
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break;
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case CPU_BCM6345:
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expected_cpu_id = BCM6345_CPU_ID;
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bcm63xx_regs_base = bcm96345_regs_base;
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bcm63xx_irqs = bcm96345_irqs;
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break;
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case CPU_BCM6348:
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expected_cpu_id = BCM6348_CPU_ID;
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bcm63xx_regs_base = bcm96348_regs_base;
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@ -12,6 +12,7 @@
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* arm mach-types)
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*/
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#define BCM6338_CPU_ID 0x6338
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#define BCM6345_CPU_ID 0x6345
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#define BCM6348_CPU_ID 0x6348
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#define BCM6358_CPU_ID 0x6358
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@ -33,6 +34,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
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# define BCMCPU_IS_6338() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6345
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
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# endif
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# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
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#else
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# define BCMCPU_IS_6345() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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@ -122,6 +136,15 @@ enum bcm63xx_regs_set {
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#define BCM_6338_UDC0_BASE (0xfffe3000) /* USB_CTL_BASE */
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#define BCM_6338_MEMC_BASE (0xfffe3100)
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/*
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* 6345 register sets base address
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*/
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#define BCM_6345_PERF_BASE (0xfffe0000)
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#define BCM_6345_TIMER_BASE (0xfffe0200)
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#define BCM_6345_WDT_BASE (0xfffe021c)
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#define BCM_6345_UART0_BASE (0xfffe0300)
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#define BCM_6345_GPIO_BASE (0xfffe0400)
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/*
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* 6348 register sets base address
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*/
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@ -204,6 +227,20 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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return BCM_6338_MEMC_BASE;
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}
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6345
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switch (set) {
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case RSET_PERF:
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return BCM_6345_PERF_BASE;
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case RSET_TIMER:
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return BCM_6345_TIMER_BASE;
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case RSET_WDT:
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return BCM_6345_WDT_BASE;
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case RSET_UART0:
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return BCM_6345_UART0_BASE;
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case RSET_GPIO:
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return BCM_6345_GPIO_BASE;
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}
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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switch (set) {
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case RSET_DSL_LMEM:
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@ -461,6 +498,17 @@ enum bcm63xx_irq {
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#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
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#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
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/*
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* 6345 irqs
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*/
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#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
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#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
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#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
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#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
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#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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/*
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* 6348 irqs
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*/
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