ramips: register mt7621 pcie through device tree
Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 44009
This commit is contained in:
Felix Fietkau
parent
50a5cd829c
commit
070f67aa9b
2 changed files with 98 additions and 27 deletions
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@ -274,4 +274,53 @@
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interrupt-parent = <&gic>;
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interrupts = <23>;
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};
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pcie@1e140000 {
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compatible = "mediatek,mt7621-pci";
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reg = <0x1e140000 0x100
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0x1e142000 0x100>;
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#address-cells = <3>;
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#size-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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device_type = "pci";
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bus-range = <0 255>;
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ranges = <
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0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
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0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
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>;
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status = "okay";
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pcie0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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};
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pcie1 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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};
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pcie2 {
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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};
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};
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};
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@ -12,7 +12,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -41,6 +41,7 @@
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@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
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obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
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obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
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obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
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@ -22,7 +22,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
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--- /dev/null
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+++ b/arch/mips/pci/pci-mt7621.c
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@@ -0,0 +1,791 @@
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@@ -0,0 +1,813 @@
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+/**************************************************************************
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+ *
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+ * BRIEF MODULE DESCRIPTION
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@ -71,11 +71,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+#include <linux/version.h>
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+#include <asm/pci.h>
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+#include <asm/io.h>
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+//#include <asm/mach-ralink/eureka_ep430.h>
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+#include <linux/init.h>
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+#include <linux/mod_devicetable.h>
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+#include <linux/module.h>
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+#include <linux/delay.h>
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+//#include <asm/rt2880/surfboardint.h>
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+#include <linux/of.h>
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+#include <linux/of_pci.h>
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+#include <linux/platform_device.h>
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+
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+#include <ralink_regs.h>
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+
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@ -210,10 +211,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+#define LC_CKDRVPD_ (1<<19)
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+
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+#define MEMORY_BASE 0x0
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+int pcie_link_status = 0;
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+
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+void __inline__ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val);
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+void __inline__ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val);
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+static int pcie_link_status = 0;
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+
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+#define PCI_ACCESS_READ_1 0
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+#define PCI_ACCESS_READ_2 1
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@ -334,34 +332,34 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ }
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+}
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+
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+struct pci_ops rt2880_pci_ops= {
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+struct pci_ops mt7621_pci_ops= {
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+ .read = pci_config_read,
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+ .write = pci_config_write,
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+};
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+
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+static struct resource rt2880_res_pci_mem1 = {
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+static struct resource mt7621_res_pci_mem1 = {
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+ .name = "PCI MEM1",
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+ .start = RALINK_PCI_MM_MAP_BASE,
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+ .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
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+ .flags = IORESOURCE_MEM,
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+};
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+static struct resource rt2880_res_pci_io1 = {
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+static struct resource mt7621_res_pci_io1 = {
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+ .name = "PCI I/O1",
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+ .start = RALINK_PCI_IO_MAP_BASE,
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+ .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
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+ .flags = IORESOURCE_IO,
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+};
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+
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+struct pci_controller rt2880_controller = {
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+ .pci_ops = &rt2880_pci_ops,
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+ .mem_resource = &rt2880_res_pci_mem1,
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+ .io_resource = &rt2880_res_pci_io1,
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+static struct pci_controller mt7621_controller = {
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+ .pci_ops = &mt7621_pci_ops,
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+ .mem_resource = &mt7621_res_pci_mem1,
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+ .io_resource = &mt7621_res_pci_io1,
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+ .mem_offset = 0x00000000UL,
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+ .io_offset = 0x00000000UL,
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+ .io_map_base = 0xa0000000,
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+};
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+
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+void __inline__
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+static void
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+read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
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+{
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+ unsigned int address_reg, data_reg, address;
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@ -374,7 +372,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ return;
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+}
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+
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+void __inline__
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+static void
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+write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
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+{
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+ unsigned int address_reg, data_reg, address;
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@ -580,13 +578,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+#endif
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+}
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+
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+int init_rt2880pci(void)
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+static int mt7621_pci_probe(struct platform_device *pdev)
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+{
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+ unsigned long val = 0;
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+ iomem_resource.start = 0;
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+ iomem_resource.end= ~0;
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+ ioport_resource.start= 0;
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+ ioport_resource.end = ~0;
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+
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+ iomem_resource.start = 0;
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+ iomem_resource.end= ~0;
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+ ioport_resource.start= 0;
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+ ioport_resource.end = ~0;
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+
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+#if defined (CONFIG_PCIE_PORT0)
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+ val = RALINK_PCIE0_RST;
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@ -740,8 +739,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
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+
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+/*
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+ ioport_resource.start = rt2880_res_pci_io1.start;
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+ ioport_resource.end = rt2880_res_pci_io1.end;
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+ ioport_resource.start = mt7621_res_pci_io1.start;
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+ ioport_resource.end = mt7621_res_pci_io1.end;
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+*/
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+
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+ RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
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@ -804,13 +803,36 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ val |= 0x50<<8;
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+ write_config(0, 0, 0, 0x70c, val);
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+ }
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+ register_pci_controller(&rt2880_controller);
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+
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+ pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
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+ register_pci_controller(&mt7621_controller);
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+ return 0;
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+
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+}
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+arch_initcall(init_rt2880pci);
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+
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+int pcibios_plat_dev_init(struct pci_dev *dev)
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+{
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+ return 0;
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+}
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+
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+static const struct of_device_id mt7621_pci_ids[] = {
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+ { .compatible = "mediatek,mt7621-pci" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
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+
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+static struct platform_driver mt7621_pci_driver = {
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+ .probe = mt7621_pci_probe,
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+ .driver = {
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+ .name = "mt7621-pci",
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+ .owner = THIS_MODULE,
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+ .of_match_table = of_match_ptr(mt7621_pci_ids),
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+ },
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+};
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+
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+static int __init mt7621_pci_init(void)
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+{
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+ return platform_driver_register(&mt7621_pci_driver);
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+}
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+
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+arch_initcall(mt7621_pci_init);
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