532 lines
15 KiB
Diff
532 lines
15 KiB
Diff
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From 8e051b79ae3f66dbad96312fe2976401c28d2148 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sat, 12 Nov 2011 12:19:55 +0100
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Subject: [PATCH 5/5] spi: add bcm63xx HSSPI driver
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Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs.
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It does feature some new modes like 3-wire or dual spi, but neither of it
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is currently implemented.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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drivers/spi/Kconfig | 7 +
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drivers/spi/Makefile | 1 +
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drivers/spi/spi-bcm63xx-hsspi.c | 484 ++++++++++++++++++++++++++++++++++++++++
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3 files changed, 492 insertions(+)
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create mode 100644 drivers/spi/spi-bcm63xx-hsspi.c
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -112,6 +112,13 @@ config SPI_BCM63XX
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help
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Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
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+config SPI_BCM63XX_HSSPI
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+ tristate "Broadcom BCM63XX HS SPI controller driver"
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+ depends on BCM63XX || COMPILE_TEST
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+ help
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+ This enables support for the High Speed SPI controller present on
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+ newer Broadcom BCM63XX SoCs.
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+
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config SPI_BITBANG
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tristate "Utilities for Bitbanging SPI masters"
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help
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -16,6 +16,7 @@ obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
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obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
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obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
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obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
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+obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
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obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
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obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
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obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
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--- /dev/null
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+++ b/drivers/spi/spi-bcm63xx-hsspi.c
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@@ -0,0 +1,484 @@
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+/*
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+ * Broadcom BCM63XX High Speed SPI Controller driver
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+ *
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+ * Copyright 2000-2010 Broadcom Corporation
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+ * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/clk.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/delay.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/err.h>
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+#include <linux/interrupt.h>
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+#include <linux/spi/spi.h>
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+#include <linux/workqueue.h>
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+#include <linux/mutex.h>
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+
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+#define HSSPI_GLOBAL_CTRL_REG 0x0
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+#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
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+#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
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+#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
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+#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
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+#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
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+#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
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+#define GLOBAL_CTRL_MOSI_IDLE BIT(18)
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+
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+#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
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+
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+#define HSSPI_INT_STATUS_REG 0x8
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+#define HSSPI_INT_STATUS_MASKED_REG 0xc
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+#define HSSPI_INT_MASK_REG 0x10
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+
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+#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
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+#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
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+#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
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+#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
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+#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
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+
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+#define HSSPI_INT_CLEAR_ALL 0xff001f1f
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+
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+#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
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+#define PINGPONG_CMD_COMMAND_MASK 0xf
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+#define PINGPONG_COMMAND_NOOP 0
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+#define PINGPONG_COMMAND_START_NOW 1
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+#define PINGPONG_COMMAND_START_TRIGGER 2
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+#define PINGPONG_COMMAND_HALT 3
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+#define PINGPONG_COMMAND_FLUSH 4
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+#define PINGPONG_CMD_PROFILE_SHIFT 8
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+#define PINGPONG_CMD_SS_SHIFT 12
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+
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+#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
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+
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+#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
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+#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
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+#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
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+#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
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+
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+#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
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+#define SIGNAL_CTRL_LATCH_RISING BIT(12)
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+#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
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+#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
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+
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+#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
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+#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
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+#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
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+#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
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+#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
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+#define MODE_CTRL_MODE_3WIRE BIT(20)
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+#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
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+
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+#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
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+
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+
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+#define HSSPI_OP_CODE_SHIFT 13
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+#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
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+#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
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+#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
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+#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
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+#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
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+
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+#define HSSPI_BUFFER_LEN 512
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+#define HSSPI_OPCODE_LEN 2
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+
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+#define HSSPI_MAX_PREPEND_LEN 15
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+
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+#define HSSPI_MAX_SYNC_CLOCK 30000000
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+
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+#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
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+
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+struct bcm63xx_hsspi {
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+ struct completion done;
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+ struct mutex bus_mutex;
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+
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+ struct platform_device *pdev;
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+ struct clk *clk;
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+ void __iomem *regs;
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+ u8 __iomem *fifo;
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+
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+ u32 speed_hz;
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+ u8 cs_polarity;
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+};
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+
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+static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs,
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+ bool active)
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+{
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+ u32 reg;
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+
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+ mutex_lock(&bs->bus_mutex);
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+ reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
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+
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+ reg &= ~BIT(cs);
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+ if (active == !(bs->cs_polarity & BIT(cs)))
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+ reg |= BIT(cs);
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+
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+ __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
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+ mutex_unlock(&bs->bus_mutex);
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+}
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+
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+static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
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+ struct spi_device *spi, int hz)
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+{
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+ unsigned profile = spi->chip_select;
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+ u32 reg;
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+
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+ reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
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+ __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
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+ bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
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+
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+ reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
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+ if (hz > HSSPI_MAX_SYNC_CLOCK)
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+ reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
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+ else
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+ reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
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+ __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
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+
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+ mutex_lock(&bs->bus_mutex);
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+ /* setup clock polarity */
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+ reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
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+ reg &= ~GLOBAL_CTRL_CLK_POLARITY;
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+ if (spi->mode & SPI_CPOL)
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+ reg |= GLOBAL_CTRL_CLK_POLARITY;
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+ __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
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+ mutex_unlock(&bs->bus_mutex);
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+}
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+
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+static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
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+{
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+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
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+ unsigned chip_select = spi->chip_select;
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+ u16 opcode = 0;
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+ int pending = t->len;
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+ int step_size = HSSPI_BUFFER_LEN;
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+ const u8 *tx = t->tx_buf;
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+ u8 *rx = t->rx_buf;
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+
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+ bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
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+ bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
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+
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+ if (tx && rx)
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+ opcode = HSSPI_OP_READ_WRITE;
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+ else if (tx)
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+ opcode = HSSPI_OP_WRITE;
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+ else if (rx)
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+ opcode = HSSPI_OP_READ;
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+
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+ if (opcode != HSSPI_OP_READ)
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+ step_size -= HSSPI_OPCODE_LEN;
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+
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+ __raw_writel(0 << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
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+ 2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
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+ 2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
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+ bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
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+
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+ while (pending > 0) {
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+ int curr_step = min_t(int, step_size, pending);
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+
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+ init_completion(&bs->done);
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+ if (tx) {
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+ memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
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+ tx += curr_step;
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+ }
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+
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+ __raw_writew(opcode | curr_step, bs->fifo);
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+
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+ /* enable interrupt */
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+ __raw_writel(HSSPI_PINGx_CMD_DONE(0),
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+ bs->regs + HSSPI_INT_MASK_REG);
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+
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+ /* start the transfer */
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+ __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
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+ chip_select << PINGPONG_CMD_PROFILE_SHIFT |
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+ PINGPONG_COMMAND_START_NOW,
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+ bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
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+
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+ if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
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+ dev_err(&bs->pdev->dev, "transfer timed out!\n");
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+ return -ETIMEDOUT;
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+ }
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+
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+ if (rx) {
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+ memcpy_fromio(rx, bs->fifo, curr_step);
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+ rx += curr_step;
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+ }
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+
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+ pending -= curr_step;
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+ }
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+
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+ return 0;
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+}
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+
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+static int bcm63xx_hsspi_setup(struct spi_device *spi)
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+{
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+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
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+ u32 reg;
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+
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+ reg = __raw_readl(bs->regs +
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+ HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
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+ reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
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+ if (spi->mode & SPI_CPHA)
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+ reg |= SIGNAL_CTRL_LAUNCH_RISING;
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+ else
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+ reg |= SIGNAL_CTRL_LATCH_RISING;
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+ __raw_writel(reg, bs->regs +
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+ HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
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+
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+ mutex_lock(&bs->bus_mutex);
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+ reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
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+
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+ /* only change actual polarities if there is no transfer */
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+ if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
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+ if (spi->mode & SPI_CS_HIGH)
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+ reg |= BIT(spi->chip_select);
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+ else
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+ reg &= ~BIT(spi->chip_select);
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+ __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
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+ }
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+
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+ if (spi->mode & SPI_CS_HIGH)
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+ bs->cs_polarity |= BIT(spi->chip_select);
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+ else
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+ bs->cs_polarity &= ~BIT(spi->chip_select);
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+
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+ mutex_unlock(&bs->bus_mutex);
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+
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+ return 0;
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+}
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+
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+static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
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+ struct spi_message *msg)
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+{
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+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
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+ struct spi_transfer *t;
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+ struct spi_device *spi = msg->spi;
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+ int status = -EINVAL;
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+ int dummy_cs;
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+ u32 reg;
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+
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+ /* This controller does not support keeping CS active during idle.
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+ * To work around this, we use the following ugly hack:
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+ *
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+ * a. Invert the target chip select's polarity so it will be active.
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+ * b. Select a "dummy" chip select to use as the hardware target.
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+ * c. Invert the dummy chip select's polarity so it will be inactive
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+ * during the actual transfers.
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+ * d. Tell the hardware to send to the dummy chip select. Thanks to
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+ * the multiplexed nature of SPI the actual target will receive
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+ * the transfer and we see its response.
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+ *
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+ * e. At the end restore the polarities again to their default values.
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+ */
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+
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+ dummy_cs = !spi->chip_select;
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+ bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
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+
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+ list_for_each_entry(t, &msg->transfers, transfer_list) {
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+ status = bcm63xx_hsspi_do_txrx(spi, t);
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+ if (status)
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+ break;
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+
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+ msg->actual_length += t->len;
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+
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+ if (t->delay_usecs)
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+ udelay(t->delay_usecs);
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+
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+ if (t->cs_change)
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+ bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
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+ }
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+
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+ mutex_lock(&bs->bus_mutex);
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+ reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
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+ reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
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+ reg |= bs->cs_polarity;
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+ __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
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+ mutex_unlock(&bs->bus_mutex);
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+
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+ msg->status = status;
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+ spi_finalize_current_message(master);
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+
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+ return 0;
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+}
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+
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+static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
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+{
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+ struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
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+
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||
|
+ if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
|
||
|
+ return IRQ_NONE;
|
||
|
+
|
||
|
+ __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
|
||
|
+ __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
|
||
|
+
|
||
|
+ complete(&bs->done);
|
||
|
+
|
||
|
+ return IRQ_HANDLED;
|
||
|
+}
|
||
|
+
|
||
|
+static int bcm63xx_hsspi_probe(struct platform_device *pdev)
|
||
|
+{
|
||
|
+ struct spi_master *master;
|
||
|
+ struct bcm63xx_hsspi *bs;
|
||
|
+ struct resource *res_mem;
|
||
|
+ void __iomem *regs;
|
||
|
+ struct device *dev = &pdev->dev;
|
||
|
+ struct clk *clk;
|
||
|
+ int irq, ret;
|
||
|
+ u32 reg, rate;
|
||
|
+
|
||
|
+ irq = platform_get_irq(pdev, 0);
|
||
|
+ if (irq < 0) {
|
||
|
+ dev_err(dev, "no irq\n");
|
||
|
+ return -ENXIO;
|
||
|
+ }
|
||
|
+
|
||
|
+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
+ regs = devm_request_and_ioremap(dev, res_mem);
|
||
|
+ if (IS_ERR(regs))
|
||
|
+ return PTR_ERR(regs);
|
||
|
+
|
||
|
+ clk = clk_get(dev, "hsspi");
|
||
|
+
|
||
|
+ if (IS_ERR(clk))
|
||
|
+ return PTR_ERR(clk);
|
||
|
+
|
||
|
+ rate = clk_get_rate(clk);
|
||
|
+ if (!rate) {
|
||
|
+ ret = -EINVAL;
|
||
|
+ goto out_put_clk;
|
||
|
+ }
|
||
|
+
|
||
|
+ clk_prepare_enable(clk);
|
||
|
+
|
||
|
+ master = spi_alloc_master(&pdev->dev, sizeof(*bs));
|
||
|
+ if (!master) {
|
||
|
+ ret = -ENOMEM;
|
||
|
+ goto out_disable_clk;
|
||
|
+ }
|
||
|
+
|
||
|
+ bs = spi_master_get_devdata(master);
|
||
|
+ bs->pdev = pdev;
|
||
|
+ bs->clk = clk;
|
||
|
+ bs->regs = regs;
|
||
|
+ bs->speed_hz = rate;
|
||
|
+ bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
|
||
|
+
|
||
|
+ mutex_init(&bs->bus_mutex);
|
||
|
+
|
||
|
+ master->bus_num = HSSPI_BUS_NUM;
|
||
|
+ master->num_chipselect = 8;
|
||
|
+ master->setup = bcm63xx_hsspi_setup;
|
||
|
+ master->transfer_one_message = bcm63xx_hsspi_transfer_one;
|
||
|
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
||
|
+ master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||
|
+ master->auto_runtime_pm = true;
|
||
|
+
|
||
|
+ platform_set_drvdata(pdev, master);
|
||
|
+
|
||
|
+ /* Initialize the hardware */
|
||
|
+ __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
|
||
|
+
|
||
|
+ /* clean up any pending interrupts */
|
||
|
+ __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
|
||
|
+
|
||
|
+ /* read out default CS polarities */
|
||
|
+ reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
|
||
|
+ bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
|
||
|
+ __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
|
||
|
+ bs->regs + HSSPI_GLOBAL_CTRL_REG);
|
||
|
+
|
||
|
+ ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
|
||
|
+ pdev->name, bs);
|
||
|
+
|
||
|
+ if (ret)
|
||
|
+ goto out_put_master;
|
||
|
+
|
||
|
+ /* register and we are done */
|
||
|
+ ret = spi_register_master(master);
|
||
|
+ if (ret)
|
||
|
+ goto out_put_master;
|
||
|
+
|
||
|
+ return 0;
|
||
|
+
|
||
|
+out_put_master:
|
||
|
+ spi_master_put(master);
|
||
|
+out_disable_clk:
|
||
|
+ clk_disable_unprepare(clk);
|
||
|
+out_put_clk:
|
||
|
+ clk_put(clk);
|
||
|
+
|
||
|
+ return ret;
|
||
|
+}
|
||
|
+
|
||
|
+
|
||
|
+static int bcm63xx_hsspi_remove(struct platform_device *pdev)
|
||
|
+{
|
||
|
+ struct spi_master *master = platform_get_drvdata(pdev);
|
||
|
+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
|
||
|
+
|
||
|
+ spi_unregister_master(master);
|
||
|
+
|
||
|
+ /* reset the hardware and block queue progress */
|
||
|
+ __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
|
||
|
+ clk_disable_unprepare(bs->clk);
|
||
|
+ clk_put(bs->clk);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+#ifdef CONFIG_PM
|
||
|
+static int bcm63xx_hsspi_suspend(struct device *dev)
|
||
|
+{
|
||
|
+ struct spi_master *master = dev_get_drvdata(dev);
|
||
|
+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
|
||
|
+
|
||
|
+ spi_master_suspend(master);
|
||
|
+ clk_disable(bs->clk);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int bcm63xx_hsspi_resume(struct device *dev)
|
||
|
+{
|
||
|
+ struct spi_master *master = dev_get_drvdata(dev);
|
||
|
+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
|
||
|
+
|
||
|
+ clk_enable(bs->clk);
|
||
|
+ spi_master_resume(master);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = {
|
||
|
+ .suspend = bcm63xx_hsspi_suspend,
|
||
|
+ .resume = bcm63xx_hsspi_resume,
|
||
|
+};
|
||
|
+
|
||
|
+#define BCM63XX_HSSPI_PM_OPS (&bcm63xx_hsspi_pm_ops)
|
||
|
+#else
|
||
|
+#define BCM63XX_HSSPI_PM_OPS NULL
|
||
|
+#endif
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+static struct platform_driver bcm63xx_hsspi_driver = {
|
||
|
+ .driver = {
|
||
|
+ .name = "bcm63xx-hsspi",
|
||
|
+ .owner = THIS_MODULE,
|
||
|
+ .pm = BCM63XX_HSSPI_PM_OPS,
|
||
|
+ },
|
||
|
+ .probe = bcm63xx_hsspi_probe,
|
||
|
+ .remove = bcm63xx_hsspi_remove,
|
||
|
+};
|
||
|
+
|
||
|
+module_platform_driver(bcm63xx_hsspi_driver);
|
||
|
+
|
||
|
+MODULE_ALIAS("platform:bcm63xx_hsspi");
|
||
|
+MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
|
||
|
+MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
|
||
|
+MODULE_LICENSE("GPL");
|