68 lines
2 KiB
Diff
68 lines
2 KiB
Diff
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From 0eba511a3cac29d6338b22b5b727f40cf8d163df Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Wed, 31 May 2017 09:18:38 +0200
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Subject: arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driver
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The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000
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speed.
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This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree.
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SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 34 ++++++++++++++++++++++++++++++++++
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1 file changed, 34 insertions(+)
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--- a/arch/arm/boot/dts/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
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@@ -333,6 +333,14 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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+ emac_rgmii_pins: emac0 {
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+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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+ "PD5", "PD7", "PD8", "PD9", "PD10",
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+ "PD12", "PD13", "PD15", "PD16", "PD17";
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+ function = "emac";
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+ drive-strength = <40>;
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+ };
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+
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i2c0_pins: i2c0 {
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allwinner,pins = "PA11", "PA12";
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allwinner,function = "i2c0";
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@@ -431,6 +439,32 @@
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clocks = <&osc24M>;
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};
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+ emac: ethernet@1c30000 {
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+ compatible = "allwinner,sun8i-h3-emac";
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+ syscon = <&syscon>;
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+ reg = <0x01c30000 0x104>;
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+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+ resets = <&ccu RST_BUS_EMAC>;
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+ reset-names = "stmmaceth";
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+ clocks = <&ccu CLK_BUS_EMAC>;
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+ clock-names = "stmmaceth";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+
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+ mdio: mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ int_mii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ clocks = <&ccu CLK_BUS_EPHY>;
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+ resets = <&ccu RST_BUS_EPHY>;
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+ };
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+ };
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+ };
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+
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wdt0: watchdog@01c20ca0 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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