62 lines
1.6 KiB
Diff
62 lines
1.6 KiB
Diff
|
From 4d805af8246efdc330d6af9a8bd10ce892327598 Mon Sep 17 00:00:00 2001
|
||
|
|
From: John Crispin <blogic@openwrt.org>
|
||
|
|
Date: Fri, 24 Jan 2014 17:01:17 +0100
|
||
|
|
Subject: [PATCH 03/53] MIPS: ralink: cleanup early_printk
|
||
|
|
|
||
|
|
Add support for the new MT7621/8 SoC and kill ifdefs.
|
||
|
|
Cleanup some whitespace error while we are at it.
|
||
|
|
|
||
|
|
Signed-off-by: John Crispin <blogic@openwrt.org>
|
||
|
|
---
|
||
|
|
arch/mips/ralink/early_printk.c | 25 +++++++++++++++++++++++++
|
||
|
|
1 file changed, 25 insertions(+)
|
||
|
|
|
||
|
|
--- a/arch/mips/ralink/early_printk.c
|
||
|
|
+++ b/arch/mips/ralink/early_printk.c
|
||
|
|
@@ -25,11 +25,13 @@
|
||
|
|
#define MT7628_CHIP_NAME1 0x20203832
|
||
|
|
|
||
|
|
#define UART_REG_TX 0x04
|
||
|
|
+#define UART_REG_LCR 0x0c
|
||
|
|
#define UART_REG_LSR 0x14
|
||
|
|
#define UART_REG_LSR_RT2880 0x1c
|
||
|
|
|
||
|
|
static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
|
||
|
|
static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
|
||
|
|
+static int init_complete;
|
||
|
|
|
||
|
|
static inline void uart_w32(u32 val, unsigned reg)
|
||
|
|
{
|
||
|
|
@@ -47,8 +49,31 @@ static inline int soc_is_mt7628(void)
|
||
|
|
(__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
|
||
|
|
}
|
||
|
|
|
||
|
|
+static inline void find_uart_base(void)
|
||
|
|
+{
|
||
|
|
+ int i;
|
||
|
|
+
|
||
|
|
+ if (!soc_is_mt7628())
|
||
|
|
+ return;
|
||
|
|
+
|
||
|
|
+ for (i = 0; i < 3; i++) {
|
||
|
|
+ u32 reg = uart_r32(UART_REG_LCR + (0x100 * i));
|
||
|
|
+
|
||
|
|
+ if (!reg)
|
||
|
|
+ continue;
|
||
|
|
+
|
||
|
|
+ uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + (0x100 * i));
|
||
|
|
+ break;
|
||
|
|
+ }
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
void prom_putchar(unsigned char ch)
|
||
|
|
{
|
||
|
|
+ if (!init_complete) {
|
||
|
|
+ find_uart_base();
|
||
|
|
+ init_complete = 1;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
|
||
|
|
uart_w32(ch, UART_TX);
|
||
|
|
while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
|